KR101155113B1 - Non volatile memory device and method of operating the same - Google Patents

Abstract

The present invention provides a memory cell array including memory cells connected to bit lines and word lines to store data; A page buffer unit connected to one or more bit lines of the bit lines and including page buffers for temporarily storing data to be stored in the memory cells or reading and storing data stored in the memory cells; And a control unit including an address counting unit for generating an address signal according to a clock signal, and a clock unit generating the clock signal and controlling whether the clock signal is generated according to a counting operation state of the address counting unit. It provides a nonvolatile memory device and a method of operating the same.

Description

Nonvolatile memory device and method of operation

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device for controlling clock generation after column counting at data input and a method of operating the same.

There is an increasing demand for nonvolatile memory devices that can be electrically programmed and erased and that data can be stored without being erased even when power is not supplied. In order to develop a large-capacity memory device capable of storing a large number of data, high integration technology of memory cells has been developed. A nonvolatile memory device includes a plurality of memory cells connected in series to form a string, and the plurality of strings include a memory cell array.

A string of a nonvolatile memory device has a structure in which a plurality of memory cells are connected in series between a bit line and a source line. Due to this string structure, the number of contacts of the bit line and the source line is reduced, and the memory cell can be made smaller to realize a high capacity memory. However, as the size of the memory cell decreases, the access speed is slow because the current of the memory cell is very small.

To overcome this, the program and data reads are performed in units of pages in the nonvolatile memory device.

1 illustrates a portion of a nonvolatile memory device.

Referring to FIG. 1, the nonvolatile memory device 100 includes a memory cell array 110 and a page buffer unit 120.

The memory cell array 110 includes memory cells for data storage. The memory cells are connected in a cell string structure to be connected to bit lines and also to word lines.

In the nonvolatile memory device, a program or data read is performed in units of pages configured in units of word lines. In this case, a buffer means is required to temporarily receive data to be programmed into memory cells in a page unit from outside, or temporarily store data read from the memory cells in a page unit.

The page buffer unit 120 includes page buffer circuits which are the above buffer means.

The page buffer unit 120 performs a program or data read operation on the memory cell array 110 in units of one page.

2 illustrates some of pins for signal input of a memory chip including a nonvolatile memory device.

2, the memory chip 200 includes one or more memory devices 100. The memory chip 200 receives an external control signal through a plurality of pins.

The pin shown in FIG. 2 shows only some control signal input pins for program or data read, and the pins in the memory chip 200 include a chip enable signal (Chip Enable; / CE) and a write enable signal ( Write Enable (/ WE), Read Enable Signal (Read Enable; / RE), Address Latch Enable Signal (ALE), Command Latch Enable Signal (CLE), Write Protect Signal (Write) Protect (/ WP), Ready Busy (R / B), and input / output pins (IO0 to IO7).

The memory chip 200 uses input / output pins IO0 to IO7 in common without a separate input pin for command, address, and data input. Therefore, while the instruction is being input, the instruction latch enable signal CLE is inputted at a high level to distinguish the instruction from being input. While the address is input, the address latch enable signal ALE is inputted at a high level so that the address is inputted. It distinguishes that it is being input.

In addition, while the command latch enable signal CLE and the address latch enable signal ALE are input at a low level, it is determined that data to be programmed is input.

The data input inputs the write enable signal / WE as a toggle signal, and then sequentially inputs data into the page buffer according to the toggle of the write enable signal / WE.

In this case, the nonvolatile memory device 100 counts column addresses divided by bit lines, and data is sequentially input to the page buffer according to the counted column addresses.

3 shows a clock signal while data is input.

Referring to FIG. 3, in the nonvolatile memory device 100, a clock signal CNTCK is generated internally in accordance with a toggle of the write enable signal / WE. Column counting is performed according to the clock signal to output a column address INT_COL, and data is input to a page buffer connected to a column corresponding to the column address INT_COL.

On the other hand, when counting to the last column address, counting is stopped by the counting end signal CNT_END because there are no more columns to count.

However, as shown in FIG. 3, only the counting of the column address INT_COL is stopped by the column counting end signal CNT_END. In particular, even after the data of the page buffer corresponding to the last column address is output, if the write enable signal / WE is continuously toggled and output, the unnecessary operation of continuously generating the internal clock signal CNTCK continues.

Accordingly, an aspect of the present invention is to provide a nonvolatile memory device and a method of operating the same, which stops generation of an internal clock signal when a column address counted to read and output programmed data is counted to the end.

Nonvolatile memory device according to a feature of the present invention,

A memory cell array connected to bit lines and word lines and including memory cells for storing data; A page buffer unit connected to one or more bit lines of the bit lines and including page buffers for temporarily storing data to be stored in the memory cells or reading and storing data stored in the memory cells; A controller including a clock unit configured to generate first and second clock signals and to control whether the clock signal is generated according to a counting operation state of the address counting unit; And an address counting unit for generating an address signal according to the second clock signal, wherein the address counting unit comprises: an address mux for outputting a start column address for data reading using address information input for reading the data; A column counter for outputting an address signal by performing column address counting from the start column address according to the second clock signal; A counter termination logic that determines whether the address signal is a last column address and outputs a first control signal for terminating counting; And an enable controller configured to output an enable signal for controlling the operation of the column counter according to the first control signal and the counting enable signal.

The clock unit may include: a mux for outputting a first clock signal using a command selection signal input according to a read command and a read enable signal; And a clock control unit configured to output the first clock signal as the second clock signal according to the first control signal, or to fix the second clock signal to have a fixed logic level.

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When the first control signal is input at the first logic level indicating the end of counting, the clock controller outputs the second clock signal at the predetermined constant logic level regardless of the input of the first clock signal. do.

The clock controller may include: a first logic calculator configured to perform a NAND logic operation on the command selection signal and the first control signal to output a second control signal; And a second logic operation unit outputting the first clock signal as the second clock signal according to the second control signal, or fixing and outputting the second clock signal to have the set logic level signal.

Nonvolatile memory device according to a feature of the present invention,

A memory cell array connected to bit lines and word lines and including memory cells for storing data; A page buffer unit connected to one or more bit lines of the bit lines and including page buffers for temporarily storing data to be stored in the memory cells or reading and storing data stored in the memory cells; And a control unit configured to generate an address signal in response to a second clock signal generated according to the first clock signal and the first control signal, and to control the second clock signal to be fixed to a predetermined logic level when the address signal is the last address. It includes.

The control unit may include a clock generation unit configured to generate the first clock signal using a command selection signal inputted according to a read command and a read enable signal; A clock controller configured to output the first clock signal as the second clock signal according to the first control signal, or to control the second clock signal to be fixed at a predetermined logic level; And an address counting unit generating an address signal in response to the second clock signal.

The address counting unit may include: an address mux for outputting a start column address for data reading using address information input for data reading; A column counter for outputting the address signal by performing column address counting from the start column address according to the second clock signal; A counter termination logic that determines whether the address signal is a last address and outputs the first control signal for terminating counting; And an enable controller configured to output an enable signal for controlling the operation of the counter according to the first control signal and the counting enable signal.

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The clock control unit outputs the first clock signal as the second clock signal when the first control signal is input at the first logic level, and inputs the second control level at the second logic level indicating the end of counting. When the first clock signal is input, the second clock signal is fixed and output at a predetermined constant logic level.

The clock controller may include: a first logic calculator configured to perform a NAND logic operation on the command selection signal and the first control signal to output a second control signal; And a second logic operation unit outputting the first clock signal as the second clock signal according to the second control signal, or fixing and outputting the second clock signal to have the set logic level signal.

Method of operating a nonvolatile memory device according to another aspect of the present invention,

Providing a control unit for generating a clock signal and performing column address counting to output data read in column units according to a data read command input to the nonvolatile memory device; Confirming a start column address using address information input together with the data read command, performing column address counting from the start column address according to the clock signal, and outputting the read data in accordance with the column address counting step; Checking whether a last column address is counted while performing the column address counting; And if the last column address is counted, stopping the counting operation and outputting a control signal for stopping the clock signal generation.

The clock signal is fixed to a set logic level by the control signal.

As described above, the nonvolatile memory device and the method of operating the same according to the present invention can prevent unnecessary power consumption by controlling not to generate a clock signal generated when the read data is output when the column address counting is stopped. .

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

4A illustrates a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 4A, a nonvolatile memory device 400 according to an embodiment of the present invention includes a memory cell array 410, a page buffer unit 420, a Y decoder 430, and a controller 440.

The memory cell array 410 includes memory cells for program storage. Memory cells are connected to bit lines and word lines.

The page buffer unit 420 includes page buffers connected to one or more bit lines. The page buffer temporarily stores data to be programmed or temporarily stores data read from memory cells.

The Y decoder 430 provides a data input / output path of the page buffer. The Y decoder 430 selects a page buffer according to a signal provided from the controller 440 and provides a path for inputting or outputting data.

The controller 440 interprets the input command to control operation for reading a program or data. In addition, in the embodiment of the present invention, the control unit 440 outputs a control signal for sequentially outputting the input data to output the read data from the page buffer according to the address counting signal, while address counting to the last column address is performed. When complete, the clock signal is no longer generated.

The control unit 440 will be described in more detail as follows.

4B illustrates the controller of FIG. 4A.

Referring to FIG. 4B, the controller 440 may include a buffer 441, a register 442, an address mux 443, a column counter 444, a mux 445, a clock control unit 446, and an enable control unit 447. Counter end logic 448 and command decoder 449.

The buffer 441, the register 442, the address mux 443, the column counter 444, the enable control unit 447, and the counter termination logic 448 perform column address counting, control a counting operation, The mux 445 and the clock controller 446 generate and control an operation clock.

The command decoder 449 decodes an input command and outputs a command selection signal RDSEL according to the input command. In an embodiment of the present invention, the command selection signal RDSEL is output at a high level when a read command is input.

The buffer 441 temporarily stores the input data PADIN <7: 0> input from the input / output pins IO <7: 0> according to the write enable signal / WE. The register 442 temporarily stores only input data PADIN <7: 0> input while the address latch enable signal ALE is input. While the address latch enable signal ALE is at a high level, the input data PADIN <7: 0> input to the register 442 is classified as address information.

The address information stored in the register 442 is transferred to the address mux 443 through the input bus INPUTBUS <7: 0>.

The address mux 443 divides the address information into row address information and column address information, and generates a start column address COL4LOAD <12: 0> using the column address information to generate a column counter 444. To pass).

The column counter 444 starts to operate by the enable signal ENABLE, and counts column addresses according to the second clock signal CNTCK2 from the start column address COL4LOAD <12: 0> to the address signal INT_COL <12. : 0>) Column address counting means incrementing the column address by one from the starting column address COL4LOAD <12: 0>.

If the column address counting continues, at some point it counts to the last column address. After the column address counting is completed up to the last column address, since there is no column address to count, the operation is stopped without performing further column address counting.

The mux 445 receives a write enable signal / WE and a read enable signal / RE, and according to the command select signal RDSEL provided from the command decoder 449, the write enable signal / WE. Alternatively, the read enable signal / RE is selected and output as the first clock CNTCK1. The command selection signal RDSEL is input at a high level when a read command is input. Accordingly, the mux 445 outputs the read enable signal / RE to the first clock CNTCK1. The read enable signal / RE is a signal that is continuously toggled.

The clock controller 446 receives the first clock signal CNTCK1, the counting end signal CNT_END, and the command selection signal RDSEL, and receives the first clock signal CNTCK1 while the counting end signal CNT_END is at a low level. The second clock signal CNTCK2 is output.

The counter termination logic 448 determines whether the address signal INT_COL <12: 0> output from the column counter 444 is the last column address, and the last column address is the address signal INT_COL <12: 0>. When output, the counting end signal CNT_END is output at a high level.

The enable control unit 447 outputs the enable signal ENABLE to the high level by the counting enable signal CNTEN, and outputs the enable signal ENABLE to the low level when the counting end signal CNT_END is input to the high level. Change to

That is, the column counter 444 terminates the counting operation by the counting end signal CNT_END. In addition, the clock control unit 446 does not generate the second clock signal CNTCK2 due to the counting end signal CNT_END.

As shown in FIG. 4B, the clock controller 446 includes a NAND gate NA, first and second inverters IN1 and IN2, and a NOR gate NOR.

The command select signal RDSEL and the counting end signal CNT_END are input to the NAND gate NA. The output of the NAND gate NA is input to the first inverter IN1. The output of the first inverter IN1 is input to the NOR gate NOR.

The first clock signal CNTCK1 is input to another input terminal of the NOR gate NOR.

The output of the NOR gate NOR is input to the second inverter IN2. The output of the second inverter IN2 is the second clock signal CNTCK2.

The process of outputting the read data to the outside by outputting the address signal INT_COL from the controller 44 will be described in more detail as follows.

5 is a timing diagram illustrating an address signal output according to an exemplary embodiment of the present invention.

First, in order to read data, an external read command and address information are input to input data PADIN <7: 0> through input / output pins IO <7: 0>.

At this time, a command latch enable signal (CLE) is input at a high level while a command is input, and an address latch enable signal ALE is input at a high level while address information is input.

The input data PADIN <7: 0> is input to the instruction decoder 449 while the instruction latch enable signal CLE is input, and the input data PADIN <while the address latch enable signal ALE is at a high level. 7: 0>) is passed through the buffer 441 to the register 442 and temporarily stored.

The register 442 stores input data input while the address latch enable signal ALE is at a high level.

The input data PADIN <7: 0>, which is stored address information, is transmitted through the input bus INPUTBUS <7: 0>.

The address mux 443 may use a row address of the address information, which is the input data PADIN <7: 0> transmitted through the input bus INPUTBUS <7: 0>, for data reading, and the column ( Column) provides the column counter 444 as a starting column address (COL4LOAD <12: 0>) for data output.

For the data read operation using the row address, since a data read process of the nonvolatile memory device is already known, a detailed description thereof will be omitted.

When data reading is completed, the column counter 444 starts counting column addresses from the start column address COL4LOAD <12: 0> for outputting data, and outputs an address signal INT_COL <12: 0>.

In this case, in order to start counting, the enable signal ENABLE should be input at a high level, and address counting is performed in synchronization with the second clock signal CNTCK2 output from the clock controller 446.

Since the start column address COL4LOAD <12: 0> is not the last column address when the first counting is started, the counter end logic 448 outputs the counting end signal CNT_END at a low level.

A read enable signal (/ RE) is input as a toggle signal for data output. The command decoder 449 inputs the command selection signal RDSEL to the mux 445 at a high level because a read command is input.

The mux 445 outputs the read enable signal / RE as the first clock signal CNTCK1 according to the high level command selection signal RDSEL.

The clock controller 446 receives the first clock signal CNTCK1, the counting end signal CNT_END, and the command selection signal RDSEL to output the second clock signal CNTCK2.

The operation of the clock controller 446 will be described in more detail as follows.

While the command selection signal RDSEL is input at the high level, the first clock signal CNTCK1 is input. The first clock signal CNTCK1 is a signal in which the read enable signal / RE is toggled.

When the column address counting is first started, the start column address COL4LOAD <12: 0> is not the last column address, so the counting end signal CNT_END is at a low level.

Accordingly, the NAND gate NA receives the high level command selection signal RDSEL and the low level counting end signal CNT_END and outputs a high level signal.

The first inverter IN1 inverts the high level signal output from the NAND gate NA and inputs the low level signal to the NOR gate NOR at a low level.

The NOR gate NOR inverts and outputs the other input when one of two input signals is at a low level. Accordingly, the first clock signal CNTCK1 is inverted and output while the low level signal output from the first inverter IN1 is input to one input terminal of the NOR gate NOR.

The second inverter IN2 inverts the output of the NOR gate NOR and outputs the second clock signal CNTCK2.

By the second clock signal CNTCK2, the column counter 444 continues column address counting to the last column address.

When the column counter 444 counts to the last column address, the counter end logic 448 confirms that the address signal CNT_COL <12: 0> indicates the last column address, and the count end signal CNT_END is at a high level. Change to

When the counting end signal CNT_END is changed to the high level, the enable controller 447 changes the enable signal ENABLE to the low level to stop the operation of the column counter 444.

In addition, the clock control unit 446 outputs the low level signal by the NAND gate NA by the high level command selection signal RDSEL and the high level counting end signal CNT_END.

The first inverter IN1 inverts the low level signal output from the NAND gate NA and inputs the high level signal to the NOR gate NOR. The NOR gate NOR outputs a low level signal regardless of another input signal when any one of the input signals is at a high level.

Therefore, the second clock signal CNTCK2 output by the second inverter IN2 is maintained at a high level so that clock generation is no longer performed.

Accordingly, when counting is completed to the last column address, clock generation as well as the column counter 444 are stopped.

The timing diagrams of the second clock signal CNTCK2, the address signal INT_COL, and the counting end signal CNT_END for the above operation are shown in FIG. 5. When the counting end signal CNT_END changes to a high level, the second clock The signal CNTCK2 is no longer in the form of a clock signal but becomes a signal maintained at a high level. Therefore, the clock is not unnecessarily generated after the counting operation is completed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 illustrates a portion of a nonvolatile memory device.

2 illustrates some of pins for signal input of a memory chip including a nonvolatile memory device.

3 shows a clock signal while data is input.

4A illustrates a nonvolatile memory device according to an embodiment of the present invention.

4B illustrates the controller of FIG. 4A.

5 is a timing diagram illustrating an address signal output according to an exemplary embodiment of the present invention.

* Brief description of the main parts of the drawings *

400: nonvolatile memory device 410: memory cell array

420: page buffer 430: Y decoder

440 control unit 441 buffer

442: Register 443: Address mux

444: column counter 445: mux

446: clock control unit 447: enable control unit

448: counter termination logic 449: command decoder

Claims (13)

A memory cell array connected to bit lines and word lines and including memory cells for storing data; A page buffer unit connected to one or more bit lines of the bit lines and including page buffers for temporarily storing data to be stored in the memory cells or reading and storing data stored in the memory cells; A control unit including a clock unit generating first and second clock signals; And An address counting unit for generating an address signal according to the second clock signal, The clock unit controls whether the first and second clock signals are generated according to the counting operation state of the address counting unit. The address counting unit, An address mux for outputting a start column address for data reading by using the address information input for reading data; A column counter for outputting an address signal by performing column address counting from the start column address according to the second clock signal; A counter termination logic that determines whether the address signal is a last column address and outputs a first control signal for terminating counting; And And an enable controller configured to output an enable signal for controlling the operation of the column counter according to the first control signal and a counting enable signal. delete Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The clock unit, A mux for outputting a first clock signal using a command selection signal input according to a read command and a read enable signal; And A clock control unit configured to output the first clock signal as the second clock signal according to the first control signal, or to fix and output the second clock signal to have a predetermined constant logic level. Nonvolatile memory device comprising a. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, The clock control unit, And outputting the second clock signal at the predetermined constant logic level regardless of the input of the first clock signal when the first control signal is input at a first logic level indicating the end of counting. . Claim 5 was abandoned upon payment of a set-up fee. The method of claim 3, The clock control unit, A first logic calculator configured to perform a NAND logic operation on the command selection signal and the first control signal to output a second control signal; And A second logic operation unit outputting the first clock signal as the second clock signal according to the second control signal, or fixing and outputting the second clock signal to have the set logic level signal; Nonvolatile memory device comprising a. A memory cell array connected to bit lines and word lines and including memory cells for storing data; A page buffer unit connected to one or more bit lines of the bit lines and including page buffers for temporarily storing data to be stored in the memory cells or reading and storing data stored in the memory cells; And A controller configured to generate an address signal in response to a first clock signal and a second clock signal generated according to the first control signal, and to control the second clock signal to be fixed at a predetermined logic level when the address signal is the last address. Including, The control unit, A clock generator configured to generate the first clock signal using a command selection signal input according to a read command and a read enable signal; A clock controller configured to output the first clock signal as the second clock signal according to the first control signal, or to control the second clock signal to be fixed at a predetermined logic level; And And an address counting unit generating an address signal in response to the second clock signal. delete Claim 8 was abandoned when the registration fee was paid. The method of claim 6, The address counting unit, An address mux for outputting a start column address for data reading by using address information input for data reading; A column counter for outputting the address signal by performing column address counting from the start column address according to the second clock signal; A counter termination logic that determines whether the address signal is a last address and outputs the first control signal for terminating counting; And An enable controller for outputting an enable signal for controlling an operation of the counter according to the first control signal and a counting enable signal Nonvolatile memory device comprising a. delete Claim 10 has been abandoned due to the setting registration fee. The method of claim 8, The clock control unit, When the first control signal is input at the first logic level, the first clock signal is output as the second clock signal, And when the first control signal is input at a second logic level indicating end of counting, the second clock signal is fixed and output at a predetermined constant logic level regardless of the input of the first clock signal. device. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, The clock control unit, A first logic calculator configured to perform a NAND logic operation on the command selection signal and the first control signal to output a second control signal; And A second logic operation unit outputting the first clock signal as the second clock signal according to the second control signal, or fixing and outputting the second clock signal to have the set logic level signal; Nonvolatile memory device comprising a. Providing a control unit for generating a clock signal and performing column address counting to output data read in column units according to a data read command input to the nonvolatile memory device; Confirming a start column address using address information input together with the data read command, performing column address counting from the start column address according to the clock signal, and outputting the read data in accordance with the column address counting step; Checking whether a last column address is counted while performing the column address counting; And If the last column address is counted, stopping the counting operation and outputting a control signal for stopping generation of the clock signal; Method of operating a nonvolatile memory device comprising a. Claim 13 was abandoned upon payment of a registration fee. The method of claim 12, And the clock signal is fixed to a set logic level by the control signal.

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