KR101068495B1 - Method of data reading a non volatile memory device - Google Patents

Abstract

The present invention relates to a data read of a nonvolatile memory device, the method comprising: sequentially reading data stored in even and odd pages of a first word line, and storing the data stored in a first latch and a second latch of a page buffer; Reading data stored in an even or odd page of a second word line, and storing the data in a third latch of the page buffer; outputting data of the first latch and converting data stored in the second latch to the first latch Delivering; Outputting data of the second latch delivered to the first latch and transferring data stored in the third latch to the first latch; And outputting data of the third latch transferred to the first latch.

Data Read, Page Buffer, Latch, Pump

Description

Method of data reading a non volatile memory device

The present invention relates to a method of operating a nonvolatile memory device, and more particularly, to a data reading method of a nonvolatile memory device that can shorten a data read time by utilizing a latch of a page buffer.

The semiconductor memory device is a memory device that stores data and can be read when needed. BACKGROUND OF THE INVENTION A semiconductor memory device has a volatile memory in which stored data is destroyed when the power is cut off, and a nonvolatile memory in which the stored data is not destroyed even when the power is cut off. Among nonvolatile memories, flash memory is widely used in computers and memory cards because it has a function of electrically erasing data of cells.

The nonvolatile memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines extending along rows and a plurality of bit lines extending along columns and a plurality of cell strings corresponding to the bit lines, respectively.

The nonvolatile memory device was initially used as a memory for simply storing data by storing and reading data. However, a cache program, a copyback, and a multi-plane operation are used to improve performance. Techniques for performing various operations such as operation) have been developed.

In addition, as a memory cell of a nonvolatile memory device is a single level cell (SLC) that stores only one bit data, a multi-level cell (MLC) capable of storing multiple bit data is developed. The number of latches in the buffer is increasing.

Generally, a nonvolatile memory device capable of storing two bits of data includes page buffer circuits including three latches. The latches of the page buffer circuit include a cache latch for data input and a cache program operation, a main latch for performing a data program or a read operation, and a temporary latch that can be used temporarily.

The page buffer circuit latches data to be programmed with the cache latch when programming the data, and then transfers the data latched to the cache latch to the main latch. The data latched in the main latch is programmed into the memory cell.

In addition, the page buffer circuit stores the read data in the main latch when reading the data programmed in the memory cell. Data stored in the main latch is transferred to the cache latch and output. This method of operation may be a way of not fully utilizing the latches in the page buffer circuit.

In particular, when a memory device designed for a multi-level cell operates as a single level cell, many latches are not used because only one latch is used as the data input / output.

Accordingly, an aspect of the present invention is to provide a data reading method of a nonvolatile memory device that can reduce data read time by fully utilizing the latches of the page buffer circuit when reading data of the nonvolatile memory device.

A data reading method of a nonvolatile memory device according to an aspect of the present invention,
Reading data stored in even and odd pages of the first word line in order and storing the data stored in the first latch and the second latch of the page buffer, respectively;

Reading data stored in an even or odd page of a second word line, and storing the data in a third latch of the page buffer; outputting data of the first latch and converting data stored in the second latch to the first latch Delivering; Outputting data of the second latch delivered to the first latch and transferring data stored in the third latch to the first latch; And outputting data of the third latch transferred to the first latch.

Reading data stored in the even and odd pages of the first word line and sequentially storing the data in the first latch and the second latch of the page buffer may include enabling a pump circuit for generating an operating voltage to start precharging. Making; Precharging an operating voltage to the first word line and the bit line to read an even page of the first word line; Reading data of an even page of the first word line and storing the data in the first latch and discharging the voltages of the precharged bit line and the first word line; Precharging an operating voltage to the second word line and the bit line to read an odd page of the first word line; And reading and storing data of an odd page of the first word line in the second latch and discharging the voltages of the precharged bit line and the second word line. The operation of reading data stored in an even or odd page of the second page and storing the data in the third latch of the page buffer may include applying an operating voltage to the third word line and the bit line to read the even or odd page of the second word line. Precharging; Reading data of an even or odd page of the second word line and storing the data in the third latch and discharging the voltages of the precharged bit line and the third word line; And discharging the pump circuit.

The first latch may be reset before the data of the second latch is transferred to the first latch.

The first latch may be reset before transferring the data of the third latch to the first latch.

According to another aspect of the present invention, a data reading method of a nonvolatile memory device is provided.

Inputting a data read command; Reading and storing data of the first to N pages, respectively, in the first to Nth (N is three or more natural numbers) latches of the page buffer; And sequentially outputting data stored in the first to Nth latches through a first latch.

Enabling the pump circuit to provide an operating voltage according to the data read command when reading the data of the first to Nth pages; Precharging a word line and a bit line to read data of the first page; Reading data of the first page and storing the data in the first latch; And discharging the precharged word lines and bit lines, wherein the word lines and bit lines precharge steps, data read and store steps, and discharging the word lines and bit lines are performed. The data repeatedly performed on the N pages and respectively read is stored in the second to Nth latches, respectively.

And disabling the enabled pump circuit when the reading of data up to the Nth page is completed.

Outputting data stored in the first to Nth latches sequentially through a first latch may include: outputting data of the first latch; And sequentially transferring the data of the second to Nth latches to the first latch, and outputting the data transferred to the first latch.

The first latch is reset before the data of the second to Nth latches are transferred to the first latch.

As described above, the data read method of the nonvolatile memory device according to the present invention reads, stores, and sequentially outputs data in the latches of the page buffer circuit so as to utilize all the latches of the page buffer circuit to read data. Can be reduced.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to make the disclosure of the present invention complete and to those skilled in the art. It is provided for complete information.

1A is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a nonvolatile memory device 100 may include a memory cell array 110, a page buffer unit 120, a Y decoder 130, an X decoder 140, a voltage providing unit 150, and a controller 160. ).

In the memory cell array 110, memory cells for data storage are connected to a bit line and a word line. The page buffer unit 120 is connected to the bit lines of the memory cell array 110 and temporarily stores data for programming and provides the bit lines, or senses the bit line voltage when data is read and stores the data in the memory cells. The page buffer circuits 122 may be temporarily stored. The page buffer circuit 122 is a circuit including three latches.

The Y decoder 130 provides a data input / output path of the page buffer unit 120. The X decoder 140 connects an operating voltage provided by the voltage provider 150 to word lines of the memory cell array 110.

The voltage provider 150 generates an operating voltage for a program or data read operation. The voltage provider 150 includes a pump circuit for generating a high voltage. The controller 160 controls the voltage providing unit 150 to generate a voltage according to an operation mode, and outputs a control signal for performing a program operation or a data read operation.

The controller 160 includes a storage means, and outputs a control signal for operation control in order according to an operation algorithm stored in a program form.

The page buffer circuit 122 will be described in more detail as follows.

FIG. 1B is a detailed circuit diagram of the page buffer circuit of FIG. 1A.

Referring to FIG. 1B, the page buffer circuit 121 may include a bit line selection unit 122, a sensing unit 123, a precharge unit 124, first to third latch units 125 to 127, a verification unit, and the like. And a data output unit 129.

The bit line selector 122 selects one bit line among the even bit line BLe and the odd bit line BLo according to the input address, and connects the bit line to the sensing unit 123. .

The sensing unit 123 senses the bit line voltage level to change the voltage at the sensing node SO. The precharge unit 124 precharges the sensing node SO.

The first to third latch units 125 to 127 temporarily store data for programming and transfer the data to a bit line through the sensing node SO or temporarily store data stored in a memory cell. In general, the first latch unit 125 is a latch unit that performs a function of the cache latch unit. The first latch unit 125 is a latch unit capable of receiving data input and receives data for a cache program operation from the first latch unit 125.

The second latch unit 126 receives the data to be programmed from the first latch unit 125 and transmits the data to the bit line through the sensing node SO, or reads and stores the data stored in the memory cell to temporarily store the data. do.

The third latch unit 127 operates as a temporary latch unit for temporarily storing data when performing a program or data read operation.

The verification unit 128 is connected between the first latch unit 125 and the second latch unit 126 to output a program verification signal. The data output unit 129 is connected to the first latch unit 125 and outputs data latched to the first latch unit 125 according to a control signal.

The page buffer circuit 121 further includes sixteenth and seventeenth NMOS transistors N16 and N17. The circuit connection of the page buffer circuit 121 will be described in detail as follows.

The bit line selector 122 includes first to fourth NMOS transistors N1 to N4. The first NMOS transistor N1 is connected between the even bit line BLe and the node K2, and the even bit line select signal PBSELBLE is input to the gate of the first NMOS transistor N1.

The second NMOS transistor N2 is connected between the odd bit line BLo and the node K2, and the odd bit line select signal PBSELBLO is input to the gate of the second NMOS transistor N2.

The third and fourth NMOS transistors N3 and N4 are connected between the even bit line BLe and the odd bit line BLo and are nodes K1 that are contacts of the third and fourth NMOS transistors N3 and N4. The variable voltage PBVIRPWR is input to

An even bit line discharge control signal PBDISCHE is input to a gate of the third NMOS transistor N3, and an odd bit line discharge control signal PBDISCHO is input to a gate of the fourth NMOS transistor N4.

The sensing unit 123 includes a fifth NMOS transistor N5. The fifth NMOS transistor N5 is connected between the node K2 and the sensing node SO, and the sensing control signal PBSENSE is input to the gate of the fifth NMOS transistor N5.

The precharge unit 124 includes a PMOS transistor (P). The PMOS transistor P is connected between the power supply voltage and the sensing node SO, and the precharge control signal PBPRECHSO_N is input to the gate of the PMOS transistor P.

The first latch unit 125 includes sixth to eighth NMOS transistors N6 to N8 and first and second inverters IN1 and IN2. The sixth NMOS transistor N6 is connected between the sensing node SO and the node QC_N, and the first transmission signal TRAN is input to the gate of the sixth NMOS transistor N6.

The seventh NMOS transistor N7 is connected between the node QC and the node K3, and the first reset signal CRST is input to the gate of the seventh NMOS transistor N7. The eighth NMOS transistor N8 is connected between the node QC_N and the node K3, and the first set signal CSET is input to the gate of the 88th NMOS transistor N8.

The first and second inverters IN1 and IN2 are connected by a latch between the node QC and the node QC_N to form a first latch L1.

The second latch unit 126 includes ninth to eleventh NMOS transistors N9 to N11 and third and fourth inverters IN3 and N4. The ninth NMOS transistor N9 is connected between the sensing node SO and the node QM_N, and the second transmission signal TRANM is input to the gate of the ninth NMOS transistor N9.

The tenth NMOS transistor N10 is connected between the node QM and the node K3, and the second reset signal MRST is input to the gate of the tenth NMOS transistor N10. The eleventh NMOS transistor N11 is connected between the node QM_N and the node K3, and the second set signal MSET is input to the gate of the eleventh NMOS transistor N11.

The third and fourth inverters IN3 and IN4 are connected by a latch between the node QM and the node QM_N to form a second latch L2.

The third latch unit 127 includes twelfth to fifteenth NMOS transistors N12 to N15 and fifth and sixth inverters IN5 and IN6. The twelfth NMOS transistor N12 is connected between the sensing node SO and the node QT, and the fourth transmission signal TRANT_N is input to the gate of the twelfth NMOS transistor N12.

The thirteenth NMOS transistor N13 is connected between the sensing node SO and the node QT_N, and a third transmission signal TRANT is input to a gate of the thirteenth NMOS transistor N13. The inverted signal of the third transmission signal TRANT is the fourth transmission signal TRANT_N.

The fourteenth NMOS transistor N14 is connected between the node QT and the node K3, and the third reset signal TRST is input to the gate of the fourteenth NMOS transistor N14. The fifteenth NMOS transistor N15 is connected between the node QT_N and the node K3, and the third set signal TSET is input to the gate of the fifteenth NMOS transistor N15.

The fifth and sixth inverters IN5 and IN6 are connected by a latch between the node QT and the node QT_N and constitute the third latch L3.

The verification unit 128 includes twentieth to twenty-second NMOS transistors N20 to N22. The twentieth NMOS transistor N20 is connected between the node K4 and the node K5, and the gate of the twentieth NMOS transistor N20 is connected to the node QC_N.

The twenty-first NMOS transistor N21 is connected between the node K4 and the node K5, and a check signal PBCHECK is input to the gate of the twenty-first NMOS transistor N21. The twenty-second NMOS transistor N22 is connected between the node K5 and the verify signal output terminal, and a gate of the twenty-second NMOS transistor N22 is connected to the node QM.

The verification signal PBVER is input to the node K4, and a high level signal is input by connecting a power supply voltage.

The data output unit 129 includes eighteenth and nineteenth NMOS transistors N18 and N19. The eighteenth NMOS transistor N18 is connected between the node QC and the first output terminal PBBITOUTb, and the nineteenth NMOS transistor N19 is connected between the node QC_N and the second output terminal PBBITOUT. Gates of the eighteenth and nineteenth NMOS transistors N18 and N19 are commonly connected to a node K6, and an output control signal PBYPASS is input to the node K6.

In addition, the page buffer circuit 121 further includes sixteenth and seventeenth NMOS transistors N16 and N17. The sixteenth NMOS transistor N16 is connected between the node K3 and the ground node, and a gate of the sixteenth NMOS transistor N16 is connected to the sensing node SO.

The seventeenth NMOS transistor N17 is connected between the sensing node SO and the node K7, and the control signal CELLIV is input to the gate of the seventeenth NOS transistor N17. The node K7 is connected to the second output terminal PBBITOUT.

A method of reading data using the page buffer circuit 121 according to the exemplary embodiment of the present invention configured as described above is as follows.

2A and 2B are flowcharts illustrating a data read operation of a nonvolatile memory device according to an embodiment of the present invention.

In particular, FIG. 2A is an operation sequence until reading and storing data in the page buffer circuit 121, FIG. 2B is an operation flowchart for outputting data stored in the page buffer circuit 121, and FIGS. 2A and 2B are memories. When storing data in a cell, it is an operation sequence when outputting data with one bit information stored in one memory cell as a single level cell.

Referring to FIG. 2A, in order to read data stored in the nonvolatile memory device 100, a data read command, address information of a memory cell to read data, and an execution command are input (S201 to S205).

In response to the command, the controller 160 sets up the voltage providing unit 150 to generate an operating voltage for performing the read command (S207). When the voltage providing unit 150 generates the operating voltage, the bit line and the word line are precharged to read the data (S209).

In the case of precharging the bit line and the word line, the word line is precharged with the read voltage and the bit line is precharged by the page buffer circuit 121.

For the bit line precharge, the precharge unit 124 of the page buffer circuit 121 precharges the sensing node SO to the power supply voltage level. When the even bit line is selected, the first NMOS transistor N1 is turned on and the fifth NMOS transistor N5 is turned on by applying the sensing control signal PBSENSE to the first voltage V1 level. As a result, the bit line is precharged. Thereafter, a read voltage is applied to the selected word line, and a pass voltage is applied to other word lines so that the bit line voltage is changed. At this time, the first NMOS transistor N1 is turned off. The selected word line, in more detail, refers to one logical page. For example, in a case where the memory cell array can store two bits, one word line includes two logical pages. In the read operation, data read is performed in units of one logical page.

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Therefore, hereinafter, it will be described that the data read to the first page, which is one logical page. After changing the bit line voltage by applying the read voltage to the first page, the sensing control signal PBSENSE is applied to the second voltage V2 level, and a voltage difference between the bit line voltage and the sensing node SO is applied. Allow the sensing node (SO) voltage to change. The data of the first page is latched in the first latch L1 of the first latch unit 125 according to the voltage level of the sensing node SO (S211). The sensing process for reading the data is the same as the data reading process of a general nonvolatile memory device, and thus a detailed description thereof will be omitted.

When the data latch of the first page is completed, the voltages of the bit line and the word line precharged in the step S209 are discharged (S213), and the bit line and the word line are precharged to read the data of the second page (S215). .

The data of the second page is sensed and latched to the second latch L2 of the second latch unit 126 (S217). After latching the data of the second page, the bit line and the word line are discharged (S219).

The bit line and the word line are precharged to read the data of the third page (S221), and the data of the third page is latched to the third latch L3 of the third latch unit 127 (S225).

As described above, after the data of the first to third pages are latched to the first to third latches L1 to L3 in sequence, data reading is started (S227).

Referring to FIG. 2B, the voltage generator 150 discharges the pump generating the operating voltage before reading the data (S229). Data is output to the node QC_N of the first latch L1 (S231). To do this, the output control signal PBYPASS is applied at a high level to turn on the nineteenth NMOS transistor N19.

After the data of the first page stored in the first latch L1 is outputted, the data of the third page of the node QM_N of the second latch L2 is transferred to the first latch L1 and output. The control signal PBYPASS is applied at a high level and output (S223, S225).

When data of the second page stored in the second latch L2 is transferred to the first latch L1 and outputted, the following operation is performed to output correct data.

When performing steps S223 and S225, firstly, the first latch L1 is reset. To this end, after pre-charging the sensing node SO, the first set signal CSET is applied to a high level to make the node QC_N '0'.

The second transmission signal TRANM and the first reset signal CRST are applied at a high level. When the second transmission signal TRANM is applied at a high level, the ninth NMOS transistor N9 is turned on and data of the node QM_N is transmitted to the sensing node SO.

The sixteenth NMOS transistor N16 is turned on or off according to the data of the node QM_N transmitted to the sensing node SO. When the first reset signal CRST is applied at the high level, the seventh NMOS transistor N7 is turned on.

If data is '1' at the node QM_N, the sensing node SO becomes '1' and the sixteenth NMOS transistor N16 is turned on. When the first reset signal CRST is applied at the high level, the seventh NMOS transistor N7 is turned on and the node QC is connected to the ground node.

Accordingly, the node QC_N is in the '1' state. Therefore, data of the node QM_N is normally transmitted to the node QC_N. Thereafter, the output control signal PBYPASS is applied to the high level to turn on the 18th and 19th NMOS transistors N18 and N19 to output data to the first latch L1.

After outputting the data of the second page, the data of the third page stored in the third latch L3 is transferred to the first latch L1 and output (S237 and S239).

The process of transferring the data of the third latch L3 to the first latch L1 and outputting the data is similar to the process of transferring the data of the second latch L2 to the first latch L1 and outputting the data.

First, the node QC_N of the first latch L1 is reset to a '0' state. The third transmission signal TRANT and the first reset signal CRST are applied to move the data of the third latch L3 to the first latch L1. The data of the first latch L1 is output.

As mentioned above, the above operation is a method that can be applied when only one bit information is stored and used in a memory cell. That is, even when a nonvolatile memory device is manufactured for a multi-level cell, when a memory device is used in preference to a program speed or the like, it may be used as a memory device including a single-level cell. Read time can be used to reduce the read time.

The read-busy signal applied to the inside of the nonvolatile memory device 100 during the operations of FIGS. 2A and 2B described above is as follows.

3 is a ready signal during a data read operation of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, the busy state is maintained while sequentially performing the data read first through third pages (S207 through S225), and data of the second latch L2 and the third latch L3 are first latched. The busy state is maintained while transferring to L1 (S233, S237).

In the nonvolatile memory device 100 according to the embodiment of the present invention, the pump circuit of the voltage providing unit 150 generates a voltage by reading data using all three latches of the page buffer circuit 121. As a result, the discharge time is reduced. In other words, the pump starts and is precharged to perform reading for each page, and is discharged when the operation is completed. Since the pump starts and ends every three pages, the high voltage precharge and discharge are performed. The time to do it can be reduced.

Therefore, all the latches of the page buffer circuit are fully utilized, which reduces the pump discharge and precharge time, thereby reducing the overall operation time and increasing efficiency.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1A is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 1B is a detailed circuit diagram of the page buffer circuit of FIG. 1A.

2A and 2B are flowcharts illustrating a data read operation of a nonvolatile memory device according to an embodiment of the present invention.

3 is a ready signal during a data read operation of a nonvolatile memory device according to an embodiment of the present invention.

* Brief description of the main parts of the drawings *

100 nonvolatile memory device 110 memory cell array

120: page buffer unit 130: Y decoder

140: X decoder 150: voltage provider

160: control unit

Claims (9)

Reading data stored in even and odd pages of the first word line in order and storing the data stored in the first and second latches of the page buffer, respectively; Reading data stored in an even or odd page of a second word line and storing the data stored in a third latch of the page buffer; Outputting data of the first latch and transferring data stored in the second latch to the first latch; Outputting data of the second latch delivered to the first latch and transferring data stored in the third latch to the first latch; And Outputting data of the third latch delivered to the first latch Data reading method of a nonvolatile memory device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Reading data stored in even and odd pages of the first word line in order and storing the data stored in the first latch and the second latch of the page buffer, respectively, Enabling the pump circuit to generate an operating voltage to initiate precharge; Precharging an operating voltage to the first word line and the bit line to read an even page of the first word line; Reading data of an even page of the first word line and storing the data in the first latch and discharging the voltages of the precharged bit line and the first word line; Precharging an operating voltage to the second word line and the bit line to read an odd page of the first word line; And Reading and storing data of an odd page of the first word line in the second latch, and discharging the voltages of the precharged bit line and the second word line; Reading data stored in an even or odd page of the second word line and storing the data in the third latch of the page buffer may include: Precharging an operating voltage to the third word line and the bit line to read an even or odd page of the second word line; Reading data of an even or odd page of the second word line and storing the data in the third latch and discharging the voltages of the precharged bit line and the third word line; And Discharging the pump circuit A data reading method of a nonvolatile memory device comprising a. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, And resetting the first latch before transferring the data of the second latch to the first latch. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, And resetting the first latch before transferring the data of the third latch to the first latch. Inputting a data read command; Reading the data stored in the first to Nth pages included in the plurality of word lines in page units and storing the data in the first to Nth latches (where N is a natural number of three or more) in the page buffer; And Sequentially outputting data stored in the first to Nth latches through a first latch A data reading method of a nonvolatile memory device comprising a. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, When reading the data of the first to Nth pages, Enabling a pump circuit for providing an operating voltage according to the data read command; Precharging a word line and a bit line to read data of the first page; Reading data of the first page and storing the data in the first latch; And Discharging the precharged word lines and bit lines; The word line and the bit line precharge step, the data read storage step, and the step of discharging the word line and the bit line are repeatedly performed for the second to the Nth page, and the data read out is the second to the Nth latch. And data stored in the nonvolatile memory device. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, Disabling the enabled pump circuit when the data reading up to the Nth page is completed. Claim 8 was abandoned when the registration fee was paid. The method of claim 5, In order to sequentially output data stored in the first to Nth latches through a first latch, Outputting data of the first latch; And And sequentially transferring data of the second to Nth latches to the first latch, and outputting the data transferred to the first latch. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, And resetting the first latch before transferring the data of the second to Nth latches to the first latch.

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