KR100705222B1 - Non-volatile memory device and method for verifying successful erasing thereof - Google Patents

Abstract

The present invention reads data of a memory cell connected to an even bit line using a main register, and reads data of a memory cell connected to an odd bit line using a cache register, thereby enabling internal operation of a page buffer without a conventional external operation. The present invention relates to a nonvolatile memory device for verifying whether data stored in a memory cell is erased or not and an erase verification method thereof. If the data stored in the memory cells connected to the first or second bit line is not erased, the erase verification unit outputs the erase verify signal to a logic low and stores the data in the memory cell connected to the first or second bit line. If is erased, the erase verify signal is output in a floating state.

Page buffer, erase verify, verify time

Description

Non-volatile memory device and method for verifying successful erasing             

1 is a circuit diagram illustrating a NAND flash memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a timing diagram for describing an operation of the NAND flash memory device of FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: memory cell array 200: bit line selection unit

300: page buffer 310: precharge unit

320: main register 340: cache register

330: program verification unit 350: erase verification unit

360: Pass / fail detector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a NAND type flash memory device for reducing an erase verification time and an erase verification method thereof.

There is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function that rewrites data at regular intervals. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

For high integration of memory devices, a NAND type flash memory device is developed in which a plurality of memory cells are connected in series (that is, a structure in which adjacent cells share drain or source with each other) to form a string. It became. Unlike NOR-type flash memory devices, NAND-type flash memory devices are memory devices that read information sequentially.

A NAND type flash memory device uses a page buffer to store a large amount of information or to read stored information in a short time. The page buffer receives a large amount of data from an input / output pad and provides the memory cells or stores and outputs data of the memory cells. In general, the page buffer is generally composed of a single register to temporarily store data. However, in recent NAND flash memory devices, a dual register, that is, a main register and a cache register, to increase program speed when programming a large amount of data. It consists of.

Since the NAND-type flash memory device performs a program in units of pages and erases in units of blocks, the program verify operation verifies one page at the same time, but the erase verify operation verifies one block. In addition, since the program verification verifies that data has been successfully written to the memory cell and the erase verification verifies that data written to the memory cell has been successfully erased, the signal according to the program verification and the signal according to the erasure verification are Are at opposite voltage levels. Therefore, erase verification cannot use the same manner as program verification. That is, the erase verification method reads the output data of the main register and logically combines the data, and detects pass / fail depending on whether the combined value is "0" or "1".

Therefore, when the 528 blocks need to be erase-verified, the data stored in the memory cell connected to the even bit line is read, the data stored in the memory cell connected to the odd bit line is read, and the internal operation is performed in the page buffer. Thereafter, the erase verification time takes a lot because of the trouble of having to toggle the output of data 528 times by performing an external read operation so that it is possible to know whether the erase is a fail or not. In addition, since a pass / fail of an erase operation must be detected by comparing whether the output data is “0” or “1” during data output, many separate logic elements are required for erase verification.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a nonvolatile memory device and an erase verification method thereof that verify whether data stored in a memory cell is erased by only an internal operation of a page buffer without a conventional external operation. The purpose is.

A nonvolatile memory device according to a preferred embodiment of the present invention, which is designed to achieve the above object, comprises: an array of memory cells connected to first and second bit lines; And a page buffer connected to the first or second bit line through a sensing node, wherein the page buffer maintains its initial voltage level when data stored in memory cells connected to the first bit line is erased. A main register whose voltage level is changed from an initial state when data stored in memory cells connected to the first bit line is not erased; If the data stored in the memory cells connected to the second bit line is erased, the voltage level is maintained in an initial state. If the data stored in the memory cells connected to the second bit line is not erased, the voltage level is changed from an initial state. Cache registers; When the voltage level of the main register or the cache register is changed from the initial state, the first signal for erasure verification is output at the first voltage level, and when the voltage level of the main register or the cache register maintains the initial state, And an erase verification unit for outputting one signal in a floating state.

According to another exemplary embodiment of the present invention, an erase verification method of the present invention, which has been made to attain the above object, includes: an array of memory cells connected to first and second bit lines; And a page buffer connected to the first and second bit lines through a sensing node and having a main register and a cache register, the nonvolatile memory device comprising: a memory device connected to the first or second bit line; When the stored data is erased, the voltage level of the main register or the cache register is changed from an initial state, and when the data stored in the memory cells connected to the first or second bit line is not erased, the main register Or maintaining a voltage level of the cache register in an initial state; And when the voltage level of the main register or the cache register is changed to an initial state, generates a first signal for erasing verification at a first voltage level, and maintains an initial state of the voltage level of the main register or the cache register. In this case, the step of generating the first signal in a floating state.

The present invention reads data of a memory cell connected to an even bit line by using a main register, and reads data of a memory cell connected to an odd bit line by using a cache register, thereby providing an internal page buffer without a conventional external operation. The operation alone verifies whether or not data stored in the memory cell has been erased.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.                     

1 is a circuit diagram illustrating a NAND type flash memory device according to an exemplary embodiment of the present invention, and FIG. 2 is a timing diagram for describing an operation of the NAND type flash memory device of FIG. 1.

Referring to FIG. 1, a NAND type flash memory device includes an array of memory cells 100 and a page buffer 300 connected to bit lines BLe and BLo.

The page buffer 300 includes a bit line selection unit 200, a precharge unit 310, a main register 320, a program verification unit 330, a cache register 340, an erase verification unit 350, and a pass / fail. The detector 360 and the NMOS transistors N18 and N19 are included.

The bit line selector 200 includes NMOS transistors N21 -N24. The NMOS transistor N21 is turned on by the discharge signal DISCHe to apply the signal VIRPWR to the even bit line BLe. The NMOS transistor N22 is turned on by the discharge signal DISCHo to apply the signal VIRPWR to the odd bit line BLo. In the data read operation, the 0 V control signal VIRPWR is applied to the unselected bit line, while in the program operation, the control signal VIRPWR of the power supply voltage VCC is applied to the unselected bit line. In addition, the NMOS transistor N23 is turned on by the bit line select signal BSLe to connect the even bit line BLe and the sensing node SO, and the NMOS transistor N24 is connected by the bit line select signal BSLo. It is turned on to connect the odd bit line BLo and the sensing node SO.

The precharge unit 310 includes a PMOS transistor P11 having one end connected to the power supply voltage VCC and the other end connected to the sensing node SO, and turned on / off by receiving a precharge signal PRECHb as a gate. do. In order to perform an erase or program verify operation after erasing or program completion, the precharge unit 310 precharges the sensing node SO to logic high when the precharge signal PRECHb becomes logic low as shown in FIG. 2. Let it be. When the erase is a pass, that is, when the data stored in the memory cell is erased, the signal precharged to the sensing node SO is discharged to the memory cell connected to the selected bit line because the memory cell is empty. In contrast, when the erase is a fail, that is, when the data stored in the memory cell is not erased, the memory cell is charged and thus the signal precharged to the sensing node SO is not discharged to the memory cell connected to the selected bit line. It is in its first precharged state (logic high).

The main register 320 includes a main latch L1 and NMOS transistors N11 and N12. One end of the NMOS transistor N11 is connected to the node QAb of the main latch L1 and is turned on / off by receiving a signal of the sensing node SO through a gate. When the data stored in the memory cell connected to the even bit line BLe is not erased, the NMOS transistor N11 is turned on by receiving a signal of the sensing node SO of logic high as a gate. One end of the NMOS transistor N12 is connected to the other end of the NMOS transistor N11, the other end thereof is connected to the ground voltage VSS, and is turned on / off by receiving the main latch signal MLH through the gate. When the data stored in the memory cell connected to the even bit line BLe is not erased, the NMOS transistor N12 is turned on by receiving the logic latch main latch signal MLH as a gate (see FIG. 2). The main latch L1 constitutes a latch with inverters IV11 and IV12. When the data stored in the memory cell connected to the even bit line BLe is erased, the initial voltage level state, that is, the node QAb is logic high, the node If QA remains logic low and NMOS transistors N11 and N12 are both turned on when the data stored in the memory cell is not erased, then node QAb goes from logic high to logic low and node QA Transition from logic low to logic high.

Here, the NMOS transistor N18 is connected between the sensing node SO and the node QA of the main latch L1 and is turned on / off by receiving a program signal PGM to the gate. The NMOS transistor N18 receives a logic high program signal PGM as a gate during a program operation and is turned on to transmit data to be programmed stored in the main latch L1 to a selected bit line, but during an erase verify operation. Is turned off. The NMOS transistor N19 is connected between the node QA of the main latch L1 and the data input / output line DINOUT, and is turned on / off by receiving a page buffer data output signal PBDO through a gate. The NMOS transistor N19 transfers the data stored in the main latch L1 to the input / output line DINOUT during the data read operation, but is turned off during the erase verify operation.

The program verifying unit 330 includes a PMOS transistor P12 having one end connected to the power supply voltage VCC and turned on / off by receiving a signal of the node QA of the main latch L1 through a gate. The operation of the program verification unit 330 will be briefly described. When the program is a pass, that is, when data is written to a memory cell connected to the selected bit line, the signal precharged to the sensing node SO is displayed. NMOS transistors N11 and N12 are turned on so that the node QAb of the main latch L1 transitions from logic high to logic low and node QA transitions from logic low to logic high. Then, the PMOS transistor P12 is turned off and the program verify signal nWDO is in a floated state. In contrast, when the program fails, that is, when data is not written to the memory cell connected to the selected bit line, the signal precharged to the sensing node SO is discharged so that the NMOS transistors N11 and N12 are turned off. The main latch L1 maintains its initial state, that is, the node QBb is logic high and the node QB is logic low. Then, the PMOS transistor P12 is turned on so that the program verify signal nWDO becomes logic high.

The cache register 340 includes a cache latch L2 and NMOS transistors N13, N14, and N15. One end of the NMOS transistor N13 is connected to the node QBb of the cache latch L2, and is turned on / off by receiving a signal of the sensing node SO to the gate. When the data stored in the memory cell connected to the odd bit line BLo is not erased, the NMOS transistor N13 is turned on by receiving a precharged signal to the sensing node SO through a gate. One end of the NMOS transistor N14 is connected to the other end of the NMOS transistor N13, the other end thereof is connected to the ground voltage VSS, and is turned on / off by receiving the cache latch signal CLH through the gate. When the data stored in the memory cell connected to the odd bit line BLO is not erased, the NMOS transistor N14 is turned on by receiving a logic latch cache latch signal CLH (see FIG. 2). The cache latch L2 constitutes a latch with inverters IV13 and IV14. When the data stored in the memory cell connected to the odd bit line BLo is erased, the initial state, that is, the node QBb is logic high and the node QB is If the logic low is maintained and the data stored in the memory cell connected to the odd bit line BLo is not erased, the NMOS transistors N13 and N14 are both turned on, so that the node QBb is pulled from logic high to logic low. Transition node QB from logic low to logic high. One end of the NMOS transistor N15 is connected to the node QB of the cache latch L2, the other end thereof is connected to the data input / output line DINOUT, and is turned on / off by receiving a data input signal DI through a gate. The NMOS transistor N15 is turned on during a program operation to store data supplied from the data input / output line DINOUT in the cache latch L2, but is turned off during erase verification.

The erase verification unit 350 includes NMOS transistors N16 and N17. One end of the NMOS transistor N16 is connected to the ground voltage VSS and is turned on / off by receiving a signal of the node QA of the main latch L1 through a gate. When the data stored in the memory cell connected to the even bit line BLe is not erased, the NMOS transistor N16 is turned on by receiving a signal of the node QA of logic high to the gate, thereby turning on the erase verification signal WDO. When the logic low and the data stored in the memory cell is erased, it is turned off to make the erase verify signal (WDO) floating. One end of the NMOS transistor N17 is connected to the ground voltage VSS and is turned on / off by receiving a signal of the node QB of the cache latch L2 through a gate. When the data stored in the memory cell connected to the odd bit line BLo is not erased, the NMOS transistor N17 is turned on by receiving a signal of the node QB of logic high to the gate to turn on the erase verification signal WDO. When the data is stored in the memory cell and is erased, the memory cell is turned off to make the erase verification signal WDO float.

The pass / fail detector 360 includes a PMOS transistor P13 and a NAND gate ND11. The NAND gate ND11 performs an inverted logical multiplication of the pass / fail check signal EN and the signal of the node EVFOn to output the pass / fail detection signal P_F. As shown in FIG. 2, the PMOS transistor P13 is turned on for a short time when the precharge signal PEN is logic high, thereby precharging the node EVFOn to logic high. Then, as shown in FIG. 2, when the pass / fail check signal EN becomes logic high, when the data stored in the memory cell connected to the selected bit line is not erased and the erase verify signal WDO is logic low, Node EVFOn precharged to logic high goes logic low. Then, the NAND gate ND11 inverts and logically multiplies the pass / fail check signal EN of the logic high and the node EVFOn of the logic low to output the pass / fail detection signal P_F to the logic high, and erase is failed. fail). In contrast, when the pass / fail check signal EN is logic high and the data stored in the memory cell connected to the selected bit line is erased and the erase verify signal WDO is floating, the node EVFOn is shown in FIG. 2. Remains precharged to logic high. Then, the NAND gate ND11 inverts and logically multiplies the pass / fail check signal EN of the logic high and the node EVFOn of the logic high to output the pass / fail detection signal P_F to a logic low, and erase erases the pass ( pass).

Hereinafter, an erase verification method of a NAND flash memory device according to an exemplary embodiment of the present invention will be briefly described with reference to FIGS. 1 and 2.

In order to verify the erase after the erase is completed, first, as shown in FIG. 2, when the precharge signal PRECH becomes logic low, the PMOS transistor P11 is turned on to precharge the node SO to logic high. .

In this case, when the data stored in the memory cell connected to the even bit line BLe is erased, since the memory cell is empty, the signal precharged to the node SO is displayed as an empty memory cell through the even bit line BLe. It is charged. In this case, since the NMOS transistors N11 and N12 are turned off, the node QAb and the output node QA of the main latch L1 retain their initial values, and the NMPOS transistor N16 is turned off to erase the verify signal. Float (WDO) In contrast, when the data stored in the memory cell connected to the even bit line BLe is not erased, the memory cell is in a charged state, and thus the signal precharged to the node SO is discharged to the memory cell through the even bit line BLe. It is not charged. In this case, since NMOS transistors N11 and N12 are turned on, node QAb of main latch L1 transitions from logic high to logic low, and node QA of main latch L1 transitions from logic low to logic high. The NMOS transistor N16 is turned on to bring the erase verify signal WDO to logic low.

Subsequently, when the data stored in the memory cell connected to the odd bit line BLo is erased, the memory cell is in an empty state, and thus a signal precharged to the sensing node SO is displayed as an empty memory cell through the odd bit line BLo. It is charged. In this case, since the NMOS transistors N13 and N14 are turned off, the node QBb and the node QB of the cache latch L2 remain at their initial values, and the NMPOS transistor N17 is turned off so that the erase verify signal ( Make WDO) floating. In contrast, when data stored in a memory cell connected to the odd bit line BLo is not erased, the memory cell is in a charged state, and thus the signal precharged to the node SO is discharged to the memory cell through the odd bit line BLo. It is not charged. In this case, because the NMOS transistors N13 and N14 are turned on, the node QBb of the cache latch L2 goes from logic high to logic low, and the node QB of the cache latch L2 goes from logic low to logic high. Transition, the NMOS transistor N17 is turned on to bring the erase verify signal WDO to logic low.

After performing such an operation, when the data stored in the memory cell connected to the selected bit line is erased, the node EVFOn remains precharged to logic high because the erase verify signal WDO is floating. Then, the NAND gate ND11 logic high pass / fail check signal EN and the logic high node EVFOn signal are inversely logic-multiplied to output the pass / fail detection signal P_F to logic low, and erase is a pass. Determine. In contrast, when data stored in the memory cell connected to the selected bit line is not erased, the node EVFOn is changed to logic low because the erase verify signal WDO is logic low. Then, the NAND gate ND11 inverts and logically multiplies the pass / fail check signal EN of logic high by the node EVFOn of logic low to output the pass / fail detection signal P_F to logic high, and erase is failed. It is determined that.

In the case where the block 528 is connected to the node EVFOn as shown in Fig. 1, if a failure occurs in even one block of the 528 blocks, the node EVFOn goes to a logic high, and the erase is considered to be a failure.

As described above, according to the present invention, an erase verification time is performed by performing erase verification on a memory cell of an even bit line using a main register, and performing erase verification on a memory cell of an odd bit line using a cache register. There is an advantage to reduce.

In addition, there is an advantage in that the number of circuits required for erasure verification can be reduced by performing erase verification only by the internal operation of the page buffer without the external operation.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (12)

An array of memory cells connected to the first and second bit lines; And A page buffer connected to the first or second bit line through a sensing node; The page buffer maintains an initial voltage level when data stored in memory cells connected to the first bit line is erased, and initializes the voltage level when data stored in memory cells connected to the first bit line is not erased. A main register changed in state;  If the data stored in the memory cells connected to the second bit line is erased, the voltage level is maintained in an initial state. If the data stored in the memory cells connected to the second bit line is not erased, the voltage level is changed from an initial state. Cache registers;  If each voltage level is changed from an initial state in response to a voltage level of the main register or the cache register, a first signal for erasure verification is output at a first voltage level, and if each voltage level maintains an initial state, the first signal is outputted. Nonvolatile memory device including an erase verification unit for outputting a signal in a floating state. The method of claim 1, When the data stored in the memory cells connected to the first or second bit line is not erased, the erase verification unit outputs the first signal to a logic low, and the memory connected to the first or second bit line. And outputting the first signal in a floating state when data stored in a cell is erased. The method of claim 1, The erase verification unit may include: a first transistor configured to set the first signal to a logic low level using a ground voltage when the voltage level of the main register is changed from an initial state; And a second transistor configured to make the first signal logic low using the ground voltage when the voltage level of the cache register is changed from an initial state. The method of claim 1, And a pass / fail detector that determines that erase is a fail when the first signal is at the first voltage level and that erase is a pass when the first signal is in a floating state. The method of claim 4, wherein The pass / fail detection unit may include a logic element configured to logically combine the first signal and a second signal for checking a pass / fail of the erase verification to output a pass / fail detection signal; And And a precharge transistor configured to precharge the input node to which the first signal is input among the input nodes of the logic element to logic high. The method of claim 1, And a precharge unit configured to precharge the sensing node to logic high for the erase verification. The method of claim 6, When the signal precharged to the sensing node is discharged to the memory cells connected to the first or second bit line, the data stored in the memory cell is erased, and the signal precharged to the sensing node is the first or second signal. The nonvolatile memory device of claim 1, wherein the data stored in the memory cells is not erased unless discharged to the memory cells connected to the second bit line. An array of memory cells connected to the first and second bit lines; And a page buffer connected to the first and second bit lines through a sensing node and having a main register and a cache register. If the data stored in the memory cells connected to the first or second bit line is not erased, the voltage level of the main register or the cache register is changed from an initial state, and the first or second bit line is changed. Maintaining a voltage level of the main register or the cache register in an initial state when data stored in the connected memory cells is erased; And When the voltage level of the main register or the cache register is changed to the initial state, the first signal for erasure verification is generated at the first voltage level, and when the voltage level of the main register or the cache register is maintained in the initial state. And erasing the first signal in a floating state. The method of claim 8, And determining that an erase operation is a fail when the first signal is generated at the first voltage level, and determining that the erase operation is a pass when the first signal is generated in a floating state. Way. The method of claim 8, When the voltage level of the main register or the cache register is changed from the initial state, the first signal is generated at a logic low level. When the voltage level of the main register or the cache register is maintained at the initial state, the first signal is floated. An erase verification method of a nonvolatile memory device generated by a. The method of claim 8, And precharging the sensing node for the erase verification. The method of claim 11, If the signal precharged to the sensing node is not discharged to the memory cells connected to the first or second bit line, the voltage level of the main register or the cache register is changed from an initial state and the signal is preconfigured to the sensing node. And maintaining the voltage level of the main register or the cache register in an initial state when the charged signal is discharged to the memory cells connected to the first or second bit line.

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