CN113257321B - Reading system and storage device of nonvolatile memory - Google Patents
Reading system and storage device of nonvolatile memory Download PDFInfo
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- CN113257321B CN113257321B CN202110644859.6A CN202110644859A CN113257321B CN 113257321 B CN113257321 B CN 113257321B CN 202110644859 A CN202110644859 A CN 202110644859A CN 113257321 B CN113257321 B CN 113257321B
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- 238000010586 diagram Methods 0.000 description 12
- 230000009286 beneficial effect Effects 0.000 description 3
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- 238000012986 modification Methods 0.000 description 2
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a reading system and a storage device of a nonvolatile memory, wherein the reading system comprises a data caching unit, a storage unit, a data reading unit connected with the data caching unit and the storage unit, and a gating unit connected with the data reading unit, and the gating unit is used for enabling data in the data caching unit to be written into the storage unit, enabling the data reading unit to read data from the data caching unit or enabling the data reading unit to read data from the storage unit. The reading system can read the data of the storage unit and the data written into the data caching unit by arranging the gating unit. The reading system can read the data which is transmitted into the data cache unit by the memory write operation without adding a register additionally, and solves the problem that all the data transmitted by the read or record write operation occupy excessive chip area.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a reading system and a storage device for a nonvolatile memory.
Background
The data writing process of the charged erasable programmable read-only memory ((Electrically Erasable Programmable read only memory, EEPROM) comprises the steps of firstly buffering data in a data buffer unit consisting of high-voltage devices after the data are transmitted to the EEPROM, starting an internal erasing period after the writing communication is finished, generating high voltage by a charge pump, and selectively applying the high voltage to a storage unit through a bit line to finish the programming operation of the EEPROM.
In some cases, the memory chip may need to record all data that is incoming for a certain write operation, such as: nonvolatile memory containing error correction algorithms (Error Checking and Correcting, ECC) require verification and encoding of the written data; after the erasing period is finished, the EEPROM memory with high reliability needs to check whether the data transmitted by the writing operation is consistent with the data actually written into the memory.
In the prior art, registers can be used for recording all data input by a write operation, but adding the registers additionally increases the chip area, for example, the page size of a nonvolatile memory unit of a 512-Kbit serial port is 128bytes, and a maximum transmission of 128×8 total 1024 bits of data is allowed, so 1024 additional registers are needed, and the area of the nonvolatile memory is excessively large. Since the chip area of the non-volatile memory is not required to be too large, adding registers to record all data incoming from a write operation is not a good solution for EEPROM memory. For data in the data cache unit which is already input, there is almost no reading system in the prior art for directly reading the data input from the data cache unit of the EEPROM memory.
The invention patent application with publication number of CN103295639A discloses a writing and reading system of fast OTP memory data, which comprises an OTP unit data input and output end, a writing circuit and a reading system, wherein the OTP unit data input and output end is respectively connected with the writing circuit and the reading system. The invention has simple structure, stable programming and high reading speed, and can ensure the service life of OTP. Although the invention discloses a writing and reading system for storage data, the invention does not disclose a function of recording data written into a storage unit of a memory for a certain time, namely the reading system does not have the capability of reading the data written into the storage unit.
Therefore, it is necessary to provide a reading system and a storage device for a nonvolatile memory to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a reading system and a storage device of a nonvolatile memory, which are used for solving the problem that all data transmitted by a single write operation are read or recorded and occupy excessive chip area.
To achieve the above object, a reading system of a nonvolatile memory of the present invention includes:
the data caching unit is used for caching data;
a storage unit for storing data;
the data reading unit is connected with the data caching unit and the storage unit;
and the gating unit is connected with the data reading unit and is used for enabling the data in the data caching unit to be written into the storage unit, enabling the data reading unit to read the data from the data caching unit or enabling the data reading unit to read the data from the storage unit.
The reading system of the nonvolatile memory has the beneficial effects that:
the invention is provided with the gating unit which is used for enabling the data in the data caching unit to be written into the storage unit, enabling the data reading unit to read the data from the data caching unit or enabling the data reading unit to read the data from the storage unit, so that the reading system of the invention can read the data of the storage unit and the data written into the data caching unit by the memory through writing operation. The reading system can read the data which is transmitted into the data cache unit by the memory write operation without adding a register, and solves the problem that all the data transmitted by a certain write operation occupy excessive chip area.
Preferably, the gating unit is a tri-state inverter.
Preferably, the tri-state inverter comprises a first inverter, a second inverter, a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube;
the source electrode of the third PMOS tube is connected with the power supply voltage end of the cache unit, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the fourth PMOS tube and the drain electrode connecting line of the third NMOS tube are connected with the programming and erasing voltage end of the data reading unit; the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is grounded;
the output end of the first inverter is connected with the grid electrode of the third PMOS tube, the input end of the second inverter is connected with the grid electrode of the fourth PMOS tube, and the output end of the second inverter is connected with the grid electrode of the third NMOS tube.
Further preferably, in the erasing stage, the input end of the second inverter receives an erasing signal, so that the fourth PMOS transistor and the third NMOS transistor are turned off, and the program erasing voltage end is in a floating state;
in a programming stage, an input end of the first inverter receives a programming signal, the third PMOS tube and the fourth PMOS tube are conducted, and the programming erasing voltage end is connected with the power supply voltage end;
and in the stage of reading the data cache unit, the grid electrode of the fourth NMOS tube receives a reading signal, so that the fourth NMOS tube and the third NMOS tube are conducted, and the programming erasing voltage is grounded. The beneficial effects are that: the three-state inverter controls the programming erasing voltage end to be respectively connected with different potentials in the erasing phase, the programming phase and the reading phase of the memory, thereby completing different control of the data reading unit in different operation phases of the memory.
Preferably, the data buffer unit includes a third inverter, a fourth inverter, a first gating NMOS and a second gating NMOS, where the third inverter and the fourth inverter are connected; the third inverter comprises a first PMOS tube and a first NMOS tube, wherein a source electrode of the first PMOS tube is connected with a power supply voltage end, a grid electrode of the first PMOS tube is connected with a grid electrode of the first NMOS tube, a drain electrode of the first PMOS tube is connected with a drain electrode of the first NMOS tube, and a source electrode of the first NMOS tube is grounded; the fourth inverter comprises a second PMOS tube and a second NMOS tube, wherein the source electrode of the second PMOS tube is connected with the power supply voltage end, the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded;
the drain electrode of the first gating NMOS tube is connected with a first data input line, the grid electrode of the first gating NMOS tube is connected with a gating control line, and the source electrode of the first gating NMOS tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube; the source electrode of the second gating NMOS tube is connected with a second data input line, the grid electrode of the second gating NMOS tube is connected with the gating control line, and the drain electrode of the second gating NMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube;
the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with a first detection node on a connecting line of the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube, and the drain electrode of the first PMOS tube and a second detection node on a drain electrode connecting line of the first NMOS tube are connected with the grid electrode of the second PMOS tube and the second NMOS tube.
Preferably, the data reading unit includes a gate tube, a fourth gate NMOS tube and a sense amplifier, the gate tube is connected to the program erase voltage end, the gate tube is connected to the memory unit through a bit line, a source electrode of the fourth gate NMOS tube is connected to the bit line, a drain electrode of the fourth gate NMOS tube is connected to an input end of the sense amplifier, a gate electrode of the fourth gate NMOS tube is connected to a signal control line, and the sense amplifier outputs a logic value level according to a current signal or a voltage signal on the bit line.
Preferably, the gate tube is a third gate NMOS tube, a gate electrode of the third gate NMOS tube is connected to the data buffer unit, a drain electrode of the third gate NMOS tube is connected to the program erase voltage terminal, and a source electrode of the third gate NMOS tube is connected to the bit line.
Preferably, the gate tube is a gate PMOS tube, a source electrode of the gate PMOS tube is connected to the program erase voltage terminal, a gate electrode of the gate PMOS tube is connected to the data buffer unit, and a drain electrode of the gate PMOS tube is connected to the bit line.
Preferably, the memory cell includes a fifth gating NMOS transistor and a memory control gate transistor, wherein a drain electrode of the fifth gating NMOS transistor is connected to the bit line, a gate electrode of the fifth gating NMOS transistor is connected to the word line, a source electrode of the fifth gating NMOS transistor is connected to the drain electrode of the memory gate control transistor, a source electrode of the memory cell control gate transistor is connected to the source line, and a gate electrode of the memory cell control gate transistor is connected to the memory control line.
The invention also provides a storage device comprising the reading system of the nonvolatile memory.
The storage device of the invention has the beneficial effects that:
the reading system of the nonvolatile memory contained in the storage device can read the data of the storage unit and also can read the data written into the data cache unit by the memory through a writing operation. The reading system can read the data which is input into the data cache unit by the memory write operation without adding a register additionally, thereby saving the chip area.
Drawings
FIG. 1 is a block diagram of a read system of a nonvolatile memory according to the present invention;
FIG. 2 is a circuit diagram of a read system of a nonvolatile memory according to the present invention;
FIG. 3 is a circuit diagram of a tri-state inverter of the present invention;
FIG. 4 is a circuit diagram illustrating a memory of the present invention in a programming operation;
FIG. 5 is a circuit diagram illustrating the memory of the present invention when performing a read operation for data in a memory cell;
FIG. 6 is a circuit diagram illustrating the memory of the present invention when performing a data read operation in a data cache unit.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
Aiming at the problems existing in the prior art, the embodiment of the invention provides a reading system and a storage device of a nonvolatile memory. Fig. 1 is a block diagram showing a configuration of a reading system of a nonvolatile memory according to the present invention. Referring to fig. 1, the read system of the nonvolatile memory of the present invention includes:
a data caching unit 1 for caching data;
a storage unit 4 for storing data; the memory cell 4 of the present invention may be a charged erasable programmable read-only memory cell (Electrically Erasable Programmable read only memory, EEPROM).
A data reading unit 2 connected to the data buffer unit 1 and the storage unit 4;
and a strobe unit 3 connected to the data reading unit 2, for writing the data in the data buffer unit 1 into the storage unit 4, for causing the data reading unit 2 to read the data from the data buffer unit 1, or for causing the data reading unit 2 to read the data from the storage unit 4.
The high voltage generating unit 6, the power voltage terminal VPP of the data buffer unit 1 is connected with the output terminal of the high voltage generating unit 6, and the high voltage generating unit 6 is used for providing power voltage for the data buffer unit 1;
the logic control unit 7, several output ends of the logic control unit 7 are respectively connected with the high voltage generating unit 6, the data reading unit 2 and the data caching unit 1, and are used for controlling the high voltage generating unit 6, the data reading unit 2 and the data caching unit 1.
And one end of the word line driving unit 8 is connected with the 1 logic control unit, and the other end of the word line driving unit 8 is connected with the memory unit 4 for controlling the level of the word line and further controlling the memory unit 4.
It should be noted that the high voltage generating unit 6, the logic control unit 7, and the word line driving unit 8 are all well known techniques commonly used by those skilled in the art, and will not be described herein.
The reading system of the nonvolatile memory has the advantages that:
the data reading unit 2 of the present invention is connected to the data caching unit 1, and the data reading unit 2 is selectively connected to the high voltage generating unit 6 or grounded or floated through the gating unit 3, so that the data in the data caching unit 1 is written into the storage unit 4, the data reading unit 2 is made to read data from the data caching unit 1, or the data reading unit 2 is made to read data from the storage unit 4, thereby enabling the reading system of the present invention to read not only the data of the storage unit 4 but also the data written into the data caching unit 1 through a write operation. The reading system can read the data which is input into the data cache unit by the memory write operation without adding a register, and the added gating unit has small structural area and small occupied chip area.
As a preferred embodiment of the present invention, the gating unit 3 is a tri-state inverter.
Fig. 3 is a circuit diagram of a tri-state inverter of the present invention as a preferred embodiment of the present invention. Referring to fig. 1 and 3, the tri-state inverter includes a first inverter 30, a second inverter 31, and a third PMOS tube 32, a fourth PMOS tube 33, a third NMOS tube 34, and a fourth NMOS tube 35, which are sequentially connected in series; the source electrode of the third PMOS transistor 32 is connected to the power supply voltage terminal VPP of the data buffer unit 1, that is, the source electrode of the third PMOS transistor 32 is connected to the high voltage generating unit 6, the drain electrode of the third PMOS transistor 32 is connected to the source electrode of the fourth PMOS transistor 33, the drain electrode of the fourth PMOS transistor 33 is connected to the drain electrode of the third NMOS transistor 34, and the drain electrode of the fourth PMOS transistor 33 and a node on a drain electrode connection line of the third NMOS transistor 34 are connected to the program erase voltage terminal VPPW of the data reading unit 2; the source electrode of the third NMOS tube 34 is connected to the drain electrode of the fourth NMOS tube 35, and the source electrode of the fourth NMOS tube 35 is grounded; the output end of the first inverter 30 is connected to the gate of the third PMOS transistor 32, the input end of the second inverter 31 is connected to the gate of the fourth PMOS transistor 33, and the output end of the second inverter 31 is connected to the gate of the third NMOS transistor 34.
As a preferred embodiment of the present invention, during the erase phase of the memory of the present invention, the input terminal of the second inverter 31 receives the erase signal, so that the fourth PMOS transistor 33 and the third NMOS transistor 35 are turned off, and the program erase voltage terminal VPPW is in a floating state;
in the programming phase, the input end of the first inverter 30 receives a programming signal, the third PMOS transistor 32 and the fourth PMOS transistor 33 are turned on, and the program-erase voltage terminal VPPW is connected to the power supply voltage terminal of the data buffer unit 1, that is, the program-erase voltage terminal VPPW is connected to the high voltage generating unit 6;
in the data reading stage of the data cache unit 1, the gate of the fourth NMOS transistor 34 receives a read signal, so that the fourth NMOS transistor 35 and the third NMOS transistor 34 are turned on, and the program erase voltage VPPW is grounded. The advantages are that: the tri-state inverter controls the programming erasing voltage terminal to be respectively connected with different potentials in the erasing stage, the programming stage and the reading stage of the memory, thereby completing different control of the data reading unit of the memory in different operation stages, and respectively enabling the data in the data cache unit 1 to be written into the memory unit 4, enabling the data reading unit 2 to read data from the data cache unit 1 or enabling the data reading unit 2 to read data from the memory unit 4.
Fig. 2 is a circuit diagram of a reading system of the nonvolatile memory according to the present invention as a preferred embodiment of the present invention. Referring to fig. 2, the data buffer unit 1 includes a third inverter 10, a fourth inverter 11, a first gating NMOS transistor 12 and a second gating NMOS transistor 13, a first data input line 14, a second data input line 15, and a gating control line 16, the third inverter 10 and the fourth inverter 11 being connected; the source electrode of the first gating NMOS 12 is connected to the third inverter 10, the drain electrode of the first gating NMOS 12 is connected to the first data input line 14, and the gate electrode of the first gating NMOS 12 is connected to the gating control line 16; the drain electrode of the second gating NMOS transistor 13 is connected to the fourth inverter 11, the source electrode of the second gating NMOS transistor 13 is connected to the second data input line 15, and the gate electrode of the second gating NMOS transistor 13 is connected to the gating control line 16.
The third inverter 10 includes a first PMOS transistor 101 and a first NMOS transistor 102, where a source of the first PMOS transistor 101 is connected to a supply voltage VPP, that is, a source of the first PMOS transistor 101 is connected to the high voltage generating unit 6, a gate of the first PMOS transistor 101 is connected to a gate of the first NMOS transistor 102, a drain of the first PMOS transistor 101 is connected to a drain of the first NMOS transistor 102, and a source of the first NMOS transistor 102 is grounded. The fourth inverter 11 includes a second PMOS transistor 111 and a second NMOS transistor 112, where a source of the second PMOS transistor 111 is connected to the power supply voltage VPP, that is, a source of the second PMOS transistor 111 is connected to the high voltage generating unit 6, a gate of the second PMOS transistor 111 is connected to a gate of the second NMOS transistor 112, a drain of the second PMOS transistor 111 is connected to a drain of the second NMOS transistor 112, and a source of the second NMOS transistor 112 is grounded.
The drain electrode of the first PMOS transistor 101 is connected with the drain electrode of the first NMOS transistor 102 to connect with the source electrode of the first gating NMOS transistor 12; a drain electrode of the first PMOS transistor 101 is connected to a first detection node Q on a drain electrode connection line of the first NMOS transistor 102, to a gate electrode of the second PMOS transistor 111 and a gate electrode of the second NMOS transistor 112; a second detection node QB on a connection line between the drain of the second PMOS transistor 111 and the drain of the second NMOS transistor 112 connects the gate of the first PMOS transistor 101 and the gate of the first NMOS transistor 102; the drain electrode of the second PMOS transistor 111 and the drain electrode of the second NMOS transistor 112 are connected to the drain electrode of the second gating NMOS transistor 13. The data reading unit 2 connects any one of the first detection node Q and the second detection node QB.
As a preferred embodiment of the present invention, the data reading unit 2 includes a gate tube 20, a fourth gate NMOS tube 22, and a sense amplifier 23, wherein a current output end of the gate tube 20 is connected to the bit line 5, a drain electrode of the fourth gate NMOS tube 22 is connected to the bit line 5, a source electrode of the fourth gate NMOS tube 22 is connected to an input end of the sense amplifier 23, a gate electrode of the fourth gate NMOS tube 22 is connected to a signal control line 221, and the sense amplifier 23 outputs a logic value level according to a current signal or a voltage signal on the bit line 5.
Referring to fig. 1 and 2, a signal control line 221 is connected to the logic control unit 7, and the signal control line 221 of the fourth gating NMOS transistor 22 is used to read an enable signal outputted from the logic control unit 7 to control the fourth gating NMOS transistor 22 to be turned on and off.
As a preferred embodiment of the present invention, referring to fig. 2, the gate tube 20 of the present invention includes a third gate NMOS tube 201, a gate of the third gate NMOS tube 201 is connected to the second node QB, a drain of the third gate NMOS tube 201 is connected to the program erase voltage terminal VPPW, and a source of the third gate NMOS tube 201 is connected to the bit line 5.
The memory cell 4 includes a memory control gate tube 40 and a fifth gate NMOS tube 41, wherein a drain electrode of the fifth gate NMOS tube 41 is connected to the bit line 5, a drain electrode of the memory control gate tube 40 is connected to a source electrode of the fifth gate NMOS tube 41, a source electrode of the memory control gate tube 40 is connected to a source line 401, and a gate electrode of the memory control gate tube 40 is connected to a memory control line 402. The gate of the fifth gating NMOS transistor 41 is connected to the word line 411, and the source of the fifth gating NMOS transistor 41 is connected to the memory cell 4.
Referring to fig. 1 and 2, the word line 411 is connected to the word line driving unit 8, and the logic control unit 7 outputs an enable signal to enable the word line driving unit 8, thereby controlling the level of the word line 411 and further controlling the fifth gate NMOS transistor 41 to be turned on or off.
Referring to fig. 1 and 2, the operation steps of writing data into the data cache unit 1 are as follows:
the first gating NMOS transistor 12 and the second gating NMOS transistor 13 are both turned on, if the logic value level of the first data input line 14 is "1", the logic value level of the second data input line 15 is "0", the logic value of the first detection node Q is "1", the logic value of the second detection node QB is "0", and at this time, the data transferred to the data buffer unit 1 is "1", and the third gating NMOS transistor 201 is in an off state.
If the logic value level of the first data input line 14 is "0", the logic value level of the second data input line 15 is "1", the logic value of the first detection node Q is "0", the logic value of the second detection node QB is "1", the data transmitted to the data buffer unit 1 is "0", and the third gating NMOS transistor 201 is in the on state.
Note that, when the gate pipe 20 is the third gate NMOS pipe 201, the logic level of the gate of the third gate NMOS pipe 201 is opposite to the data written into the data buffer unit 1. For example: if the logic value level of the first data input line 14 is "1", the logic value level of the second data input line 15 is "0", the data transmitted to the data buffer unit 1 is "1", the logic value of the second detection node QB is "0", the gate logic level of the third gating NMOS transistor 201 is "0", and the third gating NMOS transistor 201 is turned off; if the logic value level of the first data input line 14 is "0", the logic value level of the second data input line 15 is "1", the data transmitted to the data buffer unit 1 is "0", the logic value of the second detection node QB is "1", the gate logic level of the third gating NMOS transistor 201 is "1", and the third gating NMOS transistor 201 is turned on.
In another embodiment of the present invention, the gate tube 20 may be a gate PMOS tube (not shown in the figure), where a source of the gate PMOS tube is connected to the program erase voltage terminal, a gate of the gate PMOS tube is connected to the first detection node Q, and a drain of the gate PMOS tube is connected to the bit line. When the gate tube 20 is a gating PMOS tube, the logic level of the gate electrode of the gating PMOS tube is the same as the data written into the data cache unit 1. For example: if the logic level of one data input line 14 is "1", and the logic level of the second data input line 15 is "0", the logic level of the gate of the gating PMOS transistor is "1", and the gating PMOS transistor is turned off; if the logic level of one data input line 14 is "0" and the logic level of the second data input line 15 is "1", the gate logic level of the gating PMOS transistor is "0", and the gating PMOS transistor is turned on.
The following describes the operation steps of the nonvolatile memory reading system of the present invention with reference to the specific embodiments:
fig. 4 is a circuit diagram of the memory of the present invention when performing a programming operation. Referring to fig. 1 and 4, the programming operation of the memory of the present invention is as follows:
the logic control unit 7 outputs an enable signal to the signal control line 221 to turn off the fourth gate NMOS transistor 22, and the bit line 5 is disconnected from the sense amplifier 23. The logic control unit 7 controls the high voltage generating unit 6 to generate and output a high voltage signal to the power supply voltage terminal VPP, and is connected with the program erase voltage terminal VPPW and the power supply voltage terminal VPP through the gating unit 3, so that the program erase voltage terminal VPPW receives the high voltage signal; word line 411 selects memory cell 4, memory control line 402 is grounded, and source line 401 is in a floating state. The third gating NMOS transistor 201 is turned on, and the high voltage signal of the high voltage generating unit 6 is applied to the bit line 5 through the third gating NMOS transistor 201, and at this time, the memory cell 4 selected by the bit line 5 and the word line 411 together may be programmed.
FIG. 5 is a circuit diagram of the memory according to the present invention when the memory performs a read operation. Referring to fig. 1 and 5, the operation of reading data in the memory cell 4 of the present invention is as follows:
the logic control unit 7 outputs an enable signal to the signal control line 221, thereby controlling the fourth gating NMOS transistor 22 to be turned on. The word line 411 selects the memory cell 4 to be read, the memory control line 402 is connected to the sense voltage VSENSE, the source line 401 is grounded, and the sense amplifier 23, the bit line 5, and the memory cell 4 are connected to the ground. The gating unit 3 makes the program erase voltage terminal VPPW in a floating state, and the paths from the sense amplifier 23, the bit line 5, and the third gating NMOS transistor 201 to the ground terminal are disconnected.
At this time, if the bit line 5 and the word line 411 select the programmed memory cell 4, then current flows through the bit line 5, and the current flows to the sense amplifier 23→the fourth gating NMOS transistor 22→the bit line 5→the fifth gating NMOS transistor 41→the memory cell control gate transistor 40 in sequence, and the sense amplifier 23 reads out the logic value output "0";
if the bit line 5 and the word line 411 are selected as the unprogrammed memory cell 4, no current flows through the bit line 5 and the sense amplifier 23 senses a logic value output "1".
It can be stated that the memory is also in a floating state at the program erase voltage VPPW during the erase operation.
FIG. 6 is a circuit diagram illustrating the memory of the present invention when performing a data read operation in a data cache unit. Referring to fig. 1 and 6, the operation of the memory of the present invention for reading data in the data cache unit is as follows:
the operation of reading the data in the data buffer unit 1 is similar to the operation of reading the data in the memory unit 4, and the logic control unit 7 outputs an enable signal to the signal control line 221, thereby turning on the fourth gating NMOS transistor 22. But the logic control unit 7 controls the word line driving unit 8 to make all word lines in a non-selected state or to float the source line 401, thereby disconnecting the sense amplifier 23, the bit line 5, the fifth gating NMOS transistor 41, the memory cell 4 and the path to ground. The program erase voltage terminal VPPW is grounded through the gate unit 3.
If the third gating NMOS transistor 201 is in the on state, the third gating NMOS transistor 201 is in the on state when the data written into the data buffer unit 1 is "0", so that the data written into the data buffer unit 1 is determined to be "0" when the third gating NMOS transistor 201 is in the on state, as known from the above operation steps of writing data into the data buffer unit 1. When the third gating NMOS transistor 201 is in a conducting state, a current flows through the bit line 5, and the current flows to the sense amplifier 23- & gt the fourth gating NMOS transistor 22- & gt the bit line 5- & gt the third gating NMOS transistor 201- & gt the programming and erasing voltage terminal VPPW. The sense amplifier 23 reads out the logical value output "0" as the same as the data "0" written into the data buffer unit 1.
If the third gating NMOS transistor 201 is in the off state, the above operation steps of writing data into the data buffer unit 1 can determine that the data written into the data buffer unit is "1" when the data written into the data buffer unit is "1", because the third gating NMOS transistor 201 is in the off state. When the third gating NMOS transistor 201 is turned off, no current flows through the bit line 5, and the sense amplifier 23 reads out the logical value output "1", which is the same as the data "1" written into the data buffer unit 1.
The present invention time-multiplexes the gate tube 20 for controlling the programming operation and the sense amplifier for the reading operation, thereby avoiding the use of additional circuits or registers to read the data written into the data buffer unit, thereby reducing the complexity of the circuit and the area of the memory chip. The data reading unit 2 of the present invention can read data from the data caching unit 1, i.e., can record data of the largest page in the data caching unit 1, which is input by a write operation.
The invention also provides a storage device comprising the reading system of the nonvolatile memory.
The memory of the invention has the advantages that:
the reading system of the invention can not only read the data of the storage unit, but also read the data written into the data caching unit by the memory through writing operation. The reading system can read the data which is input into the data cache unit by the memory write operation without adding a register additionally, thereby saving the chip area.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (8)
1. A system for reading a nonvolatile memory, comprising:
the data caching unit is used for caching data;
a storage unit for storing data;
the data reading unit is connected with the data caching unit and the storage unit;
a strobe unit connected to the data reading unit, for writing the data in the data caching unit into the storage unit, reading the data from the data caching unit by the data reading unit, or reading the data from the storage unit by the data reading unit;
the data caching unit comprises a third inverter, a fourth inverter, a first gating NMOS tube and a second gating NMOS tube, wherein the third inverter is connected with the fourth inverter; the third inverter comprises a first PMOS tube and a first NMOS tube, wherein a source electrode of the first PMOS tube is connected with a power supply voltage end, a grid electrode of the first PMOS tube is connected with a grid electrode of the first NMOS tube, a drain electrode of the first PMOS tube is connected with a drain electrode of the first NMOS tube, and a source electrode of the first NMOS tube is grounded; the fourth inverter comprises a second PMOS tube and a second NMOS tube, wherein the source electrode of the second PMOS tube is connected with the power supply voltage end, the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded;
the drain electrode of the first gating NMOS tube is connected with a first data input line, the grid electrode of the first gating NMOS tube is connected with a gating control line, and the source electrode of the first gating NMOS tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube; the source electrode of the second gating NMOS tube is connected with a second data input line, the grid electrode of the second gating NMOS tube is connected with the gating control line, and the drain electrode of the second gating NMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube;
the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with a first detection node on a connecting line of the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube, and the drain electrode of the first PMOS tube and a second detection node on a drain electrode connecting line of the first NMOS tube are connected with the grid electrode of the second PMOS tube and the second NMOS tube;
the data reading unit comprises a gate tube, a fourth gate NMOS tube and a sense amplifier, wherein the gate tube is connected with a programming erasing voltage end, the gate tube is connected with the storage unit through a bit line, a source electrode of the fourth gate NMOS tube is connected with the bit line, a drain electrode of the fourth gate NMOS tube is connected with an input end of the sense amplifier, a grid electrode of the fourth gate NMOS tube is connected with a signal control line, and the sense amplifier outputs a logic value level according to a current signal or a voltage signal on the bit line.
2. The reading system of claim 1, wherein the gating cell is a tri-state inverter.
3. The reading system of claim 2, wherein the tri-state inverter comprises a first inverter, a second inverter, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
the source electrode of the third PMOS tube is connected with the power supply voltage end of the cache unit, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the fourth PMOS tube and the drain electrode connecting line of the third NMOS tube are connected with the programming and erasing voltage end of the data reading unit; the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is grounded;
the output end of the first inverter is connected with the grid electrode of the third PMOS tube, the input end of the second inverter is connected with the grid electrode of the fourth PMOS tube, and the output end of the second inverter is connected with the grid electrode of the third NMOS tube.
4. The reading system of claim 3, wherein during an erase phase, an input of the second inverter receives an erase signal such that the fourth PMOS transistor and the third NMOS transistor are turned off and the program erase voltage terminal is in a floating state;
in a programming stage, an input end of the first inverter receives a programming signal, the third PMOS tube and the fourth PMOS tube are conducted, and the programming erasing voltage end is connected with the power supply voltage end;
and in the stage of reading the data cache unit, the grid electrode of the fourth NMOS tube receives a reading signal, so that the fourth NMOS tube and the third NMOS tube are conducted, and the programming erasing voltage is grounded.
5. The reading system of claim 1 wherein the gate is a third gate NMOS, a gate of the third gate NMOS is connected to the data buffer unit, a drain of the third gate NMOS is connected to the program erase voltage terminal, and a source of the third gate NMOS is connected to the bit line.
6. The reading system of claim 1 wherein the gate tube is a gate PMOS tube, a source of the gate PMOS tube is connected to the program erase voltage terminal, a gate of the gate PMOS tube is connected to the data buffer unit, and a drain of the gate PMOS tube is connected to the bit line.
7. The reading system of claim 1, wherein the memory cell comprises a fifth gating NMOS transistor and a memory control gate transistor, a drain of the fifth gating NMOS transistor being connected to the bit line, a gate of the fifth gating NMOS transistor being connected to a word line, a source of the fifth gating NMOS transistor being connected to the drain of the memory gate control transistor, a source of the memory cell control gate transistor being connected to a source line, a gate of the memory cell control gate transistor being connected to a memory control line.
8. A storage device comprising a reading system as claimed in any one of claims 1-7.
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| KR20060070030A (en) * | 2004-12-20 | 2006-06-23 | 주식회사 하이닉스반도체 | Non-volatile memory device and method for verifying successful erasing thereof |
| KR100783999B1 (en) * | 2006-10-31 | 2007-12-07 | 주식회사 하이닉스반도체 | The method for reading a non-volatile memory device |
| CN102411990A (en) * | 2011-11-11 | 2012-04-11 | 上海新储集成电路有限公司 | Bit-level twin-port nonvolatile static random access memory and implementation method thereof |
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| US7136296B2 (en) * | 2005-02-28 | 2006-11-14 | International Business Machines Corporation | Static random access memory utilizing gated diode technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20060070030A (en) * | 2004-12-20 | 2006-06-23 | 주식회사 하이닉스반도체 | Non-volatile memory device and method for verifying successful erasing thereof |
| KR100783999B1 (en) * | 2006-10-31 | 2007-12-07 | 주식회사 하이닉스반도체 | The method for reading a non-volatile memory device |
| CN102411990A (en) * | 2011-11-11 | 2012-04-11 | 上海新储集成电路有限公司 | Bit-level twin-port nonvolatile static random access memory and implementation method thereof |
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