KR100403480B1 - Semiconductor Memory Device and Read/ Write Operation of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of reading and writing the same, wherein the semiconductor memory device of the present invention temporarily stores a memory area having a redundant memory area, data to be written to or read from the memory area. A data register for storing the data register, an input / output data line for applying external data to the data register or outputting temporarily stored data of the data register to the outside, a defective column address of the memory area, and a redundant column address substituted therein. A redundant control unit for receiving a redundant information area, an externally applied input column address and column address information of the redundant information area, and outputting a register selection address, and a level for selecting one of the data registers based on the register selection address A master selection unit, an operation prohibition data generation unit which generates operation prohibition data of a read or write operation and applies the prohibition data to the data register through the input / output data line, and receives the temporary data and the operation prohibition data stored in the data register in the memory area. And a memory determination controller for controlling the read and write operations of the memory.

Description

Semiconductor memory device and read / write operation method using same {Semiconductor Memory Device and Read / Write Operation of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, when a memory cell included in a specific column of a main memory region is defective or a defect occurs in a specific column itself, data is replaced with a column of a redundant region. The present invention relates to a semiconductor memory device and a method having a redundancy capable of performing an operation of writing or reading data in a memory area.

Hereinafter, a conventional semiconductor memory device will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a conventional semiconductor memory device.

As shown in FIG. 1, a conventional semiconductor memory device having redundancy includes a main memory region 101 having an array structure of one or a plurality of word lines and columns, and a redundant memory region sharing the word lines with the memory region. A memory area 11 consisting of 102 and an input / output data line 12 for transferring data to the memory area 11 from outside or writing data to the memory area 11 or data read from the memory area 11 to the outside; ), A redundant information area 13 for storing a redundant column (b) address replaced with a defective column (a) address of the memory area 11, and the replaced redundant column (b) address and applied externally. An address control unit 14 that receives an input column address and outputs a register selection address and a column selection address; and a specific data register receiving the register selection address. A register selector 15 for selecting, a data register 16 for temporarily storing data for writing to the memory area 11 or data read from the memory area 11, and the memory area 11; The memory control unit 17 for controlling data read and write operations of the memory and a redundant column (b) of the redundant memory area 102 by receiving a column selection address when a defective column (a) of the main memory area 101 occurs. It consists of the column selection part 18 which selects.

The memory area 11 has an array structure of one or a plurality of columns and word lines, and has a main memory area 101 and a redundant memory area 102 therein. The redundant memory region 102 is composed of a redundant column (b) which is replaced by a defective column (a) when the defective column (a) occurs in the main memory region (101), and the word line of the main memory region (101). And wordlines are shared.

Data read out from the memory area 11 and written into the memory area 11 are temporarily stored in the data register 16, and the data register 16 and the outside are transferred to the input / output data line 12. Connected.

At this time, the redundant information area 13 stores the address of the defective column (a) of the main memory area 101 and the address of the redundant column (b) of the redundant memory area 102 replaced therewith.

The address control unit 14 receives redundant column information, such as a defective column (a) address and a redundant column (b) address, and a register selection address for providing information for selecting the data register 16 by receiving an external input column address. And a column selection address giving information about a normal column on the memory area 11.

The register selector 15 receives the register selection address and selects a specific data register 16 in which read and write information of the memory area 11 is stored.

The memory controller 17 applies a control signal to the column selector 18 to control an operation of writing or externally reading information temporarily stored in the data register 16 to the memory region 11.

The column selector 18 selects a normal column of the main memory area 101 when there is no defect, according to the control signal of the memory controller 11 and the column selection address output from the address controller 14. Replaces the defective column of the main memory area 101 to select and drive the redundant column of the redundant memory area 102.

In order to operate the defective column a of the main memory area 101 independently of read and write operations and select and operate the redundant column b of the redundant memory area 102, the column selection address of the address control unit 14 is changed. And a column selector 18 capable of selecting one column from all the columns of the memory area 11 is required. However, since there may be a defect in which column of the main memory area 101, the column selector 18 must be provided as many as the total number of columns for selecting one column separately, so that the number of circuits is increased, thereby increasing the chip size. .

However, the conventional semiconductor memory device as described above has the following problems.

If a memory cell included in a specific column of the main memory area is defective or a specific column itself is defective, it can be replaced with a column of the redundant memory area to write data in the memory area or read data in the memory area. In the semiconductor memory device, if the defective column is not physically or logically completely independent, there is a possibility of causing an operation error due to a large leakage current flowing into the defective column during the read or write operation of the normal column, and also the physically defective column. To be independent, the number of circuits that must be added to select the defective column and the normal column becomes practically impossible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a memory determination controller for controlling an operation of writing a data or reading data in a memory area between a memory register and an input / output data line. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device and a read and write method using the same, in which a defective column in a memory area is logically completely isolated from a read or write operation without adding a plurality of column selectors.

1 is a block diagram showing a conventional semiconductor memory device

2 is a block diagram illustrating a semiconductor memory device of the present invention.

3 is a flow chart showing the flow of the read operation of FIG.

4 is a flowchart illustrating a flow of a write operation of FIG. 2.

Explanation of symbols for the main parts of the drawings

21: memory area 22: input / output line

23: redundant information area 24: redundant control unit

25: register selection unit 26: operation prohibited data generation unit

27: data register 28: memory determination control unit

201: main memory area 202: redundant memory area

a: defective column b: redundant column to be replaced

The present invention for achieving the above object consists of a main memory area of one or a plurality of word lines and columns configured in an array structure and a redundant memory area composed of one or a plurality of columns sharing a word line of the main memory area. A memory area, one or more data registers for temporarily storing data to be written to or read from the memory area, and external data to the data register or data stored in the data register to the outside A semiconductor memory device comprising output I / O data lines, comprising: a redundant information area for storing a column address of a redundant memory area replaced with a defective column address of a main memory area in the memory area, and an input column applied externally A redundant control unit for receiving the address and column address information of the redundant information area and outputting a register selection address, a register selection unit for selecting one of the data registers according to the register selection address, and operation prohibited data for a read or write operation. And an operation prohibition data generation unit configured to apply the data register to the data register through the input / output data line, and a memory determination control unit that receives temporary data and operation prohibition data stored in the data register and controls read and write operations of the memory area. Characterized in that configured.

Hereinafter, a semiconductor memory device and a read and write method using the same will be described with reference to the accompanying drawings.

2 is a block diagram illustrating a semiconductor memory device of the present invention.

As illustrated in FIG. 2, in the semiconductor memory device of the present invention, one or more columns shared with the word line of the main memory area 201 and the main memory area 201 having one or more word lines and columns arranged in an array structure. A memory area 21 including a redundant memory area 202 configured to transmit the data read from the memory area 21 to an external device or an external input / output line 22 to transmit external data to the memory area 21; The redundant information area 23 in which the redundant column b address of the redundant memory area 202 is replaced with the defective column a address of the main memory area 201 in the memory area 21 and externally. A redundant control unit 24 which receives an input input column address and redundant column address information of the redundant information area 23 and outputs a register selection address; Register selector 25 for selecting one of data registers 27 and operation inhibited data for generating read / write operation inhibited data and applying it to the data register 27 through the input / output data line. Section 26, one or more data registers 27 for temporarily storing data for writing to the memory area 21 or data read from the memory area 21, and stored in the data register 27; And a memory determination controller 28 that receives the temporary data and the operation inhibiting data and controls the read and write operations of the memory area 21.

The memory area 21 has an array structure of one or more word lines and one or more columns, and has a main memory area 201 and a redundant memory area 202 therein. The redundant memory area 202 shares a word line with the main memory area 201.

The data register 27 functions to temporarily store data that is read out from the memory area 21 and written out to the memory area 21 from the outside. 22).

The redundant information area 23 stores information about a defective column (a) address generated in the main memory area 201 in the memory area 21 and a redundant column (b) address to replace it.

In addition, the redundant information area 23 should be composed of one or more semiconductor memory cells to store the defective column (a) address of the main memory area 201 and the replaced redundant column (b) address of the redundant memory area 202. do.

The redundant controller 24 outputs a register selection address by receiving redundant column information such as the defective column (a) address and the redundant column (b) address and an input column address applied from the outside.

In addition, the redundant controller 24 receives redundant column information of the redundant information area 23 and corresponds to a defective column (a) of the main memory area 201 in which an input column address is replaced with a column of the redundant memory area 202. It is determined whether the register selection address is applied to the register selecting section 25.

The register selector 25 receives the register selection address to select a specific data register 27 from among the plurality of data registers 27.

The operation inhibiting data generation unit 26 generates the operation inhibiting data and applies it to the data register 27 through the input / output data line 22.

The operation prohibition data is stored in the selected data register 27.

The data register 27 corresponding to the replaced redundant column (b) address sent by the redundant controller 24 should store data corresponding to read or write prohibition and apply the information to the memory determination controller 28. The determination controller 28 should have a function of determining whether to perform the read or write operation by receiving data from the data register 27 before performing the read or write operation.

The memory determination controller 28 receives data from the data register 27 and decodes information on each column to control each column of the memory. The memory determination controller 28 may simultaneously control one or a plurality of columns, and the data register 27 may store data corresponding to the number of one or a plurality of columns of the memory area 21.

The memory determination controller 28 may simultaneously control one or a plurality of columns, and corresponds to a value obtained by dividing the total number of columns of the memory area 21 by the number of columns that the memory determination control unit 28 can simultaneously control. The number of column addresses is increased by the number, and a read or write operation is performed to read data of one or a plurality of word lines and an array structure of the memory area 21 or store data applied externally to all columns. .

That is, the semiconductor memory device of the present invention can completely isolate a defective column during a read or write operation of a normal column even without a column selector capable of selecting all columns.

3 is a flowchart illustrating a flow of a read operation of FIG. 2.

As shown in FIG. 3, the read operation of the semiconductor memory device of the present invention is as follows.

In the read operation, it is assumed that the column and the word line of the semiconductor memory device of the present invention are configured in plural, that is, array structures.

First, the data register is initialized (301). This is to ensure the reliability of all operations and data by making the initial state of all data registers 27 the same.

Then, the redundant control unit 24 is enabled to load read operation prohibition data into the data register 27 corresponding to the defective column a in the column of the main memory area 201 (302).

Therefore, data in the initial state is stored in the data register 27 corresponding to the normal column, and read operation prohibition data in a state logically opposite to the initial state is stored in the data register 27 corresponding to the defective column.

Subsequently, the data of the data register 27 is loaded into the memory determination controller 28 (303).

The memory determination controller 28 determines whether the data of the corresponding data register 27 is the read operation inhibited data (304), and if not the read operation inhibited data, selects the selected cell data in the column of the corresponding memory area 21. If it is read (305), if the read operation inhibited data, the memory determination controller 28 does not create any condition for the read operation in the column of the corresponding memory area 21 (306) to completely isolate the defective column from the read operation. Let's do it. By completely isolating the defective column (a) in this way, the leakage current to the defective column (a) can be cut off, thereby preventing any operation error by not affecting the read operation of the normal column.

As a result, when the read operation of the selected column is finished, the memory determination controller 28 corresponding to the defective column a stores the read operation prohibition data received from the data register 27 and the memory determination controller corresponding to the normal column ( In 28), the selected cell data of the corresponding column is stored.

When the data of the memory determination controller 28 is loaded 307 into the respective data registers 27, the cell data of the memory area 21 is stored in the respective data registers 27.

In the memory area 21, one or a plurality of word lines and one or a plurality of columns are configured in an array structure, and the memory determination controller 28 may simultaneously control one or a plurality of columns. Data corresponding to one or a plurality of columns of the memory area may be stored.

The memory determination controller 28 increases the column address by a number corresponding to a value obtained by dividing the number of columns that can be simultaneously controlled by the memory determination controller 28 in the total number of columns of the main memory area 201 and performs a read operation. Data of one or a plurality of word lines and an array structure of the main memory area 201 may be read and stored in the data register 27.

For example, if 2048 columns are configured in an array structure in one or a plurality of word lines of the main memory area 201, and the number of columns that the memory determination controller 28 can control at the same time is 64, a specific word line may be selected. After selecting and changing a total of 32 column addresses and storing the data in the data register 27, the 2048 memory cell data included in the 2048 columns can be read and stored in the data register 27.

Finally, the redundant controller 24 determines whether the input column address corresponds to a defective column of the main memory area 201 and is a column address replaced by a redundant column of the redundant memory area 202. In step 308, the register select address is applied to the input / output data line 22 to load the data of the data register 27 corresponding to the normal column.

4 is a flowchart illustrating a flow of a write operation of FIG. 2.

As shown in FIG. 4, the write operation of the semiconductor memory device of the present invention is performed as follows.

As in the read operation, the memory area is an array structure consisting of a plurality of columns and word lines.

First, the data register 27 is initialized (401). This is to ensure the reliability of all operations and data by making the initial state of all data registers 27 the same.

Then, the redundant control unit 24 is enabled to load write prohibition data into the data register 27 corresponding to the defective column a in the column of the main memory area 201 (402).

Then, data in the initial state is stored in the data register 27 corresponding to the normal column, and write operation prohibited data in a state logically opposite to the initial state is stored in the data register 27 corresponding to the defective column (a). .

The redundant control unit 24 compares the input column address with the redundant column information in the redundant information area 23, so that the input column address corresponds to a defective column in the main memory area 201, so that the redundant column b of the redundant memory area 202 is used. By determining whether or not the column address is replaced by the (), the register select address is applied to the register selector 25 to store the data of the input / output data line 22 in the data register 27 corresponding to the normal column (403).

As a result, data corresponding to the input column is stored in the data register 27 corresponding to the defective column and the write operation prohibition data is stored in the data register 27 corresponding to the replaced redundant column.

If one specific column address is applied and then the column address is continuously increased and the write data is continuously input, the column address is increased to the last column address and the data of the input / output data line 22 is read each time. Repeat the operation to save.

The data of the data register 27 is loaded 404 into the memory determination controller 28.

The memory determination controller 28 determines whether the data of the corresponding data register 27 is write operation inhibited data (405) and writes data to the selected cell in the column of the corresponding memory area if the data is not write operation inhibited data (405). 406, if the write operation inhibited data, the memory determination controller 28 does not create any condition for the write operation in the column of the corresponding memory area 21 (407) to completely isolate the defective column from the write operation.

By completely isolating the defective column, the leakage current to the defective column can be cut off, thereby preventing any operation error by not affecting the write operation of the normal column.

The memory area includes one or a plurality of word lines and one or a plurality of columns in an array structure, and the memory determination controller 28 may simultaneously control one or a plurality of columns, and the data register 27 may include a memory area ( Data corresponding to the number of one or a plurality of columns of 21) may be stored.

The memory determination controller 28 increases the column address by the number of times corresponding to a value obtained by dividing the number of columns that can be simultaneously controlled by the memory determination controller 28 in the total number of columns of the main memory area 201 to perform a write operation. When executed, data may be stored in one or a plurality of word lines and an entire column of an array structure of the main memory area 201.

For example, if 2048 columns are configured in an array structure in one or a plurality of word lines of the main memory area 201, and the number of columns that the memory determination controller 28 can control simultaneously is 64 columns in total, 32 columns. If the write operation is performed by changing addresses, data may be stored in 2048 memory cells selected in 2048 columns.

The semiconductor memory device of the present invention as described above has the following effects.

First, in the read or write operation of the semiconductor memory, the defective column is replaced with the redundant column by the control action of the memory determination controller, and the defective column is completely independent, thereby preventing the leakage current phenomenon flowing into the defective column, thereby preventing normal column operation. This interference can be solved to solve the problem that causes the error.

Secondly, a memory judgment control unit is provided between the memory area and the input / output data line and controls the operation of writing data to or reading data from the memory area. Independent of the defect column can solve the problem of increasing the memory chip size, unlike a semiconductor memory device in which many circuits for selecting the defect column and the normal column are added to make the defect column independent of the conventional hardware.

Claims (15)

A memory area comprising a main memory area having one or a plurality of word lines and columns arranged in an array structure, and a redundant memory area having one or a plurality of columns sharing word lines of the main memory area, and data for writing to the memory area; Or one or more data registers for temporarily storing data read from the memory area, and an input / output data line for applying external data to the data register or outputting data stored in the data register to the outside. In A redundant information area for storing a column address of the redundant memory area replaced with a defective column address of a main memory area in the memory area; A redundant controller which receives an input column address externally applied and column address information of the redundant information area and outputs a register selection address; A register selector for selecting one of the data registers by the register selection address; An operation prohibited data generation unit configured to generate operation prohibited data of a read or write operation and apply the operation prohibited data to the data register through the input / output data line; And a memory determination controller configured to control the read and write operations of the memory area in response to the temporary data and the operation inhibiting data stored in the data register. The semiconductor memory device of claim 1, wherein the data register stores data corresponding to one or more columns of the memory area. The semiconductor memory device according to claim 1, wherein the data register stores operation prohibition data of a read or write operation in a data register corresponding to a defective defective column address and applies the information to the memory determination controller. The semiconductor memory device of claim 1, wherein the redundant information area comprises one or more semiconductor memory cells. The register selector of claim 1, wherein the redundant control unit receives redundant column information of the redundant information area and determines whether an input column address corresponds to a defective column of the main memory area replaced with a column of the redundant memory area. And applying a selection address to the semiconductor memory device. The register selector of claim 1, wherein the redundant control unit receives redundant column information of the redundant information area to store operation prohibition data of a read or write operation in the data register corresponding to a defective column address of the main memory area. And applying a register selection address to the semiconductor memory device. The semiconductor memory device of claim 1, wherein the memory determination controller determines whether to perform a read or write operation by receiving data from the data register. The semiconductor memory device of claim 1, wherein the memory determination controller simultaneously controls one or a plurality of columns. The main memory device of claim 1, wherein the memory determination controller repeatedly reads or writes a number of times corresponding to a value obtained by dividing the number of columns that the memory determination control unit can simultaneously control from the total number of columns of the main memory area. And read or store data of all columns connected to one word line of a memory area. In a semiconductor memory device comprising a memory area composed of main and redundant memory areas, a redundant information area, a redundant control part, a register selecting part, an operation inhibiting data generating part, an input / output data line, a data register, and a memory judging control part. In Initializing the data registers; Loading read prohibited data into the data register corresponding to a defective column of the main memory area; Loading data of the data register into the memory determination controller; Performing or not reading a cell data of a corresponding column of the memory area according to data loaded in the memory determination controller; Loading data after performing a read operation of the memory determination controller into the data register; A method of reading a semiconductor memory device, comprising loading data of the data register into an input / output data line. The semiconductor memory device of claim 10, wherein the redundant controller applies a register selection address to a register selection unit to load data stored in the data register corresponding to a normal column of the memory area into an input / output data line. How read works. 11. The method of claim 10, wherein the memory determination controller reads the cell data in the selected column of the memory area if the data loaded from the data register is read operation performed data, and if the data loaded from the data register is read data not performed, A read operation method of a semiconductor memory device, characterized in that a column is completely isolated from a read operation by creating a condition that a read operation is not performed. In a semiconductor memory device comprising a memory area composed of main and redundant memory areas, a redundant information area, a redundant control part, a register selecting part, an operation inhibiting data generating part, an input / output data line, a data register, and a memory judging control part. In Initializing the data registers; Loading, by the redundant controller, write prohibited data to the data register corresponding to a defective column of the main memory area; Loading data of an input / output data line into the data register; Loading data of the data register into the memory determination controller; And performing or not performing an operation of writing data to a cell of a corresponding column according to the data loaded in the memory determination controller. 15. The write method of claim 13, wherein the redundant control unit applies a register selection address to a register selection unit to store data of an input / output data line in the data register corresponding to a normal column of the memory area. How it works. 15. The method of claim 13, wherein the memory determination controller stores the data in a selected cell in a column of the memory area if the data loaded from the data register is write operation performing data, and if the data loaded from the data register is data, the selected data of the memory area is selected. A write operation method for a semiconductor memory device, comprising: creating a condition in which a write operation is not performed in a column to completely isolate the column from the write operation.