JP3866345B2 - Semiconductor memory device and method for testing semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data write / read circuit of a semiconductor memory device.
[0002]
In recent years, semiconductor memory devices have been increasingly integrated and increased in capacity. For this reason, there is a tendency that the probability of occurrence of a defect in the miniaturized memory cell tends to increase, and a redundant cell array having a plurality of redundant cells is provided adjacent to the cell array in order to relieve the defective cell. In addition, when a defective cell occurs, it may adversely affect normal memory cells around it, so that an interference test between memory cells is performed. In order to reliably remove defective products through an operation test, it is necessary to perform an interference test with certainty.
[0003]
[Prior art]
A DRAM in which a large number of memory cells are formed in a memory cell array includes a normal cell array in which a large number of normal memory cells are formed and a redundant cell array in which a plurality of redundant cells are formed.
[0004]
When a defective cell is found in the normal cell array by the operation test, an address corresponding to the defective cell is set in the redundant address determination circuit by an operation such as cutting a fuse.
[0005]
Then, when an address for selecting the defective cell is input, the redundant address determination circuit operates to select a redundant cell instead of accessing the defective cell, and write cell information to the selected redundant cell. Alternatively, a read operation is performed.
[0006]
During an operation test, a single cell test is performed to check whether all normal cells in the normal cell array and all redundant cells in the redundant cell array operate normally, and whether there is interference between the normal cell, redundant cell, and surrounding cells is checked. Cell interference test.
[0007]
When performing the cell single test, for example, the same cell information is written in all the normal cells, and then the cell information is read from each normal cell to determine whether or not each normal cell is operating normally.
[0008]
When performing a cell independent test of a redundant cell, a forced redundant signal is input to the redundant address determination circuit so that all redundant cells can be accessed, and a write and read operation is performed on each redundant cell. Whether or not is operating normally is determined.
[0009]
When performing a cell interference test, for example, with the same cell information written in all normal cells, a specific normal cell is selected to invert the cell information, and then the normal cells around the specific normal cell are selected. It is determined whether the cell information is maintained normally. If the cell information of the surrounding normal cells is destroyed, the specific normal cell is determined as a defective cell and its access is switched to the redundant cell.
[0010]
When performing a cell interference test for redundant cells, a forced redundancy signal is input to the redundant address determination circuit so that all redundant cells can be accessed. Access to the cell is switched to a plurality of adjacent redundant cells, and a cell interference test is performed between the redundant cells.
[0011]
[Problems to be solved by the invention]
However, the cell interference test as described above cannot check cell interference between adjacent normal cells and redundant cells. Therefore, even if cell interference occurs between the normal cell and the redundant cell, there is a problem that a defective cell cannot be detected and an operation failure occurs during use.
[0012]
An object of the present invention is to provide a semiconductor memory device capable of performing a cell interference test between a normal cell and a redundant cell easily and without increasing external terminals.
[0013]
[Means for Solving the Problems]
FIG. 1 is a diagram for explaining the principle of claim 1. That is, a normal cell array 4 having a large number of normal cells and a redundant cell array 5 having a plurality of redundant cells for replacing the operation of a defective cell in the normal cell array 4 are provided, and an address inputted from the outside. Based on the signal AD and the control signal / bar OE, the normal cell or the redundant cell is selected, and cell information writing and reading operations are performed. The decoder 2 sets the normal cell array 4 and the redundant cell array 5 as a series of address spaces based on the input of the test mode signal TM and the address signal Ax for address expansion. Based on the test mode signal TM, the address expansion circuit 8 outputs a signal input to the external terminal Tex to which the control signal / bar OE is input to the decoder 2 as the address signal Ax for address expansion.
[0014]
In the address expansion circuit, the test mode signal is input to one input terminal of the NAND circuit and the NOR circuit, and the other input terminal of the NAND circuit and the NOR circuit is connected to the external terminal. The control signal is output, and an address signal for address expansion is output from the NAND circuit.
[0015]
According to a second aspect of the present invention , a test mode signal for switching between a test mode and a normal operation mode is input. Based on the test mode signal, an address signal input from an external terminal is used for address extension of the decoder in the test mode. In the normal operation mode, a signal input from the external terminal is output as a control signal, and in the test mode, redundancy is performed based on the address signal for address expansion. The cell array and a part of the normal cell array form a series of address spaces, and the cell interference test is performed by sequentially selecting the redundant cell array, the redundant cell in the normal cell array, and the normal cell.
[0016]
(Function)
According to another aspect of the present invention, when a test mode signal is input to the address expansion circuit, a signal input to an external terminal to which a control signal is input is input to the decoder as an address signal for address expansion. When the test mode signal and the address signal for address expansion are input to the decoder, the normal cell array and the redundant cell array become a series of address spaces. Within a series of address spaces, cell interference tests of normal cells and redundant cells are reliably performed.
[0017]
When the test mode signal becomes L level, the signal input to the external terminal is output as a control signal from the NOR circuit, and when the test mode signal becomes H level, the signal input to the external terminal is address-extended from the NAND circuit. Is output as an address signal.
[0018]
According to a second aspect of the present invention , a test mode signal for switching between a test mode and a normal operation mode is input. Based on the test mode signal, an address signal input from an external terminal is used for address extension of the decoder in the test mode. In the normal operation mode, a signal input from the external terminal is output as a control signal, and in the test mode, redundancy is performed based on the address signal for address expansion. The cell array and a part of the normal cell array form a series of address spaces, and the cell interference test is performed by sequentially selecting the redundant cell array, the redundant cell in the normal cell array, and the normal cell.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 shows an embodiment of a DRAM embodying the present invention. An address signal AD including a column address signal and a row address signal input from the outside is input to the decoder 2 and the redundant address determination circuit 3 via the address buffer 1. The decoder 2 includes a main decoder 2a and a redundant decoder 2b.
[0020]
The main decoder 2a outputs a selection signal for selecting a normal cell in the normal cell array 4 based on the input address signal AD, and the redundant address determination circuit 3 corresponds to a defective cell in the normal cell array 4. When a redundant address to be set is set and the input address signal AD matches the redundant address, a redundant signal is output to the redundant decoder 2b. The redundant decoder 2b outputs a selection signal for selecting a redundant cell in the redundant cell array 5 based on the input redundant signal.
[0021]
The cell information read from the normal cell array 4 is output as output data Dout through the input / output circuit 6, and the write data Din input from the outside is selected through the input / output circuit 6. Alternatively, it is written in a redundant cell.
[0022]
The test mode entry signal TE input from the outside is input to the test mode detection circuit 7. The test mode detection circuit 7 generates an H level test mode signal TM on the basis of the test mode entry signal TE to generate an address. Output to the extension circuit 8 and the decoder 2. When the H-level test mode signal TM is input to the decoder 2, the main decoder 2a and the redundant decoder 2b operate as a series of decoders.
[0023]
The address expansion circuit 8 is supplied with an output control signal / OE or an upper bit address signal Ax of the address signal AD from an external terminal Tex. When the test mode signal TM is not input during normal operation, the address expansion circuit 8 outputs the output control signal / OE input from the external terminal Tex to the input / output circuit 6 and the test mode signal TM is input. If it is, the address signal Ax input from the external terminal Tex is output to the decoder 2.
[0024]
The specific configuration of the address expansion circuit 8 will be described with reference to FIG. 3. The test mode signal TM is input to the NAND circuit 9 and the NOR circuit 10, and the output control signal OE or the address signal Ax is used as a buffer circuit. The signal is input to the NAND circuit 9 and the NOR circuit 10 through the operating inverter circuit 11a.
[0025]
The output signal of the NOR circuit 10 is output as an output control signal / bar OE via inverter circuits 11d and 11e, and the output signal of the NAND circuit 9 is output as an address signal Ax via inverter circuits 11b and 11c. The
[0026]
In the address expansion circuit 8 configured as described above, an L-level test mode signal TM is input during normal operation other than in the test mode. Then, the output signal of the NAND circuit 9 is fixed at the H level, and the address signal Ax is fixed at the H level.
[0027]
Further, since the NOR circuit 10 inverts and outputs the output signal of the inverter circuit 11a, an output control signal / bar OE having the same phase as the output control signal input from the outside during normal operation is output from the inverter circuit 11e.
[0028]
When the test mode signal TM at H level is input in the test mode, the output signal of the NOR circuit 10 becomes L level, and the output control signal / bar OE output from the inverter circuit 11e is fixed at L level.
[0029]
Further, the signal Ax having the same phase as the address signal Ax input from the external terminal Tex in the test mode is output from the inverter circuit 11c.
Next, the operation of the DRAM configured as described above will be described.
[0030]
At the time of the operation test, the test mode signal TM becomes H level based on the test mode entry signal TE. When the test mode signal TM becomes H level, the address signal Ax input to the external terminal Tex at the time of the test operation is input to the decoder 2 via the address expansion circuit 8, and the decoder 2 includes a main decoder 2a and a redundant decoder 2b. The address signal Ax is the most significant bit, and a word line selection signal or a column selection signal is output to the normal cell array 4 and the redundant cell array 5 based on the address signals AD and Ax which are one bit higher than the address signal AD. .
[0031]
By such an operation, the normal cell array 4 and the redundant cell array 5 become the same address space, and a specific normal cell or redundant cell is selected based on the address signals AD and Ax.
[0032]
Then, a cell single test and a cell interference test of the normal cell and the redundant cell are performed. At this time, the normal cell array 4 and the redundant cell array 5 have the same address space based on the address signals AD and Ax. Therefore, the cell interference test between the normal cell and the redundant cell located at the boundary between the normal cell array 4 and the redundant cell array 5 is performed by sequentially selecting the memory cells in the normal cell array 4 and the redundant cell array 5 and performing the cell interference test. Is surely done.
[0033]
During normal operation, test mode signal TM is at L level, and main decoder 2a and redundant decoder 2b operate independently. Further, the output control signal and the bar OE inputted to the external terminal Tex are inputted to the input / output circuit 6 via the address expansion circuit 8.
[0034]
In this state, when a specific normal cell in the normal cell array 4 is selected based on the address signal AD input from the outside, a write operation or a read operation is performed on the cell.
[0035]
In addition, when the address of the defective cell in the normal cell array 4 is set in advance as a redundant address in the redundant address determination circuit 3 and the input address signal AD matches the redundant address, the redundant address determination circuit 3 outputs a decoder. 2 outputs a redundant signal. The redundant decoder 2b selects a redundant cell in the redundant cell array 5, and a write operation and a read operation are performed on the selected redundant cell.
[0036]
In the DRAM configured as described above, the following operational effects can be obtained.
(A) At the time of the operation test, the main decoder 2a and the redundant decoder 2b operate as a series of decoders by the H-level test mode signal TM and the address signal Ax input to the external terminal Tex. Is a series of address spaces. When the address signal Ax is input for the column address signal and the row address signal, as shown in FIG. 4, even if a redundant cell array is provided on each of the column side and the row side as shown in FIG. The cell array 5 can be the same address space as the normal cell array 4.
[0037]
Therefore, the cell interference test between the normal cell and the redundant cell located at the boundary between the normal cell array 4 and the redundant cell array 5 can be reliably performed by sequentially selecting the normal cell and the redundant cell and performing the cell interference test. it can.
(B) In order to make the normal cell array 4 and the redundant cell array 5 into a series of address spaces, the address signal Ax input from the outside is input using the external terminal Tex for inputting the output control signal / bar OE. Therefore, it is not necessary to provide a new external terminal to increase the address signal by 1 bit. Therefore, an increase in the number of external terminals can be prevented beforehand.
[0038]
In the above embodiment, the normal cell array 4 and the redundant cell array 5 are made a series of address spaces by increasing the address signal by 1 bit. However, the main decoder and the redundant decoder operate as a series of decoders by the test mode signal. Then, by shifting the input address signal by one bit, the row side redundant cell array 5a and a part of the normal cell array 4 are made one address space as shown in FIG. As shown in (b), the column-side redundant cell array 5b and a part of the normal cell array 4 can be used as one address space.
[0039]
【The invention's effect】
As described in detail above, the present invention provides a semiconductor memory device and a method for testing a semiconductor memory device that can easily perform a cell interference test between a normal cell and a redundant cell without increasing the number of external terminals. Can do.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a block diagram showing an embodiment.
FIG. 3 is a circuit diagram showing an address expansion circuit.
FIG. 4 is an explanatory diagram showing an address space.
FIG. 5 is an explanatory diagram showing another address space setting.
[Explanation of symbols]
2 Decoder 4 Normal cell array 5 Redundant cell array 8 Address expansion circuit AD, Ax Address signal bar OE Control signal TM Test mode signal Tex External terminal

Claims (2)

A normal cell array having a large number of normal cells and a redundant cell array having a plurality of redundant cells for replacing the operation of defective cells in the normal cell array, and based on an address signal and a control signal input from the outside A semiconductor memory device that performs a cell information write operation and read operation by selecting the normal cell or redundant cell,
A decoder that uses the normal cell array and the redundant cell array as a series of address spaces based on input of a test mode signal and an address signal for address expansion;
An address expansion circuit that outputs a signal input to an external terminal to which the control signal is input, based on the test mode signal, to the decoder as an address signal for address expansion ;
In the address expansion circuit, the test mode signal is input to one input terminal of a NAND circuit and a NOR circuit, and the other input terminal of the NAND circuit and the NOR circuit is connected to the external terminal. A semiconductor memory device that outputs a control signal and outputs an address signal for address expansion from the NAND circuit . A normal cell array having a large number of normal cells, a redundant cell array having a plurality of redundant cells for replacing the operation of a defective cell in the normal cell array, and a decoder for selecting the normal cell array and the redundant cell array A test method for a semiconductor memory device,
  Input test mode signal to switch between test mode and normal operation mode,
  Based on the test mode signal, an address signal input from an external terminal is output as an address signal for address extension of the decoder in the test mode, and input from the external terminal in the normal operation mode. Output as a control signal,
  In the test mode, based on the address signal for address expansion, the normal cell array and the redundant cell array are set as a series of address spaces, and the cells in the normal cell array and the redundant cells in the redundant cell array are sequentially selected. Cell interference test
A test method for a semiconductor memory device.

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