CN114203244A

CN114203244A - Memory test circuit

Info

Publication number: CN114203244A
Application number: CN202010908118.XA
Authority: CN
Inventors: 林佑道; 姚泽华; 陈懿范
Original assignee: Elite Semiconductor Memory Technology Inc
Current assignee: Elite Semiconductor Memory Technology Inc
Priority date: 2020-09-02
Filing date: 2020-09-02
Publication date: 2022-03-18

Abstract

The invention provides a memory test circuit, comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first electronic fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second electronic fuse group for generating a damage indication signal according to the output of the second latch circuit after receiving the error indication signal; and a comparison circuit for enabling the second latch circuit according to the relationship between the first address and the second input address and the state of the first latch circuit or the first electronic fuse group.

Description

Memory test circuit

Technical Field

The present invention relates to a memory test circuit, and more particularly, to a memory test circuit capable of automatically testing error types.

Background

The memory Test can be generally divided into a pre-package Test mode (CP), which is also called die Test, and a Final Test mode (FT), which is performed after the memory package is completed. A memory usually has a plurality of redundant word lines (redundant word lines), and when a word line of the memory is found to have an error, the word line with the error is replaced by the redundant word line. However, in the final test mode, the memory can only store a very small number of word line error addresses, that is, only a very small number of redundant word lines can be used, and when the number of word lines with errors is greater than the number of word line error addresses that can be stored, the memory is determined to be unrepairable.

However, when the memory has errors, it is possible because the number of word lines with errors is greater than the number of word line error addresses that can be stored, but it is also possible for other reasons. However, the conventional memory testing method takes a lot of labor and time to confirm the type of error when the memory has errors.

Disclosure of Invention

Therefore, an object of the present invention is to provide a memory test circuit capable of automatically providing error type information.

A memory test circuit, comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first electronic fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second electronic fuse group for generating a damage indication signal according to the output of the second latch circuit after receiving the error indication signal; and a comparison circuit for enabling the second latch circuit according to the relationship between the first address and the second input address and the state of the first latch circuit or the first electronic fuse group.

According to the aforementioned embodiments, the memory test circuit provided by the present invention can provide reference information of error types, so that the problem of the prior art that a lot of labor and time are required to identify the error type can be improved.

Drawings

FIG. 1 is a block diagram of a memory test circuit according to an embodiment of the invention.

FIGS. 2 and 3 are schematic diagrams illustrating the operation of the memory test circuit shown in FIG. 1 under different states.

FIG. 4 shows failure analysis conditions of a plurality of memory elements.

[ notation ] to show

10. 10', 10_1, 10_2 … 10_ m memory element

12 memory test circuit

14 decoder

16 memory array

122 comparison circuit

C1 memory cell

LA _1 and LA _2 latch circuit

EG _1, EG _2 electronic fuse group

WL _1-WL _ r word lines

RWL _1 redundant word line

XA receiving end

Detailed Description

The present invention will be described in terms of various embodiments, and it is also noted that elements of the various embodiments may be implemented in hardware (e.g., a device or circuit) or in firmware (e.g., at least one program written in a microprocessor). Furthermore, the terms "first," "second," and the like in the following description are used only to define different elements, parameters, data, signals, or steps. And are not intended to be limiting.

FIG. 1 is a block diagram of a memory test circuit according to an embodiment of the invention. The detailed operation will be described in detail below. In addition, the memory test circuit described in the following embodiments is used in the last test mode, but the memory test circuit provided by the present invention can also be used in different modes. In addition, the memory test circuit provided by the invention can be used on other types of semiconductor devices.

The memory device 10 includes a memory test circuit 12, a decoder 14, and a memory array 16. The memory array 16 includes a plurality of memory cells (memory cells) C1. The memory cells C1 are arranged in a matrix and electrically coupled to corresponding word lines and bit lines.

In the present embodiment, the memory array 16 is configured with at least one redundancy word line RWL _ 1. When the memory device 10 enters the final test mode and a normal word line is found to be defective, the defective word line is replaced with a redundant word line in the normal mode. For example, when one of the word lines WL _1 to WL _ r is found to be a defective word line, the decoder 14 selects the redundant word line RWL1 to replace the defective word line WL _1 when the memory device 10 is accessed in the normal mode. Because of the limited area of the memory device 10, the number of redundant word lines configured in the memory array 16 is limited. If the number of defective word lines exceeds the number of redundant word lines, the memory device 10 is considered to be unrepairable.

Referring to fig. 1, the memory test circuit 12 includes latch circuits LA _1 and LA _2, an electronic fuse group EG _1, an electronic fuse group EG _2, and a comparison circuit 122. The electronic fuse group EG _1 and the electronic fuse group EG _2 each include at least one electronic fuse (E-fuse). The latch circuit LA _1 is composed of a plurality of latches (not shown) for receiving a first input address ADD1 and an error indication signal EAIO via a receiving terminal XA (e.g., an address pin) to generate a first address AD1 and a latch circuit status signal AAIO [0], wherein the error indication signal EAIO indicates whether the first input address ADD1 is an error address (i.e., whether the address corresponds to a damaged word line). The electronic fuses (E-fuses) (not shown) in the first electronic fuse group EG _1 are used to receive the first address AD1 and the latch circuit status signal AAIO [0] to generate the output address ADDR and the fuse indicator signal EN in the burn-in (burn) mode. When the memory device 10 is accessed in the normal mode, the memory array 16 replaces the defective word line with a redundant word line based on the output address ADDR.

In one embodiment, the error indication signal EAIO is generated by inputting a test pattern (test pattern) from the input terminal XA. Then, after a corresponding word line is started, a data reading operation is performed, and then the data is transmitted to the receiving terminal XA for output, in this process, a circuit (not shown) is used to compare whether the output data is indeed the written data, and the error indication signal EAIO is the comparison result.

The latch circuit LA _2 is composed of a latch (not shown) for receiving the error indication signal EAIO to generate a latch circuit status signal AAIO [1 ]. The electrical fuse group EG _2 is used to receive the latch circuit status signal AAIO [1] to generate the damage indication signal OV. The comparison circuit 122 is used for comparing the first address AD1 with a second input address received via the receiving terminal XA, thereby generating a comparison signal cmpen to activate the latch circuit LA _ 2. The damage indication signal OV is used to indicate whether the number of damaged word lines found in the final test mode exceeds the configured number of redundant word lines.

Referring to FIG. 1, the decoder 14 can be a row decoder or a column decoder, i.e., the redundancy word line RWL1 can be a row redundancy word line or a column redundancy word line. The operation of the memory device 10 according to embodiments of the present invention will now be described in more detail. For simplicity, the memory device 10' of FIGS. 2 and 3 is configured with only one redundant word line RWL1, which is illustrated as an example.

The final test mode includes two stages, a buffer/compare stage and a burn-in stage. In the register/compare stage, the latch circuit LA _1 receives the input address ADD1 inputted serially and the error indication signal EAIO via the receiving terminal XA, wherein the error indication signal EAIO indicates whether the input address ADD1 is an error address. In the burning stage, the electronic fuse group EG _1 blows the corresponding electronic fuse according to the address AD1 and the latch circuit state signal AAIO [0 ].

In the final test mode, the latch circuit LA _1 and the electronic fuse group EG _1 have three conditions. In the first situation, the latch circuit LA _1 and the electronic fuse group EG _1 have not yet received signals. At this time, as shown in FIG. 2, if the latch circuit LA _1 receives a new input address ADD1[3:12] and the error indication signal EAIO indicates that the address ADD1[3:12] is an error address, the latch circuit LA _1 stores the address ADD1[3:12] and the error indication signal EAIO and correspondingly generates a first address AD1[3:12] and a latch circuit status signal AAIO [0], wherein the latch circuit status signal AAIO [0] indicates the use state (used) of the latch circuit LA _1 and the latch circuit status signal AAIO [0] is sent to the comparison circuit 122 to enable the comparison operation.

In the present embodiment, the bank EG _1 comprises 11 electronic fuses (not shown), which generate output addresses ADDR [3:12] and fuse state signals EN in the burn-in stage after receiving the first addresses AD1[3:12] and the latch circuit state signals AAIO [0], wherein the fuse state signals EN indicate that the 11 electronic fuses of the bank EG _1 are used. When the memory device 10 is accessed in the normal mode, if INA is the same as ADDR [3:12], the decode circuit 14 selects to turn on redundant word line RWL1 instead of the normal word line.

In the second condition, the latch circuit LA _1 has stored the input address ADD1[3:12] and the error indication signal EAIO and generates the first address AD1[3:12] and the latch circuit state signal AAIO [0 ]. At this time, as shown in FIG. 3, if the latch circuit LA _1 receives a new input address ADD2[3:12], the comparison circuit 122 is enabled by the latch circuit status signal AAIO [0], so that it can start to compare the first address AD1[3:12] with the new input address ADD2[3:12 ]. If the new input address ADD2[3:12] is the same as the first address AD1[3:12], the comparison circuit 122 does not generate the comparison signal cmpen, and the latch circuit LA _2 is not activated. If the new input addresses ADD2[3:12] and AD1[3:12] are different, the comparison circuit 122 generates the comparison signal cmpen, so that the latch circuit LA _2 is enabled. At this time, if the error indication signal EAIO received by the latch circuit LA _2 indicates that the input address ADD2[3:12] is an error address, the latch circuit LA _2 generates a latch circuit status signal AAIO [1], wherein the latch circuit status signal AAIO [1] indicates the use status (used) of the latch circuit LA _ 2.

In the burn-in phase, the electronic fuse group EG _1 receives the first address AD1[3:12] and the latch circuit state signal AAIO [0], and then generates the output address ADDR [3:12] and the fuse state signal EN. The electronic fuse EG _2 generates a damage indication signal OV after receiving the latch circuit status signal AAIO [1], wherein the damage indication signal OV indicates that two normal word lines of the memory array 16 are damaged. Since only one redundant word line RWL _1 is allocated to the memory device 10 ', when a tester reads the damage indication signal OV through the XIO terminal, it is clear that the number of damaged word lines in the memory device 10' exceeds the allocated redundant word lines, and thus no further failure analysis is required.

In the third situation, 11 electronic fuses of the electronic fuse set EG _1 are used, so the fuse state signal EN has changed logic level. As shown in FIG. 3, when the fuse state signal EN changes logic level, the comparison circuit 122 is forced to generate the comparison signal cmpen, so that the latch circuit LA _2 is enabled. At this time, if the error indication signal EAIO received by the latch circuit LA _2 indicates that the new input address ADD2[3:12] is an error address, the latch circuit LA _2 generates a latch circuit status signal AAIO [1 ]. In the burn-in phase, the electronic fuse EG _2 generates a damage indication signal OV after receiving the latch circuit status signal AAIO [1], wherein the damage indication signal OV indicates that the number of damaged word lines in the memory element 10' exceeds the configured number of redundant word lines.

Accordingly, when the damage indication signal OV has a first logic level (e.g., 0) and the memory device 10 ' shows an error status during the final test of the memory device 10 ', the error of the memory device 10 ' is not caused by the number of damaged word lines exceeding the number of configured redundant word lines (i.e., exceeding a predetermined number of redundant word lines), i.e., there may be available redundant word lines, and the memory device is further analyzed to determine whether there is any other error. For example, it is determined whether the faulty address is not completely written into the electronic fuse group, or the quality of the redundant word line is not good, or the test pattern is faulty. On the contrary, when the damage indication signal OV has the second logic level (e.g. 1) and the memory device 10 shows an error state, it indicates that the number of damaged word lines exceeds the number of configured redundant word lines, i.e. the redundant word lines are not available but the normal word lines are still damaged, so that the memory device 10' can be directly determined as being unrepairable.

As described above, the electronic fuse group EG _1 is not limited to storing only one set of error addresses. In one embodiment, the e-fuse group EG _1 may store multiple sets of error addresses. In such an embodiment, multiple comparison circuits may be required to compare whether the new input address and the multiple sets of stored error addresses are the same. Finally, the tester reads the damage indication signal OV through the XIO terminal to determine whether the number of damaged word lines in the memory device 10' exceeds the number of redundant word lines allocated, and then performs further failure analysis.

According to the foregoing description, the memory test circuit of the present application can be briefly described as follows: a memory circuit comprises a plurality of latch circuits and a plurality of electronic fuse groups, wherein at least one of the latch circuits (such as a first latch circuit LA _1) and at least one of the electronic fuse groups (such as a first electronic fuse group EG _1) determines whether to store a first input address according to whether the first input address is an error address, and at least one of the other latch circuits (such as a second latch circuit LA _2) and at least one of the electronic fuse groups (such as a second electronic fuse group EG _2) generate a damage indication signal according to the states of the latch circuits and the electronic fuse groups storing the first input address and the relation between the first input address and the second input address, wherein the damage indication signal is used for indicating whether the number of damaged word lines exceeds a preset redundant word line number.

Fig. 4 shows the failure analysis conditions of a plurality of memory elements (after the memory IC package is completed) 10_1, 10_2, …, 10_ m. Firstly, a tester reads and writes data to the unit cells in 10_1, 10_2, … and 10_ m, and when the output data is equal to the input data, the memory element displays passing; when the output data is not equal to the input data, the memory element indicates a fail (or error state). At this time, the tester reads the damage indication signal OV from the XIO terminal lead of each memory device, so that it can be clearly known that the number of damaged word lines of the memory devices is less than the number of configured redundant word lines. The tester will perform further failure analysis on those elements because they have failed a number of word lines less than the number of redundant word lines configured, but still show an error condition for the memory element.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims

1. A memory test circuit, comprising:

the first locking circuit is used for receiving a first input address and an error indication signal to generate a first address, wherein the error indication signal is used for indicating whether the first input address is an error address or not;

a first electronic fuse group for receiving the first address to generate an output address;

a second latch circuit for receiving the error indication signal;

a second electronic fuse group for generating a damage indication signal according to an output of the second latch circuit after receiving the error indication signal, the damage indication signal indicating whether the number of the word lines with damage exceeds a predetermined number of the redundant word lines; and

the comparison circuit is used for comparing the first address with a second input address and generating a comparison signal according to the relationship between the first address and the second input address and the state of the first latch circuit or the first electronic fuse group so as to start the second latch circuit.

2. The memory test circuit of claim 1, used in a memory device comprising a memory array that replaces a defective word line with a redundant word line based on the output address when the memory device is accessed in a normal mode.

3. The memory test circuit of claim 1, wherein the first latch circuit further generates a first latch circuit status signal according to the first input address and the error indication signal, the first latch circuit status signal representing an active status of the first latch circuit and being used to enable the comparison circuit.

4. The memory test circuit of claim 1, wherein the second latch circuit further outputs a second latch circuit status signal according to the error indication signal, the second latch circuit status signal represents a use status of the second latch circuit and the second plurality of electronic fuses generates the damage indication signal according to the second latch circuit status signal.

5. The memory test circuit of claim 1, wherein the second latch circuit is forced to be activated when at least one of the electronic fuses in the first electronic fuse group is used to record an error address.

6. The memory test circuit of claim 5,

the first electronic fuse group further generates a fuse indicating signal, the fuse indicating signal is used for indicating the using state of the first electronic fuse group, and the comparing circuit receives the fuse indicating signal;

when at least one electronic fuse in the first electronic fuse group is used for recording an error address, the fuse indicating signal enables the comparison circuit to forcibly start the second latch circuit.

7. The memory test circuit of claim 5, wherein the second latch circuit generates a second latch circuit status signal if the error indication signal received by the second latch circuit indicates that the second input address is an erroneous address after the second latch circuit is forced to be activated, the second latch circuit status signal represents a use status of the second latch circuit, and the second electronic fuse group generates the fail indication signal according to the second latch circuit status signal.

8. The memory test circuit of claim 1, wherein the first latch circuit stores the first input address and the error indication signal to generate the first address if the first latch circuit receives the first input address and the first plurality of electronic fuses have no signal input and the error indication signal indicates that the first input address is an error address.

9. The memory test circuit of claim 1,

wherein the comparator compares the second input address with the first address only when the first latch circuit has stored the first input address and the error indication signal and generated the first address;

if the second input address is different from the first address, the comparison circuit starts the second latch circuit, and if the second input address is the same as the first address, the comparison circuit does not start the second latch circuit.

10. A memory test circuit, comprising:

a plurality of latch circuits and a plurality of electronic fuse groups:

at least one of the latch circuits and at least one of the electronic fuse groups determine whether to store the first input address according to whether the first input address is an error address;

at least one of the latch circuits and at least one of the electronic fuse groups generate a fail indication signal indicating whether the number of word lines with fail exceeds a predetermined number of redundant word lines, based on the states of the latch circuit and the electronic fuse group storing the first input address and the relationship between the first input address and the second input address.