TWI724937B - Memory test circuit - Google Patents

Abstract

A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating a fault indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relationship between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

Description

Memory test circuit

The present invention relates to a memory test circuit, and particularly relates to a memory test circuit that can automatically test for error types.

Memory testing can usually be divided into pre-package test mode (chip probe, CP) and final test mode (Final Test, FT). The pre-package test can also be called bare die test, and the final test mode is completed in the memory package. Test afterwards. The memory usually has multiple redundant word lines. When an error is found in the word line of the memory, the redundant word line is used to replace the wrong word line. However, in the final test mode, the memory can only store a very small number of word line error addresses, that is, only a very small number of redundant word lines can be used. When the number of error lines is greater than the number of word lines that can be stored If the number of character lines is incorrect, the memory will be judged as irreparable.

However, when the memory has errors, it may be because the number of word lines with errors is greater than the number of word line error addresses that can be stored, but it may also be due to other reasons. In the current memory test method, when the memory has an error, it takes a lot of manpower and time to confirm the type of error.

Therefore, an object of the present invention is to provide a memory test circuit that can automatically provide error type information.

A memory test circuit includes: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first electronic fuse group for receiving the first address A one-bit address to generate an output address; a second blocking circuit to receive the error indication signal; a second electronic fuse group to generate an output address based on the output of the second blocking circuit receiving the error indication signal Damage indication signal; and a comparison circuit for activating the second latching circuit according to the relationship between the first address and the second input address and the state of the first latching circuit or the first electronic fuse group.

According to the foregoing embodiment, the memory test circuit provided by the present invention can provide reference information of the type of error, so it can improve the problem of the type of error that requires a lot of manpower and time in the prior art.

In the following, several embodiments will be used to describe the content of the present invention. Please also note that the components in each embodiment can be implemented through hardware (such as a device or circuit) or firmware (such as writing at least one program in a microprocessor). To implement. In addition, the “first”, “second” and similar descriptions in the following description are only used to define different elements, parameters, data, signals or steps. It is not used to limit the order.

FIG. 1 shows a block diagram of a memory test circuit according to an embodiment of the invention. The detailed operation will be detailed below. Moreover, the memory test circuit described in the following embodiments is used in the last test mode, but the memory test circuit provided by the present invention can also be used in different modes. In addition, the memory test circuit provided by the present invention can also be used on other types of semiconductor devices.

The memory device 10 includes a memory test circuit 12, a decoder 14 and a memory array 16. The memory array 16 includes a plurality of memory cells C1. The memory cells C1 are arranged in a matrix and are electrically coupled to corresponding word lines and bit lines.

In this embodiment, the memory array 16 is configured with at least one redundant word line RWL_1. When the memory device 10 enters the final test mode, when it is found that the normal character line is damaged, it will replace the damaged character line with a redundant character line in the normal mode. For example, when the word line WL_1 among the word lines WL_1 to WL_r is found to be a damaged word line, when the memory device 10 is accessed in the normal mode, the decoder 14 will select The redundant word line RWL1 replaces the damaged word line WL_1. Due to the limited area of the memory device 10, the number of redundant word lines configured in the memory array 16 is limited. If the number of damaged word lines exceeds the number of redundant word lines, the memory device 10 will be regarded as irreparable.

Referring to FIG. 1, the memory test circuit 12 includes latching circuits LA_1, LA_2, an electronic fuse group EG_1, an electronic fuse group EG_2, and a comparison circuit 122. The electronic fuse group EG_1 and the electronic fuse group EG_2 each include at least one electronic fuse (E-fuse). The latching circuit LA_1 is composed of a plurality of latches (not shown), which is used to receive a first input address ADD1 and an error indication signal EAIO via the receiving terminal XA (for example, address pin) to Generate the first address AD1 and the lock circuit status signal AAIO[0], where the error indication signal EAIO is used to indicate whether the first input address ADD1 is an error address (that is, whether the address corresponds to a damaged word Yuan line). The electronic fuse (E-fuse) (not shown) in the first electronic fuse group EG_1 is used to receive the first address AD1 and the latch circuit state signal AAIO[0] to be in the burn mode Generate output address ADDR and fuse indicator signal EN. When the memory device 10 is accessed in the normal mode, the memory array 16 uses redundant word lines to replace the damaged word lines based on the output address ADDR.

In one embodiment, the error indication signal EAIO is generated by sending a test pattern from the input terminal XA. Then, after starting a corresponding character line, read the data, and then send the data to the receiving terminal XA for output. In this process, a circuit (not shown) is used to compare whether the output data is actually written The error indication signal EAIO is the result of the comparison.

The latching circuit LA_2 is composed of a latch (not shown), which is used to receive the error indication signal EAIO to generate the latching circuit state signal AAIO[1]. The electronic fuse group EG_2 is used to receive the lock circuit state signal AAIO[1] to generate a damage indication signal OV. The comparison circuit 122 is used to compare the first address AD1 with a second input address received via the receiving terminal XA, thereby generating a comparison signal cmpen to activate the latch circuit LA_2. The damage indication signal OV is used to indicate whether the number of damaged word lines found in the final test mode exceeds the configured number of redundant word lines.

Referring to Figure 1, the decoder 14 can be a row decoder or a column decoder, that is, the redundant word line RWL1 can be a row redundant word line or a column redundant word line. Hereinafter, a more detailed example will be used to illustrate the operation of the memory device 10 according to the embodiment of the present invention. For the sake of brevity, only one redundant word line RWL1 is configured in the memory device 10' in Figs. 2 and 3, which is described as an example.

The final test mode consists of two stages: the temporary storage/comparison stage and the burn-in stage. In the temporary storage/comparison phase, the latch circuit LA_1 receives the serial input input address ADD1 and the error indication signal EAIO through the receiving terminal XA, wherein the error indication signal EAIO is used to indicate whether the input address ADD1 is an error Address. In the burn-in phase, the electronic fuse group EG_1 will blow the corresponding electronic fuse according to the address AD1 and the blocking circuit state signal AAIO[0].

In the final test mode, the latching circuit LA_1 and the electronic fuse group EG_1 will have three conditions. In the first situation, the latch circuit LA_1 and the electronic fuse group EG_1 have not yet received signals. At this time, as shown in Figure 2, if the latching circuit LA_1 receives a new input address ADD1[3:12], and the error indication signal EAIO indicates that the address ADD1[3:12] is an error address, Then the lock circuit LA_1 stores the address ADD1[3:12] and the error indication signal EAIO, and correspondingly generates the first address AD1[3:12] and the lock circuit state signal AAIO[0], wherein the lock circuit The status signal AAIO[0] indicates the use status (used) of the latching circuit LA_1, and the latching circuit status signal AAIO[0] will be sent to the comparison circuit 122 to enable the comparison operation.

In this embodiment, the electronic fuse group EG_1 includes 11 electronic fuses (not shown). After receiving the first address AD1[3:12] and the blocking circuit state signal AAIO[0], the electronic fuses The fuse generates an output address ADDR[3:12] and a fuse status signal EN during the burn-in phase, where the fuse status signal EN indicates that the 11 electronic fuses of the electronic fuse group EG_1 have been used. When the memory device 10 is accessed in the normal mode, if the input address INA is the same as the address ADDR[3:12], the decoding circuit 14 will select to turn on the redundant word line RWL1 instead of the original Normal character line.

In the second situation, the latching circuit LA_1 has stored the input address ADD1[3:12] and the error indication signal EAIO, and generated the first address AD1[3:12] and the latching circuit state signal AAIO[0] . At this time, as shown in Figure 3, if the latching circuit LA_1 receives a new input address ADD2[3:12], the comparison circuit 122 has been enabled by the latching circuit state signal AAIO[0], So you can start to compare the first address AD1[3:12] with the new input address ADD2[3:12]. If the new input address ADD2[3:12] and the first address AD1[3:12] are the same, the comparison circuit 122 will not generate the comparison signal cmpen, so the latch circuit LA_2 will not be activated. If the new input address ADD2[3:12] and the address AD1[3:12] are different, the comparison circuit 122 generates a comparison signal cmpen, so the latch circuit LA_2 is activated. At this time, if the error indication signal EAIO received by the latching circuit LA_2 indicates that the input address ADD2[3:12] is an error address, the latching circuit LA_2 generates the latching circuit state signal AAIO[1], where the The lock circuit state signal AAIO[1] indicates the use state (used) of the lock circuit LA_2.

In the burn-in phase, after the electronic fuse group EG_1 receives the first address AD1[3:12] and the blocking circuit state signal AAIO[0], it generates the output address ADDR[3:12] and the fuse state signal EN. The electronic fuse EG_2 receives the lock circuit state signal AAIO[1] and generates a damage indication signal OV, where the damage indication signal OV indicates that two normal character lines of the memory array 16 are damaged. Because the memory device 10' only has one redundant word line RWL_1, when the tester reads the damage indication signal OV through the XIO terminal, he can clearly know that the number of damaged word lines in the memory device 10' exceeds The number of redundant character lines is configured, so no further fault analysis is required.

In the third situation, the 11 electronic fuses of the electronic fuse group EG_1 have been used, so the fuse status signal EN has changed the logic level. As shown in FIG. 3, when the fuse state signal EN changes the logic level, the comparison circuit 122 is forced to generate the comparison signal cmpen, so the latch circuit LA_2 is activated. At this time, if the error indication signal EAIO received by the latch circuit LA_2 indicates that the new input address ADD2[3:12] is an error address, the latch circuit LA_2 generates the latch circuit state signal AAIO[1]. In the burn-in phase, the electronic fuse EG_2 receives the latch circuit state signal AAIO[1] and generates a damage indication signal OV, where the damage indication signal OV indicates that the number of damaged word lines in the memory element 10' exceeds The number of redundant character lines configured.

Accordingly, when the final test test is performed on the memory device 10', if the damage indication signal OV has a first logic level (for example, 0) and the memory device 10' displays an error state, it represents the memory device 10' The error is not because the number of damaged word lines exceeds the number of redundant word lines configured (that is, more than a predetermined number of redundant word lines), that is, there may be redundant word lines that can be used, so you must Further analysis of the memory components to confirm whether there are other errors. For example, confirm whether the error address is not completely written into the electronic fuse group, or the quality of the redundant character line is not good, or the test pattern has an error. Conversely, when the damage indication signal OV has a second logic level (for example, 1) and the memory device 10 displays an error state, it means that the number of damaged word lines exceeds the number of redundant word lines configured, and That is, there is no useable redundant character line but the normal character line is still damaged. Therefore, it can be directly determined that the memory element 10' cannot be repaired.

As mentioned above, the electronic fuse group EG_1 is not limited to only store a set of error addresses. In one embodiment, the electronic fuse group EG_1 can store multiple sets of error addresses. In such an embodiment, multiple comparison circuits are needed to compare whether the new input address is the same as multiple sets of stored error addresses. Finally, the tester reads the damage indication signal OV through the XIO terminal to know whether the number of damaged word lines in the memory device 10' exceeds the number of redundant word lines configured, and then performs further failures analysis.

According to the foregoing description, the memory test circuit of this case can be briefly described as: a memory circuit including a plurality of latching circuits and a plurality of electronic fuse groups, at least one of the latching circuits (for example, the first latching circuit LA_1), and At least one of the electronic fuse groups (for example, the first electronic fuse group EG_1) determines whether to store the first input address according to whether the first input address is an error address, and the other at least one in the blocking circuit (for example, the first The second latching circuit LA_2) and at least one of the other electronic fuse groups (for example, the second electronic fuse group EG_2) will be based on the state of the latching circuit and the electronic fuse group storing the first input address, as well as the first input address and the second The relationship between the two input addresses is used to generate a damage indication signal, and the damage indication signal is used to indicate whether the number of damaged word lines exceeds a predetermined number of redundant word lines.

Figure 4 shows the failure analysis status of multiple memory devices (after the memory IC packaging is completed) 10_1, 10_2,...,10_m. The tester first reads and writes data to the unit cell within 10_1, 10_2,...,10_m. When the output data is equal to the input data, the memory device displays pass; when the output data is not equal to the input data, the memory device displays Fail (fail, or error state). At this time, the tester reads the damage indication signal OV from the respective XIO terminals of the memory components, and it can be clearly known that the number of damaged word lines in the memory components is less than the configured redundant words The number of element lines. Because the number of damaged word lines of those components is less than the number of redundant word lines configured, but the memory components still show an error state, the tester will conduct further failure analysis on them. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

10, 10’, 10_1, 10_2...10_m: memory components 12: Memory test circuit 14: Decoder 16: memory array 122: comparison circuit C1: Memory cell LA_1, LA_2: blocking circuit EG_1, EG_2: electronic fuse group WL_1-WL_r: character line RWL_1: Redundant character line XA: receiving end

FIG. 1 shows a block diagram of a memory test circuit according to an embodiment of the invention. Figures 2 and 3 show schematic diagrams of the operation of the memory test circuit shown in Figure 1 in different states. Figure 4 shows the failure analysis status of multiple memory devices.

10: Memory components

12: Memory test circuit

14: Decoder

16: memory array

122: comparison circuit

C1: Memory cell

LA_1, LA_2: blocking circuit

EG_1, EG_2: electronic fuse group

WL_1-WL_r: character line

RWL_1: Redundant character line

XA: receiving end

Claims (10)

A memory test circuit, including: A first blocking circuit for receiving a first input address and an error indication signal to generate a first address, the error indication signal for indicating whether the first input address is an error address; A first electronic fuse group for receiving the first address to generate an output address; A second blocking circuit for receiving the error indication signal; A second electronic fuse group for generating a damage indication signal according to the output of the second latching circuit after receiving the error indication signal, and the damage indication signal is used for indicating whether the number of damaged character lines exceeds a predetermined redundancy The number of character lines; and A comparison circuit for comparing the first address and a second input address, and according to the relationship between the first address and the second input address and the first latching circuit or the first electronic fuse group To generate a comparison signal to activate the second latching circuit. The memory test circuit described in claim 1 is used in a memory device including a memory array. When the memory device is accessed in the normal mode, the memory array will be used based on the output address Redundant character lines are used to replace damaged character lines. The memory test circuit according to claim 1, wherein the first lockout circuit further generates a first lockout circuit state signal according to the first input address and the error indication signal, and the first lockout circuit state signal represents the first lockout circuit state signal. The use state of a blocking circuit is used to enable the comparison circuit. The memory test circuit according to claim 1, wherein the second lockout circuit further outputs a second lockout circuit state signal according to the error indication signal, the second lockout circuit state signal represents the use state of the second lockout circuit, and The second electronic fuse group generates the damage indication signal according to the second latching circuit state signal. The memory test circuit according to claim 1, wherein when at least one electronic fuse in the first electronic fuse group has been used to record an error address, the second latch circuit is forcibly activated. The memory test circuit described in claim 5, The first electronic fuse group further generates a fuse indicator signal, the fuse indicator signal is used to indicate the use state of the first electronic fuse group, and the comparison circuit receives the fuse indicator signal; Wherein, when at least one electronic fuse in the first electronic fuse group has been used to record an error address, the fuse indication signal causes the comparison circuit to forcibly activate the second latching circuit. For the memory test circuit described in claim 5, after the second latching circuit is forcibly activated, if the error indication signal received by the second latching circuit indicates that the second input address is an error address, the The second lockout circuit generates a second lockout circuit state signal, the second lockout circuit state signal represents the use state of the second lockout circuit, and the second electronic fuse group generates the damage based on the second lockout circuit state signal Indicating signal. The memory test circuit according to claim 1, wherein if the first lock circuit receives the first input address, the first lock circuit and the first electronic fuse group have not yet received a signal input and the error indication signal Indicating that the first input address is an error address, the first locking circuit stores the first input address and the error indication signal to generate the first address. The memory test circuit as described in claim 1, Wherein the first lock circuit has stored the first input address and the error indication signal and generated the first address, the comparator compares the second input address with the first address; If the second input address and the first address are not the same, the comparison circuit activates the second latch circuit, if the second input address is the same as the first address, the comparison circuit does not activate the second latch Circuit. A memory test circuit, including: Multiple blocking circuits and multiple electronic fuse groups: At least one of the blocking circuits and at least one of the electronic fuse groups determines whether to store the first input address according to whether a first input address is an error address; At least one of the other at least one of the latching circuits and at least one of the other of the e-fuse groups will depend on the status of the latching circuit and the e-fuse group storing the first input address, as well as the first input address and a first input address. The relationship between the two input addresses is used to generate a damage indication signal, and the damage indication signal is used to indicate whether the number of damaged word lines exceeds a predetermined number of redundant word lines.

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