KR0164397B1 - Multi-bit test circuit of semiconductor memory device having data changing circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Chip test circuit of semiconductor memory device

2. The technical problem to be solved by the invention

The present invention provides a multi-bit test circuit having a data change circuit which can improve test coverage while simultaneously increasing the number of memory chips for parallel testing and can arbitrarily change data in the memory module with respect to integrated input / output pins.

3. Summary of Solution to Invention

The present invention relates to a multi-bit test circuit of a semiconductor memory device having a plurality of data input / output pins or pads for exchanging data inside a chip and data outside the chip. An input / output sense amplifier which senses and amplifies the data to transmit data to the outside of the chip, data input means for buffering and driving the data to transfer and store the data outside the chip into the chip, and the data input / output pin. A lead data change circuit capable of inputting and changing the integrated data only by the integrated data input / output pins by integrating data inputted / outputted when transferring or reading the data, and transferring or writing the data to the data input / output pins. Integrate input and output data when And a write data change circuit capable of inputting and modifying the integrated data with only the integrated data input / output pins.

4. Important uses of the invention

It is suitably used for semiconductor memory devices.

Description

Multi-bit Test Circuit of Semiconductor Memory Device with Data Change Circuit

1 shows a data path of a multi-bit test circuit according to the prior art.

2 shows a data path of a multi-bit test circuit in accordance with the present invention.

3 is an operation timing diagram of FIG.

FIG. 4 is a diagram showing one embodiment of the write data changing circuit of FIG.

FIG. 5 shows an embodiment of the lead data changing circuit of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a multi-bit test circuit capable of screening a bad chip sufficiently by increasing the number of chips simultaneously tested in parallel.

When testing the performance of bus-wide semiconductor memory devices, several probe tips or packages are used to test wafer status on the test board's load board to reduce test costs. Create a socket to test the state and use parallel testing to test multiple chips at the same time. In this case, as the number of chips that can be tested simultaneously in the test equipment increases, the manufacturing cost is reduced. However, the number of chips that can be tested simultaneously cannot be increased infinitely, but the drive pins that generate the clock and address, the hardware of the test equipment, and the data generated and desired. Since the number of IO pins to compare data is limited, the chip to be tested is determined by the number of pins that generate signals and addresses and the number of I / O pins. The number of drive pins of a typical memory tester is 120 to 320, and the number of input / output pins is about 40 to 144. For example, in case of 8 Mega Synchronous Graphic RAM (8M SGRAM), the number of clock pins is 11, the number of address pins is 10, and the input / output pins are IO pins. The limit of the number of chips that can be tested at the same time as 32 is byte-wide is determined by the number of IO pins. Therefore, the hardware of the test equipment is increased to increase the number of chips that can be tested simultaneously. Increasing the number of input and output pins is an expensive formatter and additional logic, which greatly increases the value of the test equipment. Therefore, when fabricating a semiconductor memory chip, a test circuit is embedded in the memory chip. Therefore, the timing of operation outside the chip is a low address strobe. Column Address Strobe before the signal is enabled from logic high to logic low Signal and Write Enable: When the signal is enabled as logic low, it is recognized as Multi-Bit-Test (MBT) mode, and multiple input / output (IO) is integrated to write and read. This is done.

FIG. 1 is a diagram illustrating a data path of a multi-bit test circuit of a memory chip having 32 input / output pins. Referring to FIG. 1, the input / output pins or the input / output pads 0 to 31 and the eight test circuits A which test the integrated input / output pins four by four, each test circuit A includes a read path including a comparator and a light ( Write) has a path. Thus, I / O pins 0 to 3, 4 to 7, 8 to 11, 12 to 15, 16 to 19, 20 to 23, 24 to 27, and 28 to 31 are connected to one test circuit A, respectively. The total number of chips that can be tested at one time by integrating and testing only eight test circuits A can reduce test costs. That is, even if the data is written or read only to one input / output pin from the outside, the same data is used internally in the integrated input / output pin. The number of I / O pins of the memory device continues to increase in the future, and the number of chips that can be tested at the same time can be increased by integrating the number of I / O pins at the rate as the number of I / O pins increases, but the same data is always written between the integrated I / O pins. Or Read. Therefore, when the input / output pins are shorted, the same data may be written or read, and even if a defect occurs in the memory cell, the screen may not be screened. In addition, since the data inside the memory cell cannot be changed arbitrarily for the integrated I / O pins, Pattern Sensitivity Test Coverage enables functional tests to be performed independently on all I / O pins without integrating the I / O pins. Compared to the normal test, the processing speed is slower, and as the degree of integration increases, the micro defects of the massive I / O lines cannot be inspected. Therefore, the current memory chip test method is capable of screening defects sufficiently by using a multi-bit test alone. Screen) There is a problem that can not be. Therefore, there is a problem that the test must be performed in two steps after finally performing a normal test. The problem of the prior art is that the integrated input and output pins are the result of only being able to write and read only the same data at all times.

Accordingly, it is an object of the present invention to provide a multi-bit test circuit that improves test coverage while increasing the number of memory chips performing parallel testing at the same time.

Another object of the present invention is to provide a multi-bit test circuit having a data change circuit that can arbitrarily change data in a memory module for integrated input / output pins.

It is another object of the present invention to provide a multi-bit test circuit for checking for disturbing noise.

It is still another object of the present invention to provide a multi-bit test circuit having sufficient test coverage even by multi-bit testing, and thus eliminating normal testing, thereby reducing test costs by simplifying test steps.

In order to achieve the objects of the present invention, the present invention provides a multi-bit test circuit of a semiconductor memory device including a plurality of data input / output pins or pads for exchanging data inside a chip and data outside the chip. An input / output sense amplifier connected to an input / output line of the chip to sense and amplify the data in order to transmit the data inside the chip to the outside of the chip, and to buffer and drive the data to transfer and store the data outside the chip inside the chip. A data input means for inputting and outputting data, and a lead data changing circuit capable of inputting and modifying the integrated data only by the integrated data input / output pin by integrating data inputted and outputted when the data is transmitted or read from the data input / output pin. Transfer the data to the input / output pins When a letter or characterized by having in the integration of only the data integrated by integrating the input and output data to be the data input and output pins can input and change light data change circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following description focuses on the data path when the multi-bit test mode is enabled except for specific parts not particularly related to the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

2 is a diagram illustrating a data path of a multi-bit test circuit according to the present invention. FIG. 2 illustrates that the 32 data input / output pins shown in FIG. 1 write and read data to eight input / output pins A externally when the multi-bit test mode is enabled, that is, a logic high. Means for arbitrarily changing the data of integrated I / O lines by adding write data change circuits and lead data change circuits in addition to the conventional test method of increasing the number of chips that can be tested simultaneously by writing or reading data to 32 input / output pins. Was provided.

FIG. 3 shows the operation timing of external signals applied to operate the multi-bit test circuit shown in FIG. Low address strobe signal Column address strobe signal before is enabled from logic high to low And light enable signal Is enabled to logic low to additionally connect the address terminals together with the integrated I / O pins, and in the case of four integrated I / O pins, connect to the address pins A0, A1, A2, and A3 (not shown). In other words, the address pin A0 is input / output pins 0, 4, 8, 12, 16, 20, 24, 28, and the address pin A1 is input / output pins 1, 5, 9, 13, 17, 21, 25, 29 and address Data change is controlled by connecting I / O pins 2, 6, 10, 14, 18, 22, 26, 30 to pin A2 and I / O pins 3, 7, 11, 15, 19, 23, 27, 31 to address pin A3. Connected to do so. In addition, by increasing the number of input / output pins to be integrated, all the input / output pins can be integrated. At this time, an address combination or an unused pin can be used for data change control. If the signal of the address pin is logic low, the integrated data is bypassed. If the signal of the address pin is logic high, the integrated data is inverted and entered. When the operation timing as described above is input to the memory device, the multi-bit test mode enable signal MDQEN operates as logic high so that the multi-bit test circuit operates and each address information is transferred to the address latch signal MRAi. For example, address pin A0 is address latch signal MRA0, address pin A1 is address latch signal MRA1, address pin A2 is address latch signal MRA2, and address pin A3 is latched with address latch signal MRA3, and the multi-bit test is performed. The mode enable signal MDQEN remains until reset, and the address information can be changed by reapplying the multi-bit test mode enable operation timing as necessary.

4 is an embodiment of the write data changing circuit of FIG. In the write data path, an additional circuit for the multi-bit test mode is configured between the external input / output pin or the TTL buffer of the pad, the data input buffer, and the driving stage. Referring to FIG. 4, two serially connected PMOS transistors for inputting the data input signal DQi and two serially connected enmo transistors are connected in series to each other. The data input buffer 90 and the output terminal of the data input buffer 90 and the inverter 3 is connected and the inverter 3 is connected to the input of switch 5. The output terminal of the switch 5 is connected in series with the inverters 11, 15, 17. Noah gate 35 having the multi-bit test enable signal MDQEN as one input signal and the column address strobe delay signal? CD as the other input signal is connected to inverters 7 and switches 5 and 9, respectively. An input terminal of the inverter 13 is connected and an output terminal of the inverter 13 is connected to the switch 9. The node 20 is connected to the switches 5 and 9 and the output terminal of the inverter 7. An output terminal of the inverter 33 having the multi-bit test enable signal MDQEN as an input signal is connected to one side of the switch 31, and the other side of the switch 31 is connected to the node 40. The switch 31 is also connected to the node 50 with the data input signal DINM as input. Input terminals of Noah gate 27 and NAND gate 29 have one side connected to node 50 and the other side receiving address latch signal MRAi as input. The output terminal of the NOR gate 27 is connected to the input terminal of the inverter 25 and the output terminals of the NAND gate 29 and the inverter 25 are connected to the input terminal of the NAND gate 23. The output terminal of the NAND gate 23 is connected to the input terminal of the inverter 21 and the output terminal of the inverter 21 is connected to the node 30. In a new configuration according to the present invention, the input and output pins 0, 4, 8, 12, 16, 20, 24, and 28, which are representatively connected to the outside, enter the multi-bit test mode between the integrated data input signal DINM and the data buffer input signal DINi. When the address latch signal MRAi, which latches address information at the timing of write CAS Before RAS (WCBR) operation to enable, is logic low, the data input signal DINM is bypassed as it is, and the address latch signal MRAi is The logic high has a circuit for inverting the data input signal DINM and sending it to the data buffer input signal DINi, and is used to write data to the memory pin.

5 is an embodiment of the lead data changing circuit of FIG. Referring to FIG. 5, the data input signals RDQ0, RDQ1, RDQ2, and RDQ3 are connected to nodes 10, 20, 30, and 40, respectively, and the address latch signals MRA0, MRA1, MRA2, and MRA3 are respectively nodes 50, 60, 70, It is connected to 80 each. The data input signals RDQ0, RDQ1, RDQ2, and RDQ3 are respectively input to one side of the input terminals of NOR gates 3, 7, 11, and 15 and NAND gates 5, 9, 13, and 17, and the address latch signals MRA0, MRA1, MRA2, Each of the MRA3 is input to the other side of the input terminal of Noah gate 3, 7, 11, 15 and NAND gate 5, 9, 13, 17, respectively. The output terminals of Noah gates 3, 7, 11, and 15 are respectively connected to input terminals of inverters 19, 21, 23, and 25, and one side of the input terminals of NAND gates 27, 29, 31, and 33 is connected to the inverters 19, 21, 23 of , 25 output terminals are connected, and the other end is connected to the output terminals of the NAND gates 5, 9, 13 and 17. The output terminals of the NAND gates 27, 29, 31 and 33 are connected to the input terminals of the inverters 35, 37, 39 and 41. The output terminal of the inverter 35 is connected to the first input terminal of each of the NOA gate 43 and the NAND gate 45, the output terminal of the inverter 37 is connected to the second input terminal of each of the NOA gate 43 and the NAND gate 45, and the output terminal of the inverter 39 is The third input terminal of each of the NORGATE 43 and the NAND gate 45 is connected, and the output terminal of the inverter 41 is connected to the fourth input terminal of the NORGATE 43 and the NANDGate 45 respectively. The output terminal of the NOR gate 43 is connected to the input terminal of the inverter 47, and the output terminal of the NAND gate 47 and the output terminal of the inverter 47 are connected to the input terminal of the NAND gate 49. The output terminal of the NAND gate 49 is connected to the input terminal of the inverter 51.

When the data stored in the memory pin of each input / output pin is enabled in the lead data path and the word line is enabled and the bit line is enabled, and the data is loaded on the input / output line, the input / output line sensing is performed. The data then passes through comparator 10, a circuit that compares the integrated data before going to the output buffer. The comparators are present one by one on the integrated input and output pins. Between the input / output sense amplifier and the comparator 10 comparing the integrated data, the address latch signal MRAi latching the address information at the timing of WCBR operation enabling the data of each input / output line and the multi-bit test mode. When the address latch signal MRAi is a logic low, the data of the input / output line is bypassed as it is, and when the MRAi is a logic high, the data of the input / output line is inverted and inputted to the comparator 10. Referring to FIG. 2, FIG. 4, and FIG. 5 in detail, the multi-bit test enable signal MDQEN is not present when there is no input of the WCBR operation timing that enables the multi-bit test mode. The logic chip is kept at a logic low, and the memory chip performs normal normal operation to separate data for each input / output pin to write and read. For example, when the write operation is performed, the integrated data input signal DINM is disconnected and the column is disconnected because the data coming from the external I / O pins to the respective data input buffers as shown in FIG. 4 is the logic bit low in the multi-bit test enable signal MDQEN. Address strobe signal If the delayed signal? CD is a logic low, it is output as the data input buffer and the output signal DINi of the drive stage, and normal write operation is performed. When the WCBR operation timing is input and the multi-bit test enable signal MDQEN remains logic high and the address pin is input and the address latch signal MRAi is input, the multi-bit test enable signal MDQEN receives the normal write data path ( The normal write data path) is cut off and the integrated data input signal DINM is output as the data input buffer and the output signal DINi of the driving stage. At this time, the integrated data input signal DINM is bypassed or inverted by the input of the address latch signal MRAi. If the address pins A0, A1, A2, and A3 containing address information are logic low at the timing of WCBR operation, the address latch signals MRA0, MRA1, MRA2, and MRA3 become logic low so that the integrated data of all input / output pins are bypassed. When only the address of the address pin A0 is logic high and the address pins A1, A2, and A3 are logic low, the signal MRA0 is logic high, and the address latch signals MRA1, MRA2, and MRA3 are logic low. The integrated data input signal DINM is inverted into the data input buffers of 3, 12, 16, 20, 24, and 28, and the integrated data input signal DINM is bypassed as it is to other input / output pins to enter the data input buffer. Is driven and written to memory. As described above, input / output pins 0, 4, 8,... The combination of 28 and 28 can be used to drive data of the desired type into the memory.

The lead data of FIG. 5 before going to the comparator 10 which compares the data after passing the input / output sense amplifier through the normal lead path in order to randomly change the data by the write data changing circuit of FIG. The data RDQ0, RDQ1, RDQ2, and RDQ3 of each input / output pin in the change circuit are integrated by inverting or inverting the data of the input / output pins by the input of the address latch signal MRA0 latched by the address information at the WCBR operation timing. You will enter Comparator 10, which compares the data. If the address pins A0 and A2 containing address information are logic low in the WCBR operation timing and A1 and A3 are logic high, the address latch signals MRA0 and MRA2 become logic low and MRA1 and MRA3 become logic high to Data RDQ0, RDQ2 are bypassed as is, RDQ1, RDQ2 are bypassed as is, RDQ1, RDQ2 are inverted and entered into the comparator. If the data of all I / O pins are the same, the output of the comparator is logical low. If the data of one I / O pin is wrong, the comparator The output of is logic high and is output through the data output buffer. Based on the embodiments as described above, it can be easily predicted by those skilled in the art that the data of the integrated input / output pins can be arbitrarily adjusted differently from the data input signal DINM of the externally connected representative input / output pins. There will be. It is obvious that the multi-bit test circuit according to the present invention shown in FIG. 2 is an optimal embodiment realized based on the technical idea according to the present invention. However, it should be noted that other modifications than the configuration of FIGS. 4 and 5 may be made in the configuration of the lead data changing circuit and the write data changing circuit according to the present invention. In addition, various embodiments may be made in addition to an address signal input method for changing data of an integrated input / output pin.

As described above, a normal test for independently testing each input / output pin of the test coverage while increasing the number of memory chips that are simultaneously tested in parallel by a semiconductor integrated circuit and an integrated data change circuit having a multi-bit test circuit according to the present invention. All defects can be screened at the same level, integrated I / O pins can be inspected for short-circuit, integrated I / O pins can be converted into internal data, and memory products are highly integrated. Due to this, there is an effect that can screen the micro-defect of the grand I / O line. In addition, since the defect can be screened sufficiently by the multi-bit test alone, the normal test method can be completely implemented by replacing the multi-bit test mode, and the number of chips that can be tested at the same time by integrating all the input / output pins (the number of parallel chips) By increasing the maximum, there is an effect that can screen enough defects.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (8)

A multi-bit test circuit of a semiconductor memory device having a plurality of data input / output pins or pads for exchanging data inside a chip and data outside the chip, wherein the data is stored in the chip by being connected to an input / output line inside the chip. An input / output sense amplifier which senses and amplifies the data for transmission to the outside, data input means for buffering and driving the data to transfer and store the data outside the chip inside the chip, and the data to the data input / output pins. Lead data changing circuit which integrates data input / output at the time of transmitting or reading, and inputs and changes the integrated data only by the integrated data input / output pin, and input / output when transferring or writing the data to the data input / output pin. To integrate data Multi-bit test circuit of a semiconductor memory device characterized by comprising a write data change circuit which can input and change the said data integration of only the data input and output pins. The multi-bit test circuit of claim 1, wherein the write data change circuit is capable of randomly changing and writing data integrated outside the chip when data is input. 2. The multi-bit test circuit of claim 1, wherein the write data changing circuit includes a comparator capable of arbitrarily changing and reading the data output during data output. 2. The multi-bit test circuit of claim 1, wherein the multi-bit test circuit further comprises a control circuit for randomly changing the integrated data. 2. The multi-bit test circuit of claim 1, wherein the lead data change circuit changes the integrated data using a predetermined operation timing, extra input / output pins, or an electric fuse. 2. The multi-bit test circuit of claim 1, wherein the write data changing circuit changes the integrated data using a predetermined operation timing, extra input / output pins, or an electric fuse. 5. The multi-bit test circuit of claim 1, wherein the control means continuously changes the integrated data. The multi-bit test circuit of claim 1, wherein the multi-bit test circuit performs parallel testing while continuously changing the integrated data.