KR970008211A - Multi-bit Test Circuit of Semiconductor Memory Device with Data Change Circuit - Google Patents
Multi-bit Test Circuit of Semiconductor Memory Device with Data Change Circuit Download PDFInfo
- Publication number
- KR970008211A KR970008211A KR1019950022055A KR19950022055A KR970008211A KR 970008211 A KR970008211 A KR 970008211A KR 1019950022055 A KR1019950022055 A KR 1019950022055A KR 19950022055 A KR19950022055 A KR 19950022055A KR 970008211 A KR970008211 A KR 970008211A
- Authority
- KR
- South Korea
- Prior art keywords
- data
- input
- chip
- output
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술 분야1. The technical field to which the invention described in the claims belongs
반도체 메모리장치의 칩 테스트 회로.Chip test circuit of semiconductor memory device.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
본 발명은 동시에 병렬 테스트하는 메모리 칩의 수를 증가시키면서 테스트 커버리지를 향상시키고, 통합된 입출력핀들에 대해서 메모리 쎌 내부의 데이타를 임의로 변경할 수 있는 데이타 변경회로를 구비한 멀티 비트 테스트 회로를 제공한다.The present invention provides a multi-bit test circuit having a data change circuit which can improve test coverage while simultaneously increasing the number of memory chips for parallel testing and can arbitrarily change data in the memory module with respect to integrated input / output pins.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 칩 내부의 데이타와 칩 외부의 데이타를 교환하기 위한 복수개의 데이타 입출력 핀 또는 패드를 구비하는 반도체 메모리장치의 멀티 비트 테스트 회로에 있어서, 상기 칩 내부의 입출력 라인에 접속되어 상기 칩 내부의 데이타를 칩외부로 전송하기 위하여 상기 데이타를 센싱하여 증폭하는 입출력 센스앰프와, 상기 칩 외부의 데이타를 칩 내부에 전송하여 저장하기 위하여 상기 데이타를 버퍼링하고 구동시키는 데이타 입력 수단과, 상기 데이타 입출력 핀으로 상기 데이타를 전송하거나 독출할때 입출력되는 데이타를 통합하여 통합된 상기 데이타 입출력 핀만으로 통합된 상기 데이타를 입출력하고 변경할수 있는 리이드 데이타 변경회로와, 상기 데이타 입출력 핀으로 상기 데이타를 전송하거나 쓰기를 할때 입출력되는 데이타를 통합하여 통합된 상기 데이타 입출력 핀만으로 통합된 상기 데이타를 입출력하고 변경할 수 있는 라이트 데이타 변경회로를 포함한다.The present invention relates to a multi-bit test circuit of a semiconductor memory device having a plurality of data input / output pins or pads for exchanging data inside a chip and data outside the chip. An input / output sense amplifier for sensing and amplifying the data to transmit data to the outside of the chip, data input means for buffering and driving the data to transfer and store the data outside the chip into the chip, and the data input / output pins. A lead data change circuit capable of inputting and changing the integrated data only by the integrated data input / output pins by integrating data inputted / outputted when transferring or reading the data; Integrate input and output data when And a data write circuit which changes a data integration of only the integrated input and output wherein said data input and output pins can make changes.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 메모리장치에 적합하게 사용된다.It is suitably used for semiconductor memory devices.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 멀티 비트 테스트 회로의 데이타 경로를 도시한 도면, 제3도는 제2도의 동작 타이밍도, 제4도는 제2도의 라이트 데이타 변경회로의 일실시예를 나타낸 도면.2 is a diagram showing a data path of a multi-bit test circuit according to the present invention, FIG. 3 is an operation timing diagram of FIG. 2, and FIG. 4 is an embodiment of the write data changing circuit of FIG.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950022055A KR0164397B1 (en) | 1995-07-25 | 1995-07-25 | Multi-bit test circuit of semiconductor memory device having data changing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950022055A KR0164397B1 (en) | 1995-07-25 | 1995-07-25 | Multi-bit test circuit of semiconductor memory device having data changing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970008211A true KR970008211A (en) | 1997-02-24 |
KR0164397B1 KR0164397B1 (en) | 1999-02-18 |
Family
ID=19421518
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950022055A KR0164397B1 (en) | 1995-07-25 | 1995-07-25 | Multi-bit test circuit of semiconductor memory device having data changing circuit |
Country Status (1)
Country | Link |
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KR (1) | KR0164397B1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100403480B1 (en) * | 2001-08-23 | 2003-10-30 | 플래시스 주식회사 | Semiconductor Memory Device and Read/ Write Operation of the same |
KR100937995B1 (en) | 2007-12-26 | 2010-01-21 | 주식회사 하이닉스반도체 | Semiconductor memory device and Testing method of the same |
-
1995
- 1995-07-25 KR KR1019950022055A patent/KR0164397B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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KR0164397B1 (en) | 1999-02-18 |
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