JP2005032375A - Semiconductor memory and its testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems that a simultaneous write access to a number of memory cells connected in parallel in a data line direction, i.e. multiplex selection, is inhibited as a memory function, and in a memory array of the above constitution, a write access time is long and test time cannot be shortened. <P>SOLUTION: A semiconductor memory provided with an access sequencer for simultaneously accessing a plurality of memory cells in the direction of data lines 111 to 114 and the direction of word lines 101 to 104 at the time of a write access to the memory array 100 of the above constitution and a test decoder 300 which is a control signal generation circuit improves write access processing efficiency and shortens test access time by using the test decoder 300. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device and a test method therefor, and in particular, a semiconductor memory including a memory array including a plurality of memory cells connected in a data line direction and a plurality of word lines that activate the memory cells. The present invention relates to a device and a test method thereof.

  As a conventional test method for a semiconductor memory device, the memory cells connected in parallel in the word line direction of the memory array are simultaneously activated, and simultaneous writing is performed to shorten the write time to the memory array. Test time can be shortened (see, for example, Patent Document 1).

Further, even for a memory having a bank structure in which a plurality of memory arrays are connected to each data line, the memory arrays connected in parallel are simultaneously accessed for writing, and simultaneous writing is performed to shorten the time for writing to the memory. This makes it possible to shorten the test time (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 5-249196 (pages 15-17, FIGS. 1 and 3) JP-A-6-267298 (page 9, FIG. 1)

  In such a conventional semiconductor memory device testing method, it is possible to shorten the access time by simultaneous write access to memory cells connected in parallel in the word line direction, but in parallel in the data line direction. Simultaneous write access to the connected memory cells is not possible as a memory function. Therefore, for a memory array having a configuration in which a large number of memory cells are connected in the data line direction, the test time cannot be shortened by shortening the write time.

  The present invention has been made to solve the above-mentioned conventional problems, and it is possible to reduce the test time for a memory array having a configuration in which a large number of memory cells are connected in the data line direction, with a simple and small circuit scale. It is an object of the present invention to provide a semiconductor memory device that can be realized by the above and a test method thereof.

  In order to solve the above-described problems, the semiconductor memory device according to the present invention can simultaneously access a plurality of memory cells arranged in the data line and word line directions when performing write access to the memory array. The access time can be reduced.

  Also, a test method for a semiconductor memory device according to the present invention enables simultaneous access to a plurality of memory cells arranged in the direction of a data line and a word line, and tests a semiconductor memory device to reduce test access time. Is performed, a test pattern in which adjacent cells change simultaneously is generated so that the interaction acts strongly on the memory cell to be tested.

  With the above-described features, the semiconductor memory device according to the present invention can improve the write access processing efficiency. The test method for the semiconductor memory device according to the present invention reduces the test cost and the test quality. It is possible to achieve improvement.

  According to a test method of a semiconductor integrated circuit according to a first aspect of the present invention, a memory array in which at least one or more memory cells are arranged in a data line direction and a word line direction, respectively, A test method for testing a semiconductor memory device comprising at least one or more word lines to be activated and at least one or more data lines respectively connected to the plurality of memory cells, By activating at least one word line at the same time, the plurality of memory cells are activated at the same time, and from the at least one data line to the plurality of memory cells. Since it is assumed that the same write data is written at the time, write access to the memory array having a configuration in which a large number of memory cells are connected in the data line direction is performed. In this case, it is possible to increase the processing efficiency of the write access by simultaneously accessing a plurality of memory cells in the data line and word line directions with a simple and small-scale circuit. It is possible to reduce the test cost and improve the test quality.

  According to a test method for a semiconductor memory device according to a second aspect of the present invention, in the test method for a semiconductor memory device according to the first aspect, the number of combinations of word lines activated at the same time is N (N is Since it includes a state in which at least one word line is selected from a combination of (two to the power of N) different word lines of (an integer of 2 or more) word lines, memory in the data line direction is included. In a write access to a memory array in which a large number of cells are connected, a mechanism for simultaneously accessing a plurality of memory cells in the data line and word line directions by a simple and small-scale circuit is provided. It is possible to increase the processing efficiency, thereby reducing the test time, that is, the test cost, and improving the test quality.

  According to a test method for a semiconductor memory device according to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, every other word line in the order of the data line direction among all the N word lines. Are activated at the same time, and a second word line selected state in which only the word lines that are not activated in the first word line selected state are activated at the same time. In a write access to a memory array having a configuration in which a large number of memory cells are connected in the data line direction, a plurality of memory cells are arranged in the data line and word line directions with a simple and small circuit. Accessing at the same time can improve the processing efficiency of write access, and this can reduce test time, that is, test cost and improve test quality. It is possible to become.

  According to a test method for a semiconductor memory device according to a fourth aspect of the present invention, a memory array in which at least one or more memory cells are arranged in the data line direction and the word line direction, respectively, A test method for testing a semiconductor memory device comprising at least one or more word lines to be activated and at least one or more data lines connected to the plurality of memory cells, respectively. Two word lines connected to two adjacent memory cells arranged vertically in the data line direction with respect to a specific memory cell in the memory cell are activated at the same time and connected to the two adjacent memory cells. Since the same write data is written from the same data line to the activated two adjacent memory cells at the same time. Write access to a memory array with a large number of memory cells connected in the data line direction by accessing multiple memory cells in the data line and word line directions simultaneously with a simple and small circuit. As a result, the test time, that is, the test cost can be reduced, and the test quality can be improved.

  According to a test method for a semiconductor memory device according to a fifth aspect of the present invention, in the test method for a semiconductor memory device according to the fourth aspect, the write data is an inverted value of a write value of the specific memory cell. Therefore, in a write access to a memory array having a configuration in which many memory cells are connected in the data line direction, a plurality of memory cells are simultaneously accessed in the data line and word line directions by a simple and small circuit. Thus, it is possible to increase the processing efficiency of the write access, thereby reducing the test time, that is, the test cost, and improving the test quality.

  According to a test method for a semiconductor memory device according to a sixth aspect of the present invention, a memory array in which at least one or more memory cells are arranged in the data line direction and the word line direction, respectively, A test method for testing a semiconductor memory device comprising at least one or more word lines to be activated and at least one or more data lines connected to the plurality of memory cells, respectively. One word line connected to two adjacent memory cells arranged on the left and right in the word line direction with respect to a specific memory cell in the memory cell is activated at the same time, and connected to the two adjacent memory cells. Since the same write data is written at the same time from the two data lines to the activated two adjacent memory cells. Write access to a memory array with a large number of memory cells connected in the data line direction by accessing multiple memory cells in the data line and word line directions simultaneously with a simple and small circuit. As a result, the test time, that is, the test cost can be reduced, and the test quality can be improved.

  According to a test method for a semiconductor memory device according to a seventh aspect of the present invention, in the test method for a semiconductor memory device according to the sixth aspect, the write data is an inverted value of a write value of the specific memory cell. Therefore, as described above, it is possible to increase the processing efficiency of write access to a memory array having a configuration in which a large number of memory cells are connected in the data line direction by a simple and small-scale circuit, and the test time, that is, It is possible to reduce the test cost and improve the test quality.

  According to a test method for a semiconductor memory device according to an eighth aspect of the present invention, a memory array in which at least one or more memory cells are arranged in the data line direction and the word line direction, respectively, A test method for testing a semiconductor memory device comprising at least one or more word lines to be activated and at least one or more data lines connected to the plurality of memory cells, respectively. Two word lines connected to four adjacent memory cells arranged diagonally with respect to a specific memory cell in the memory cell are activated at the same time, and two word lines connected to the four adjacent memory cells are activated. Since the same write data is written at the same time from the data line to the four adjacent memory cells that have been activated, the mem In a write access to a memory array having a large number of connected recells, a plurality of memory cells are simultaneously accessed in the data line and word line directions with a simple and small-scale circuit to increase the write access processing efficiency. In addition, the test time, that is, the test cost can be reduced, and the test quality can be improved.

  According to a semiconductor memory device test method of a ninth aspect of the present invention, in the semiconductor memory device test method according to the eighth aspect, the write data is an inverted value of a write value of the specific memory cell. Therefore, in a write access to a memory array having a configuration in which many memory cells are connected in the data line direction, a plurality of memory cells are simultaneously accessed in the data line and word line directions by a simple and small circuit. Thus, it is possible to increase the processing efficiency of write access, reduce the test time, that is, the test cost, and improve the test quality.

  According to a semiconductor memory device of a tenth aspect of the present invention, a memory array in which at least one or more memory cells are arranged in the data line direction and the word line direction, respectively, and the memory cells are activated A semiconductor memory device comprising at least one or more word lines and at least one or more data lines respectively connected to the plurality of memory cells, the at least one word line being By activating the word line, the plurality of memory cells are activated at the same time, and the same write data is written to the plurality of memory cells from the at least one data line at the same time. In the write access to the memory array having a configuration in which a large number of memory cells are connected in the data line direction, the data line and the By providing a mechanism for simultaneously accessing a plurality of memory cells in the data line direction, the processing efficiency of write access to a memory array having a configuration in which a large number of memory cells are connected in the data line direction is improved by a simple and small-scale circuit. As a result, the test time, that is, the test cost can be reduced and the test quality can be improved.

  According to a semiconductor memory device in accordance with an eleventh aspect of the present invention, in the semiconductor memory device according to the tenth aspect, after all the memory cells are written at the time of write access, the values of all the memory cells are set at the time of read access. Since it is provided with means for reading one by one and comparing the written value to all the memory cells with the expected value stored in advance and performing a PASS / FAIL self-determination of the memory cell test, As with, a simple and small-scale circuit can increase the processing efficiency of write access to a memory array configured with a large number of memory cells connected in the data line direction, and can reduce test time, that is, test cost. As a result, the test quality can be improved.

  According to a twelfth aspect of the present invention, in the semiconductor memory device according to the tenth or eleventh aspect, a CPU is used for the word line control, the data line control, and the write data control. In a write access to a memory array having a configuration in which a large number of memory cells are connected in the data line direction by a simple and small-scale circuit, a plurality of memory cells in the data line and word line directions are used. By controlling the mechanism for simultaneously accessing the data, it is possible to increase the processing efficiency of the write access, to reduce the test time, that is, the test cost, and to improve the test quality.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
The first embodiment corresponds to the first and second aspects of the invention, in which the same write data is simultaneously written in all the memory cells constituting the memory array.
FIG. 1 is a diagram showing a semiconductor memory device according to the first embodiment of the present invention, and shows a configuration of the semiconductor memory device according to the first embodiment and a write access system using the same.

  In FIG. 1, 101-104 are word lines, 111-114 are data lines, 115-118 are inverted data lines for inputting / outputting inverted signals to the data lines 111-114, 121-124, and 131. To 134, 141 to 144, and 151 to 154 are memory cells connected to the word lines 101 to 104 and the data lines 111 to 114, respectively, and 100 is the memory cells 121 to 124, 131 to 134, 141 to 144, 151 to 154, memory arrays 161 to 164 are sense amplifiers connected to the data lines 111 to 114 and the inverted data lines 115 to 118, and 171 to 174 are sense amplifiers 161 to 164 and input / output lines. Switch circuits 181 to 184 for controlling the connection of ON / OF of the switch circuits 171 to 174 A data line selection signal to be controlled, 191 is an input / output line connected to the switch circuits 171 to 174, 192 is an inverted input / output line to which an inverted signal is input / output with respect to the input / output line 191, and 201 to 204 are During normal operation, the normal word lines 211 to 214 connected to the word lines 101 to 104 via the selector circuits 221 to 224 are connected to the word lines 101 to 104 via the selector circuits 221 to 224 during the test operation. Connected test word line, 220 is a mode selection signal indicating normal operation or test operation, 221 to 224 select normal word lines 201 to 204 and test word lines 211 to 214 by mode selection signal 220 The word line selectors 231 to 234 that perform the data line selection signal 1 via the selector circuits 251 to 254 during normal operation. The normal data line selection signals 241 to 244 connected to 1 to 184 are test data line selection signals 251 to 251 connected to the data line selection signals 181 to 184 via the selector circuits 251 to 254 during the test operation. Reference numeral 254 denotes a data line selection signal selector that selects the normal data line selection signals 231 to 234 and the test data line selection signals 241 to 244 by the mode selection signal 220. Reference numeral 300 denotes the test word lines 211 to 214 and the test data lines. This is a test decoder that outputs selection signals 241 to 244.

The operation of the semiconductor memory device according to the first embodiment configured as described above will be described below.
The semiconductor memory device shown in FIG. 1 shows an example of a 4 × 4 memory array constituted by memory cells 121 to 154.
In writing data to the memory array during normal operation, a unique memory cell is accessed for a unique address access. For example, when memory cells 121 to 154 are mapped to addresses 0x0 to 0xf (0x represents a hexadecimal number), normal word line 201 and normal data line selection signal for write access to memory address 0x0 231 is activated. The word line selector 221 activates the word line 101 to select and output the normal word line 201 when the mode selection signal 220 becomes “L” during normal operation. At the same time, the data line selection signal selector 251 selects and outputs the normal data line selection signal 231 and activates the data line selection signal 181. As a result, write data is input from the input / output line 191 and the inverted input / output line 192 to the data line 111 and the inverted data line 115 via the switch circuit 171 and the sense amplifier 161, and the data is written to the memory cell 121. It is.

  On the other hand, the mode selection signal 220 at the time of the test operation becomes “H”, the word line selector 221 selects and outputs the test word line 211, and the word line selectors 222 to 224 also select and output the test word lines 212 to 214. . Similarly, the data line selection signal selectors 251 to 254 select and output the test data line selection signals 241 to 244. The test word lines 211 to 214 and the test data line selection signals 241 to 244 are output from the test decoder 300 and output arbitrary values during the test operation. Therefore, the test decoder 300 can access not only one memory cell for one access such as a normal operation but also a plurality of memory cell accesses for one access.

FIG. 5 is a timing chart showing the write access during the normal operation and the test operation in the semiconductor memory device shown in FIG. 1, and a to s show waveforms of the signals.
In FIG. 5, (a) shows a clock signal, and each subsequent signal is treated as a clock synchronization signal. (B) is a memory address mapped to the memory cells 121 to 154 in normal operation, (c) is an input / output line 191, (d) to (g) are normal word lines 201 to 204, (h) to (k). Are normal data line selection signals 231 to 234, (l) to (o) are test word lines 211 to 214, and (p) to (s) are signal waveforms of test data line selection signals 241 to 244, respectively. 401 indicates a write access start time, 402 indicates a normal write access end time, 403 indicates a test write access end time, 404 indicates a normal write cycle, and 405 indicates a test write cycle.

Hereinafter, the operation of the write access example in the normal operation and the test operation will be described with reference to FIG.
Here, an example in which “H” is written in all the memory cells 121 to 154 is shown. First, in normal operation, access to the memory address 0x0 starts at the write access start time 401. As a result, the normal word line 201 becomes “H” and the word line 101 is activated, and the normal data line selection signal 231 becomes “H” and the data line 111 and the inverted data line 115 are selected. The memory cell 121 is written with “H” via an input / output line 191 and an inverted value “L” via an input / output line 192 from a data generation circuit (not shown) (hereinafter, access data to the memory cell). , Only the values on the data lines 111 to 114 connected to the input / output line 191 are used.) Similarly, in the subsequent access to the memory addresses 0x1 to 0xf, the normal word lines 201 to 204 and the normal data line selection signals 231 to 234 corresponding to the memory addresses are respectively set to “H” (FIGS. 5D to 5K). )), “H” input from the input / output line 191 is written in the memory cells 122 to 154. Writing to all 16 memory cells is completed at the normal write access end time 402, and the total normal write cycle 404 is 16 clock cycles.

  On the other hand, in the test operation, at the write access start time 401, the signals of the test word lines 211 to 214 and the test data line selection signals 241 to 244 are simultaneously output “H” from the test decoder 300 (FIG. 5L). (See (s)). As a result, all the word lines 101 to 104 are activated, all the data lines 111 to 114 are selected, and "H" input from the data generation circuit (not shown) via the input / output line 191 is all the memory cells 121 to Written to 154. Writing to all 16 memory cells is completed at the test write access end time 403, and the total test write cycle 405 is one clock cycle, which enables writing in 1/16 period of normal operation.

  In such a semiconductor integrated circuit test method of the first embodiment, a memory array having a plurality of memory cells arranged in the data line direction and the word line direction, a plurality of word lines, and a plurality of data lines are provided. A plurality of memory cells, wherein at least one word line is activated to activate a plurality of memory cells at the same time, and write data is input from a plurality of data lines at the same time Since the test is performed by writing the same data at the same time, the writing is performed as compared with the conventional semiconductor memory device testing method for the memory array having a configuration in which many memory cells are connected in the data line direction. Access processing efficiency can be greatly improved, and test cost reduction and test quality improvement can be achieved with a simple and small circuit scale. Theft is possible.

  In the first embodiment, the case where the memory array has a 4 × 4 structure is shown. However, the present invention is not limited to this structure. If the same data is written in all the memory cells at once, the m × n structure is used. (M and n are integers of 2 or more). In this case, it is necessary to increase the number of test word lines and test data line selection signals from the test decoder in accordance with the increase in selectors, sense amplifiers, word lines and data lines as the number of memory cells increases.

(Embodiment 2)
The second embodiment corresponds to the invention of claims 3 to 9, and the test data written in the word line direction and the data line direction is different for the memory cells constituting the memory array. When performing a writing test, writing in which data changes simultaneously in the vertical, horizontal, and diagonal directions can be executed with a simple circuit configuration.

  FIG. 2 is a diagram showing a semiconductor memory device according to the second embodiment of the present invention. Compared to the memory array similar to that of the first embodiment, the checker whose data changes simultaneously in the vertical, horizontal, and diagonal directions as described above. An example of a configuration of a test decoder 300 that can implement the writing test method with a simple circuit and an example of a test method using the same are shown. In FIG. 2, the same components as those in FIG.

  In FIG. 2, 301 is an enable signal in a test, 302 is a clock signal, 303 and 308 are inverter elements, 304 and 309 are AND elements, 305 and 310 are feedback signals, 306, 307, and 311 to 313 are flip-flops, 211 and 213 are the test word lines that are the outputs of the flip-flop 306, 212 and 214 are the test word lines that are the outputs of the flip-flop 307, and 241 and 243 are the test data line selection signals that are the outputs of the flip-flop 311; Reference numerals 242 and 244 denote the test data line selection signals to be output from the flip-flop 313.

  6 is a timing chart at the time of write access in the test operation using the semiconductor memory device shown in FIG. 2, and FIG. 7 is a write sequence at the time of this write access and logical value states of the memory cells 121 to 154. FIG.

  6, (a) shows the clock signal 302, (b) is an enable signal, (c) to (f) are test word lines 211 to 214, and (g) to (j) are test data line selection signals 241. ..., 244, (k) show signal waveforms of the input / output line 191, 411 to 418 show write access start times, 421 to 422 show access enable times, and 423 to 424 show access disable times.

In FIG. 7, Steps 1 to 8 show the logical value states of the memory cells 121 to 154 after the write access performed at the write access start times 411 to 418.
The operation of the thus configured semiconductor memory device of the second embodiment and the test method thereof will be described below with reference to FIGS. 2, 6, and 7. FIG.

  In the initial operation, the enable signal 301 outputs “L”, and the AND elements 304 and 309 also output “L”. Therefore, the flip-flops 306 to 306 to which the clock signal 302 is applied for a sufficient time (at least three cycles or more) are applied. In each of 307 and 311 to 313, “L” is set. The flip-flops 306 to 307 and 311 to 313 may be initialized as reset flip-flops. At the access enable time 421, the write signal starts when the enable signal 301 is asserted to “H” (see FIG. 6B). At this time, “H” from the enable signal 301 and a value “H” obtained by inverting the feedback signal 305 of the flip-flop 306 by the inverter element 303 are input to the AND element 304. “H” is output. Similarly, the AND element 309 also receives “H” from the enable signal 301 and a value “H” obtained by inverting the feedback signal 310 of the flip-flop 312 by the inverter element 308. H "is output.

  (Step S1) At the write access start time 411, the output of the flip-flop 306 changes from “L” to “H”, and simultaneously outputs “H” to the input of the flip-flop 307 and the feedback signal 305. “H” is output to 211 and 213 (see FIGS. 6C and 6E). Similarly, the output of the flip-flop 311 changes from “L” to “H” and outputs “H” to the input of the flip-flop 312 and simultaneously outputs “H” to the test data line selection signals 241 and 243 ( (Refer FIG.6 (g) and (i)). Due to these signal changes, the word lines 101 and 103 are activated, and “H” is input to the data lines 111 and 113 from the data generation circuit (not shown) via the input / output line 191 (see FIG. 6 (k)). ), “H” is written in the memory cells 121, 123, 141, and 143 (see 411 in FIG. 7).

  Since the output of the flip-flop 307 remains “L” and the AND element 304 is input with “L” from the feedback signal 305 through the inverter element 303, the output of “L” is output to the input of the flip-flop 306. Become. Since the outputs of the flip-flops 312 to 313 remain “L”, the AND element 309 receives the output “L” of the flip-flop 312 from the feedback signal 310 via the inverter element 308, and therefore, “H” is input. “H” is output to the input of the flip-flop 311.

  (Step S 2) At the write access start time 412, the output of the flip-flop 306 changes from “H” to “L”, and outputs “L” to the input of the flip-flop 307, the feedback signal 305, and the test word lines 211 and 213. To do. At the same time, the output of the flip-flop 307 changes from “L” to “H”, and outputs “H” to the test word lines 212 and 214 (see FIGS. 6D and 6F). Since the output of the flip-flop 311 remains “H” and does not change, “H” is output to the input of the flip-flop 312 and the test data line selection signals 241 and 243 (see FIGS. 6G and 6I). Due to these signal changes, the word lines 102 and 104 are activated, and “L” is input to the data lines 111 and 113 from a data generation circuit (not shown) via the input / output line 191. 144, “L” is written (see 412 in FIG. 7).

  The AND element 304 is in a state of outputting “H” to the input of the flip-flop 306 because “H” is input from the feedback signal 305 through the inverter element 303. Since the output of the flip-flop 313 remains “L” and the output of the flip-flop 312 changes from “L” to “H”, the AND element 309 changes the output “H” of the flip-flop 312 from the feedback signal 310. Since “L” is input via the inverter element 308, “L” is output to the input of the flip-flop 311.

  (Step S3) At the write access start time 413, the output of the flip-flop 306 changes from “L” to “H”, and outputs “H” to the input of the flip-flop 307, the feedback signal 305, and the test word lines 211 and 213. To do. At the same time, the output of the flip-flop 307 changes from “H” to “L” and outputs “L” to the test word lines 212 and 214. The output of the flip-flop 311 changes from “H” to “L”, and outputs “L” to the input of the flip-flop 312 and the test data line selection signals 241 and 243. At the same time, the output of the flip-flop 313 changes from “L” to “H”, and outputs “H” to the data line selection signals 242 and 244 (see FIGS. 6H and 6J). Due to these signal changes, the word lines 101 and 103 are activated, and “L” is input to the data lines 112 and 114 from the data generation circuit (not shown) via the input / output line 191, so that the memory cells 131, 133, and 151 are input. 153, “L” is written (see 413 in FIG. 7).

  Since “L” is input to the AND element 304 from the feedback signal 305 through the inverter element 303, “L” is output to the input of the flip-flop 306. Since the output of the flip-flop 312 remains “H”, the AND element 309 receives the output “H” of the flip-flop 312 from the feedback signal 310 via the inverter element 308, and thus the flip-flop 312 “L” is output to the input of the group 311.

  (Step S4) At the write access start time 414, the output of the flip-flop 306 changes from “H” to “L”, and outputs “L” to the input of the flip-flop 307, the feedback signal 305, and the test word lines 211 and 213. To do. At the same time, the output of the flip-flop 307 changes from “L” to “H” and outputs “H” to the test word lines 212 and 214. Since the output of the flip-flop 311 remains “L” and does not change, “L” is output to the input of the flip-flop 312 and the test data line selection signals 241 and 243. At the same time, the output of the flip-flop 313 remains “H” and does not change, and outputs “H” to the data line selection signals 242 and 244.

Due to these signal changes, the word lines 102 and 104 are activated, and “H” is input to the data lines 112 and 114 from the data generation circuit (not shown) via the input / output line 191, so that the memory cells 132, 134, 152 , “H” is written in 154 (see 414 in FIG. 7).
The write access is completed by deasserting the enable signal 301 to “L” at the access disable time 423.

By executing the above steps S1 to S4, the table writing test, which is half of the checker writing test, is completed (hereinafter expressed as front / back).
That is, by executing these steps S1 to S4, the data is transferred so that the arrangement of H, L, H, L,... Of each memory cell is reversed for each word line as in the checker game board. Written.

  Similarly, when the enable signal 301 is asserted to “H” at the access enable time 422, the checker (back) writing test is started. The checker (back) write test is performed by writing an inverted value of the value written in the memory cells 121 to 154 in the checker (front) write test. Hereinafter, the sequence is shown in steps S5 to S8.

  (Step S5) At the write access start time 415, “L” is written in the memory cells 121, 123, 141, and 143 by inputting “L” from the input / output line 191 in the same sequence as in step S1. (See 415 in FIG. 7).

  (Step S6) At the write access start time 416, "H" is written to the memory cells 122, 124, 142, 144 by inputting "H" from the input / output line 191 in the same sequence as step S2. (See 416 in FIG. 7).

  (Step S7) At the write access start time 417, by inputting “L” from the input / output line 191 in the same sequence as in step S3, “H” is written in the memory cells 131, 133, 151, and 153. (See 417 in FIG. 7).

(Step S8) At the write access start time 418, "H" is written to the memory cells 122, 124, 142, 144 by inputting "H" from the input / output line 191 in the same sequence as in step S4. (See 418 in FIG. 7)
The write access is completed when the enable signal 301 is deasserted to “L” at the access disable time 424.

By executing the above steps S5 to S8, the checker (back) writing test is completed.
That is, by executing these steps S5 to S8, the data is arranged so that the arrangement of L, H, L, H,... Of each memory cell is reversed for each word line, contrary to steps S1 to S4. Is written.

The total number of access cycles in this checker (front / back) writing test is 8 cycles, and writing is possible in a 1/4 period during normal operation (normal operation: 32 cycles = 16 cycles × 2 patterns [Table /back]).
In addition, this checker writing test method performs the following operation as compared with the checker writing test method based on normal operation.

  (Operation 1) The vertically arranged cells change simultaneously with the data line direction of the memory cells. For example, in the transition from step S5 to step S6 in FIG. 7, the memory cells 142 and 144 that are vertically arranged in the data line direction with respect to the memory cell 143 simultaneously change from “L” to “H”.

  (Operation 2) The left and right cells change simultaneously with respect to the word line direction of the memory cells. For example, in the transition from step S6 to step S7 in FIG. 7, the memory cells 133 and 153 arranged in the left and right direction in the word line direction with respect to the memory cell 143 are simultaneously changed from “L” to “H”.

  (Operation 3) The diagonally arranged cells of the memory cells change simultaneously. For example, in the transition from step S7 to step S8 in FIG. 7, the memory cells 132, 152, 134, and 154 that are diagonally arranged with respect to the memory cell 143 are simultaneously changed from “H” to “L”.

  As a result, in the checker test for inspecting failures affected mainly by the interaction between adjacent memory cells, between data lines, and between word lines, by adding the methods 1 to 3 above, multilayer wiring can be realized. It is possible to improve inspection quality for complicated failures.

  In such a test method of the semiconductor integrated circuit according to the second embodiment, a simple checker test for inspecting a failure affected mainly by an interaction between adjacent memory cells, between data lines, and between word lines is simple. By adding the method of operations 1 to 3 using a simple circuit, it is possible to reduce the test time for a memory array having a configuration in which a large number of memory cells are connected in the direction of the data line, in a simple and small circuit scale, and to achieve multilayer wiring. This makes it possible to improve the inspection quality against complex failures that accompanies the process.

  This is because two adjacent memory cells arranged on the left and right in the word line direction and two adjacent memory cells arranged up and down in the data line direction with respect to a specific memory cell in a plurality of memory cells. In addition, two word lines connected to two adjacent memory cells arranged vertically in the data line direction are respectively applied to four adjacent memory cells arranged diagonally. By activating at the same time, inputting write data from one data line connected to the two adjacent memory cells, and writing the same data to the two adjacent memory cells at the same time, , One word line connected to two adjacent memory cells arranged on the left and right in the word line direction is activated, and write data is sent from the two data lines connected to the two adjacent memory cells at the same time. By writing the same data to the two adjacent memory cells at the same time, it is further possible to connect the four adjacent memory cells to the four adjacent memory cells arranged diagonally. The activated two word lines are activated, and the write data is input from the two data lines connected to the four adjacent memory cells at the same time, so that the four adjacent memory cells are activated at the same time. In the checker test for inspecting a failure affected by an interaction such as a shortcut or crosstalk between adjacent memory cells, between data lines, and between word lines mainly by writing the same data to By adding the method 3, it is possible to improve the inspection quality with respect to a complicated failure due to the multilayer wiring.

  In the second embodiment, the memory array has a 4 × 4 structure. However, the present invention is not limited to this structure, and an m × n structure (m and n are even numbers of 2 or more) may be used. In this case, the test word lines and test data line selection signals taken out from the outputs of the flip-flops 306 and 311 are odd-numbered signals such as 211, 213, 215, 217,..., 241, 243, 245, 247,. If the test word line and test data line selection signals taken out from the outputs of the flip-flops 307 and 313 are even numbers such as 212, 214, 216, 218,..., 242, 244, 246, 248,. Good.

(Embodiment 3)
The third embodiment corresponds to the inventions of claims 10 and 11, and the batch writing to all the memory cells and the determination after the writing according to the first embodiment can be realized with a simple circuit configuration. It is what I did.

  FIG. 3 is a diagram showing a semiconductor memory device according to the third embodiment of the present invention, and shows a configuration of the test decoder 300 of the first embodiment and a test method using a newly added test determination mechanism. .

  3, reference numeral 321 denotes a test clock signal, 322 denotes a timing generation circuit that generates timing from the test clock signal 321, 323 denotes an output signal selector that selects an output signal in synchronization with the timing signal from the timing generation circuit 322, 214 is a test word line output from the output signal selector 323, 241 to 244 are test data line selection signals output from the output signal selector 323, 191 is an input / output line to which write data is output from the output signal selector 323, and 192 Is an inverted input / output line that outputs write data from the output signal selector 323, 324 is a storage circuit that stores the expected value of the read data, 325 is an expected value of the storage circuit 324, and read data from the input / output line 191. The determination circuit 326 for comparing the result of the determination circuit 325 A determination flag signal 327, a timing generation circuit 322, an output signal selector 323, a storage circuit 324, a control circuit for controlling the determination circuit 325, a setting signal 328 for setting the control circuit 327, and an input / output line 340 191, an input / output switching circuit for switching the data input / output direction of the inverted input / output line 192, 300 is a test decoder including a timing generation circuit 322, an output signal selector 323, a control circuit 327, and an input / output switching circuit 340, and 350 is a control circuit 327 is a test determination circuit including an input / output switching circuit 340, a storage circuit 324, and a determination circuit 325.

The operation of the semiconductor memory device of the third embodiment configured as described above and the test method thereof will be described below.
During the test operation, the timing generation circuit 322 generates a plurality of signal waveforms (hereinafter referred to as a signal waveform group) having arbitrary timing synchronized with the test clock signal 321 and outputs the signal waveforms to the output signal selector 323. The arbitrary timing is set by the control from the control circuit 327 set by the setting signal 328. The output signal selector 323 selects the required waveform from the signal waveform group as it is under the control of the control circuit 327, or generates a combination of the signal waveforms in the signal waveform group, whereby the test word lines 211 to 214, test Data line selection signals 241 to 244, input / output lines 191, and inverted input / output lines 192 are output.

  (At the time of data writing) The output signal selector 323 outputs test word lines 211 to 214 and test data line selection signals 241 to 244 in accordance with a write sequence to the memory cells 121 to 154, and at the same time inputs / outputs by the input / output switching circuit 340. Write data is output to the line 191 and the inverted input / output line 192 as output lines. At this time, in the storage area allocated to the memory cells 121 to 154 in the storage circuit 324, the same value as the write data is stored as expected value data by the control circuit 327. In the write sequence, a plurality of memory cells are simultaneously accessed from the memory cells 121 to 154 as much as possible to reduce the number of steps in the sequence.

  (When reading data) The output signal selector 323 outputs test word lines 211 to 214 and test data line selection signals 241 to 244 in accordance with the read sequence to the memory cells 121 to 154. In the read sequence, it is necessary to read one memory cell from the memory cells 121 to 154. In accordance with the read sequence, the input / output switching circuit 340 uses the input / output line 191 as an input line to read the read data and input it to the determination circuit 325. Similarly, the expected value data allocated to the memory cells 121 to 154 corresponding to the read sequence is output from the storage circuit 324 to the determination circuit 325. The determination circuit 325 compares the read data with the expected value data under the control of determination start from the control circuit 327 and outputs the result as a determination flag signal 326.

  In the semiconductor integrated circuit test method according to the third embodiment, data write and read accesses are realized on a clock cycle basis by the test clock signal 321 and the PASS (good) by the test determination circuit 350 as a self-determination circuit. / FAIL (failure) is also determined, so that the test time for a memory array having a configuration in which a large number of memory cells are connected in the direction of the data line can be reduced easily and with a small circuit scale. A simple circuit can perform an access test at a higher speed and a reduction in the number of steps in the test sequence without depending on the access performance of a peripheral circuit that accesses the bus.

(Embodiment 4)
The fourth embodiment corresponds to the inventions of claims 10 to 12 and is capable of realizing simultaneous writing with respect to specific writing processing at the time of batch writing and checker writing with a simple configuration. Is.

  FIG. 4 is a diagram showing a semiconductor memory device according to the fourth embodiment of the present invention. In the fourth embodiment, the control mechanism of the input / output line 191 added to the test decoder 300 of the first embodiment and the control mechanism are shown. This shows a write access method using.

  4, reference numeral 331 denotes a CPU that controls the write sequence, 332 denotes a storage device that stores the write sequence as data, 333 denotes an IO control circuit that inputs and outputs signals under the control of the CPU 331, and includes an input / output line 191 and an inverted input / output It is also the control circuit for line 192. Reference numeral 334 denotes a CPU 331, a storage device 332, an IO control circuit 333, and an external interface, respectively. A bus control circuit that controls between them, 335 is an external interface signal that connects the bus control circuit 334 and the outside, and 211 to 214 are Test word lines output from the IO control circuit 333, 241 to 244 are test data line selection signals output from the IO control circuit 333, 191 is an input / output line through which data is input / output from the IO control circuit 333, and 192 is an IO This is an inverted input / output line through which data is input / output from the control circuit 333.

The operation of the semiconductor memory device according to the fourth embodiment configured as described above will be described below.
When there is a process of writing a specific data pattern to the memory cells 121 to 154 by a soft program and a hard sequence, for example, the all “H” pattern of the first embodiment or the checker pattern of the second embodiment The specific data pattern write access sequence is described as a control program that can be processed by the CPU 331. In the specific data pattern write access sequence, a plurality of memory cells are simultaneously accessed from the memory cells 121 to 154 as much as possible in order to reduce the number of write access cycles. The control program is stored in the storage device 332 from the external interface signal 335 via the bus control circuit 334. When the specific write process occurs in the soft program and hard sequence, the CPU 331 is activated from the external interface signal 335 via the bus control circuit 334. The activated CPU 331 reads out the control program from the storage device 332 via the bus control circuit 334 and executes it. According to the control program, the CPU 331 activates and controls the IO control circuit 333 via the bus control circuit 334. The IO control circuit 333 controls write data to the test word lines 211 to 214, test data line selection signals 241 to 244, input / output lines 191, and inverted input / output lines 192 in accordance with the write access sequence under the control of the CPU 331. Output. In the fourth embodiment, a specific write process in a soft program and a hard sequence is performed by performing simultaneous write access to a plurality of memory cells programmed in advance (question what kind of case). Please show a concrete example of what is assumed)), and it is possible to improve the processing efficiency of software programs and hard sequences.

  In the semiconductor integrated circuit test method according to the fourth embodiment as described above, word line control, data line control, and write data control are performed using a CPU, that is, a software program and a hard sequence. Thus, for a specific write process in the soft program and the hard sequence, simultaneous write access to a plurality of preprogrammed memory cells is performed, so that many memory cells are connected in the data line direction. The test time for the memory array having the configuration can be shortened with a simple and small circuit scale, and the processing efficiency of the software program and the hard sequence can be increased with a simple circuit.

  In the fourth embodiment, even if writing other than batch writing or checker writing is performed as long as the efficiency of the writing process with respect to a plurality of memory cells connected in parallel to the data line method is improved, this is executed. You may make it do. This can be easily performed by changing the program.

  Also in the third and fourth embodiments, the memory array may have an m × n structure (m and n are integers of 2 or more). Also in this case, it is necessary to increase the number of test word lines and test data line selection signals from the test decoder in accordance with the increase in selectors, sense amplifiers, word lines and data lines as the number of memory cells increases.

  Furthermore, also in the third embodiment, the control circuit and the timing generation circuit may be replaced with a CPU as in the fourth embodiment and may be performed in a programmable manner.

  As described above, according to the semiconductor memory device and the test method thereof of the present invention, a semiconductor memory device in which a large number of memory cells are connected in the data line direction is tested at a high speed with a simple and small circuit, and is based on the interaction. Suitable for improving the inspection quality of failures.

1 is an overall schematic diagram of a semiconductor memory device according to a first embodiment of the present invention. FIG. 5 is a diagram showing a configuration of a test decoder as a control signal generation circuit in a semiconductor memory device according to a second embodiment of the present invention. FIG. 5 is a schematic diagram showing a control signal generation circuit, a test decoder as a write data control circuit, and a test determination circuit as a data test self-diagnosis circuit in a semiconductor memory device according to a third embodiment of the present invention. FIG. 9 is a schematic diagram showing a test decoder as a control signal generation circuit and a write data control circuit in a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 5 is a diagram showing a timing chart of write access in the semiconductor memory device according to the first embodiment of the present invention. FIG. 10 is a diagram showing a timing chart of write access of the semiconductor memory device in the second embodiment of the present invention. The figure which shows the write-in sequence in the test method of the semiconductor memory device in Embodiment 2 of this invention.

Explanation of symbols

101 to 104 Word lines 111 to 114 Data lines 121 to 154 Memory cells 161 to 164 Sense amplifiers 171 to 174 Switch circuits 181 to 184 Data line selection signals 191 Input / output lines 192 Inverted input / output lines 201 to 204 Normal word lines 211 to 214 Test word line 220 Mode selection signal 221 to 224 Word line selector 231 to 234 Normal data line selection signal 241 to 244 Test data line selection signal 251 to 254 Data line selection signal selector 300 Test decoder 301 Enable signal 302 Clock signal 303 Inverter element 304 AND Element 305 Feedback signal 306,307 Flip-flop 308 Inverter element 309 AND element 310 Feedback signal 311-313 Flip-flop 321 Test clock signal 322 Timing generation circuit 323 Output signal selector 324 Memory circuit 325 Judgment circuit 326 Judgment flag signal 327 Control circuit 328 Setting signal 331 CPU
332 Storage device 333 IO control circuit 334 Bus control circuit 335 External interface signal 340 Input / output switching circuit 350 Test determination circuit 401 Write access start time 402 Write access end time 403 Test write access end time 404 Normal write cycle 405 Test write cycle 411- 418 Write access start time 421, 422 Access enable time 423, 424 Access disable time

Claims (12)

A memory array in which at least one or more memory cells are arranged in each of a data line direction and a word line direction, at least one or more word lines for activating the memory cells, and the plurality of memories A test method for testing a semiconductor memory device comprising at least one or more data lines connected to cells,
Activating the plurality of memory cells at the same time by activating the at least one word line at the same time;
Write the same write data to the plurality of memory cells from the at least one data line at the same time.
A test method for a semiconductor memory device. The method of testing a semiconductor memory device according to claim 1.
The combination of the word lines activated at the same time is at least one or more of (N to the power of 2) different word lines among all N (N is an integer of 2 or more) word lines. Including the selected word line,
A test method for a semiconductor memory device. The method of testing a semiconductor memory device according to claim 2.
The combination of word lines activated at the same time is
A first word line selection state in which every other word line in the data line direction among all the N word lines is activated at the same time;
A second word line selection state in which only the word lines that have not been activated in the first word line selection state are activated at the same time.
A test method for a semiconductor memory device. A memory array in which at least one or more memory cells are arranged in each of a data line direction and a word line direction, at least one or more word lines for activating the memory cells, and the plurality of memories A test method for testing a semiconductor memory device comprising at least one or more data lines connected to cells,
Two word lines connected to two adjacent memory cells arranged vertically in the data line direction with respect to a specific memory cell in the plurality of memory cells are activated at the same time,
The same write data is written to the activated two adjacent memory cells from the same data line connected to the two adjacent memory cells at the same time.
A test method for a semiconductor memory device. The method of testing a semiconductor memory device according to claim 4.
The write data is an inverted value of a write value of the specific memory cell.
A test method for a semiconductor memory device. A memory array in which at least one or more memory cells are arranged in each of a data line direction and a word line direction, at least one or more word lines for activating the memory cells, and the plurality of memories A test method for testing a semiconductor memory device comprising at least one or more data lines connected to cells,
Activating one word line connected to two adjacent memory cells arranged on the left and right in the word line direction with respect to a specific memory cell in the plurality of memory cells at the same time;
Write the same write data to the activated two adjacent memory cells at the same time from the two data lines connected to the two adjacent memory cells.
A test method for a semiconductor memory device. The method of testing a semiconductor memory device according to claim 6.
The write data is an inverted value of a write value of the specific memory cell.
A test method for a semiconductor memory device. A memory array in which at least one or more memory cells are arranged in each of a data line direction and a word line direction, at least one or more word lines for activating the memory cells, and the plurality of memories A test method for testing a semiconductor memory device having at least one or more data lines connected to cells,
Activating two word lines connected to four adjacent memory cells diagonally arranged with respect to a specific memory cell in the plurality of memory cells at the same time;
Writing the same write data at the same time from the two data lines connected to the four adjacent memory cells to the activated four adjacent memory cells.
A test method for a semiconductor memory device. The method of testing a semiconductor memory device according to claim 8.
The write data is an inverted value of a write value of the specific memory cell.
A test method for a semiconductor memory device. A memory array in which at least one or more memory cells are arranged in each of the data line direction and the word line direction;
A plurality of word lines for activating the memory cell; and
A plurality of data lines connected to the plurality of memory cells, respectively, and a semiconductor memory device comprising:
Activating the plurality of memory cells at the same time by activating at least one of the word lines;
Write the same write data to the plurality of memory cells from the at least one data line at the same time.
A semiconductor memory device. The semiconductor memory device according to claim 10.
After writing to all the memory cells at the time of write access, the values of all the memory cells are read one by one at the time of read access, and the write value to all the memory cells is compared with the expected value stored in advance. A means for performing PASS / FAIL self-determination of the memory cell test,
A semiconductor memory device. The semiconductor memory device according to claim 10 or 11,
The word line control, the data line control, and the write data control are performed programmably using a CPU.
A semiconductor memory device.

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