JP3583070B2 - RAM test data generation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a RAM test data generation circuit, and more particularly to a RAM test data generation circuit built in a semiconductor integrated circuit together with a RAM.
[0002]
[Prior art]
In recent years, with the development of process technology, for example, semiconductor integrated circuits each having a built-in plurality of RAMs of 16 Kbytes or more and having different capacities as instruction caches or data caches have been increasing. For this reason, in consideration of the operation of the CPU and other circuits incorporated in the semiconductor integrated circuit together with the RAM, the test of the RAM is made difficult in order to test the RAM, and the test pattern design man-hour is increased, and the test pattern becomes longer. , The test time is also longer.
[0003]
As a countermeasure, it has been proposed to incorporate a test circuit for self-testing a RAM in a semiconductor integrated circuit.
[0004]
FIG. 9 is a block diagram showing an example of a test circuit in a semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 4-315899, for example. Referring to FIG. 9, this conventional semiconductor memory device includes a self-test circuit 4, a memory cell array 5, a transfer gate 6, a data register 7, a row decoder 8, and a comparison circuit 9 as blocks that operate during a test. The self-test circuit 4 includes a micro ROM 41, a row address generator 42, a register address generator 43, a pattern generator 44, and a controller 45. In this conventional semiconductor memory device, each block other than the memory cell array 5 and the row decoder 8 is a block of a test circuit added exclusively for testing.
[0005]
The operation of this conventional semiconductor memory device will be briefly described. At the time of a test, first, test pattern data is written to the memory cell array 5 according to a test program stored in the micro ROM 41. At this time, the test pattern data is serially output from the pattern generator 44 to the data register 7 and written serially in accordance with the register address from the register address generator 43. Next, the row address is output from the row address generation section 42 to the row decoder 8, and the data or the inverted data of the data register 7 is selected via the transfer gate 6 by the inversion control and the transfer control of the control section 45. Is written simultaneously to each cell in the row. At this time, when changing the data of the test pattern corresponding to the row address, it is performed by changing the data of the data register 7 based on the outputs of the pattern generator 44 and the register address generator 43.
[0006]
Next, data is read from the memory cell array 5 according to the test program stored in the micro ROM 41. At this time, the data of the test pattern used as the expected read value is serially output from the pattern generator 44 to the data register 7 and written serially in accordance with the register address from the register address generator 43. Is output to Next, the row address is output from the row address generator 42 to the row decoder 8, the data of each cell in the selected row of the memory cell array 5 is simultaneously read, and the inversion control and the transfer control of the controller 45 The read data or the inverted data is output to the comparison circuit 9 via the transfer gate 6, is compared with the data of the test pattern in the data register 4, and the comparison result is output.
[0007]
In this conventional semiconductor memory device, a register address generator 43, a pattern generator 44, a controller 45, a data register 7, and a transfer gate 6 operate according to a test program stored in a micro ROM 41 to generate test pattern data. This eliminates the need for test pattern design man-hours during testing. Further, the cells in the selected row of the memory cell array 5 are simultaneously written and read out at the same time, and are compared with the data of the expected read value, thereby reducing the test time.
[0008]
[Problems to be solved by the invention]
The conventional semiconductor memory device described above is a semiconductor integrated circuit dedicated to storage, and when a block is dedicated to testing, the effect is large. However, in a semiconductor integrated circuit including a plurality of RAMs having different capacities, it is necessary to generate test patterns and data of expected read values based on the matrix configuration of the RAM cell array, and a test circuit is incorporated for each of the plurality of RAMs. As a result, an increase in overhead due to the test circuit cannot be ignored, and there is a problem that the cost of the semiconductor integrated circuit increases.
[0009]
In addition, many CPUs and other circuits built in a semiconductor integrated circuit together with a plurality of RAMs have a function that can replace a block that is additionally provided only for a test. Another challenge is to make testing more efficient. For example, the address generating means and the comparing means at the time of the test can be replaced by a counter means and a calculating means in the CPU and other circuits, respectively. When the semiconductor integrated circuit has a built-in ROM, the test sequence controlling means at the time of the test has It can be replaced by mounting a test program in a part of the ROM.
[0010]
Also, depending on the semiconductor integrated circuit, it is desirable to add only a RAM test data generation circuit for internally generating data of a RAM test pattern at the time of a test and externally perform test control, thereby making the RAM test more efficient and suppressing an increase in cost. There is also a request.
[0011]
Accordingly, it is an object of the present invention to at least reduce the circuit area of a RAM test data generation circuit incorporated as one of the test functions and reduce the cost of a semiconductor integrated circuit.
[0012]
[Means for Solving the Problems]
Therefore, the present invention provides a RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM during a test.
A detection circuit configured to detect an access cycle of the RAM corresponding to the set value when the control data is set during the test and to output a detection signal;
A flip-flop circuit for setting initial value data during a test, inverting the data every time a RAM access cycle is performed during the inactive period of the detection signal, and outputting a bus as each bit output of the test pattern data.
[0013]
The present invention also relates to a RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test. A detection circuit for detecting a cycle and outputting a detection signal;
A shift register circuit that sets initial value data in an alternative bit inversion pattern during a test, shifts and rotates each RAM access cycle during an inactive period of the detection signal, and outputs each bit output as data of the test pattern on a bus. I have.
[0014]
Further, the detection circuit, a control register in which the control data is set during a test,
A down counter that counts down every RAM access cycle during a test, outputs the detection signal with a zero value, and sets the set value in the next RAM access cycle.
[0015]
Further, the detection circuit selects a control register in which the control data is set during a test, and a plurality of lower bits of an address signal corresponding to a set value of the control register during the test, and performs a logical product signal or logical sum of each bit. An address detection circuit for outputting a signal as the detection signal.
[0016]
The present invention also relates to a RAM test data generating circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test. And an address detection circuit for selecting a logical product signal or a logical sum signal of each bit as a detection signal, and
A flip-flop circuit in which initial value data is set during a test and which is inverted every RAM access cycle during an inactive period of the detection signal;
An output circuit that outputs the output of the flip-flop circuit as each bit output of the data of the test pattern and outputs the output as a bus.
[0017]
The present invention also relates to a RAM test data generating circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test. And an address detection circuit for selecting a logical product signal or a logical sum signal of each bit as a detection signal, and
A shift register circuit in which initial value data is set in an alternative bit inversion pattern during a test, and shifts and rotates every RAM access cycle during an inactive period of the detection signal;
An output circuit that outputs each bit output of the shift register circuit as data of the test pattern and outputs the data as a bus.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing Embodiment 1 of a RAM test data generation circuit of the present invention. Referring to FIG. 1, the RAM test data generation circuit 1 of this embodiment includes a detection circuit 11 and a flip-flop circuit 12, and is connected to a plurality of RAMs or comparison means via an address bus or a data bus. It is shown.
[0019]
The detection circuit 11 includes a control register 111 and a down counter 112. During a test, control data is set, a RAM access cycle corresponding to the set value is detected, and a detection signal is output. The control register 111 is set with control data via a data bus at the time of a test, and the down counter 112 counts down at the time of each input of a clock signal corresponding to a RAM access cycle at the time of the test, and flips the detection signal at a zero value. The setting value of the control register 111 is set at the next clock signal input.
[0020]
Also, the flip-flop circuit 12 is set with initial value data via a data bus during a test, and is inverted every time a clock signal is input during an inactive period of a detection signal by the detection circuit 11, and is inverted during an active period of the detection signal. The data is output to the data bus as each bit output of the test pattern data without being inverted. Further, depending on the test sequence control, the output test pattern data is directly output to the comparing means without passing through the data bus, and is used as read expected value data.
[0021]
Next, the operation of the RAM test data generation circuit of the present embodiment will be described with reference to the drawings. FIG. 2 is a flowchart showing a procedure example of a test sequence control for testing one RAM shown in FIG. However, it is assumed that the test sequence control and the RAM address generation are performed in blocks not shown in FIG. FIG. 3 is an explanatory diagram showing a configuration example of a memory cell array of a RAM to be tested. This RAM is provided with a memory cell array in which eight bits of data are input and output, and eight memory cell arrays of eight rows and four columns are arranged in parallel in accordance with the number of bits of the input and output data, and each cell constituting the memory cell array is provided. Shows an address. FIG. 4 is a timing chart showing an operation example of the RAM test data generation circuit of the present embodiment.
[0022]
At the time of the test, first, in step S1 of the test sequence control of FIG. 2, a value “7h” is set as control data in the control register 111 corresponding to the number of rows 8 of the cell array of the RAM to be tested, and the initial value data “0” is set. Is set in the flip-flop circuit 12, and the down counter 112 is reset.
[0023]
In step S2, writing to the RAM is performed. In writing to the RAM, address signals in ascending order are supplied to the RAM from the address bus and clock signals are supplied to the down counter 112 and the flip-flop circuit 12 in accordance with the access cycle of the RAM. Since the down counter 112 has a zero value and the detection signal is “1”, the down counter 112 sets the value “7h” set in the control register 111 at the first clock signal input, and the flip-flop circuit 12 Without being inverted, the down counter 112 counts down and the flip-flop circuit 12 performs inversion every time the next clock signal is input, and the data of the test pattern having the output of the flip-flop circuit 12 as each bit output is the data. Output to the bus and written to RAM. At this time, as shown in FIG. 4, when the down counter 112 counts down every time a clock signal is input and reaches a zero value, the detection signal becomes “1”, and the flip-flop circuit 12 is inverted when the next clock signal is input. Is skipped.
[0024]
FIG. 5 is an explanatory diagram showing an example of a test pattern written in the cell array of the RAM. As shown in FIG. 5, a test pattern of a checker board in which data of adjacent cells are inverted from each other is written in a cell array of a RAM.
[0025]
In step S3, the value “7h” is set again as control data in the control register 111, the initial value data “0” is set in the flip-flop circuit 12, and the down counter 112 is reset.
[0026]
In step S4, the RAM is read. In this RAM reading, an ascending address signal is supplied from the address bus to the RAM in accordance with the access cycle of the RAM, the RAM is read, and the read data is output to the comparing means via the data bus. . At the same time, the test pattern of the checker board shown in FIG. 4 is output from the flip-flop circuit 12 as expected read value data of the RAM, and is compared with the read data by the comparing means to indicate a match / mismatch, as in the case of writing to the RAM. The comparison result is output.
[0027]
In step S5, it is determined whether or not there is a mismatch as a result of the comparison. If there is a mismatch, the test ends with a problem.
[0028]
Next, in step S6, the value “7h” is set as control data in the control register 111, and the initial value data “1” is set in the flip-flop circuit 12, and in step S7, the data is written into the RAM as in step S2. Is performed. At this time, since the set value of the flip-flop circuit 12 is inverted, the test pattern to be written is a back test pattern in which the test pattern of the checker board shown in FIG.
[0029]
In step S8, the value “7h” is set again as control data in the control register 111, and “1” is set in the flip-flop circuit 12, and in step S9, as in step S4, reading from the RAM is performed. The read data is output to the comparison means via the data bus. At the same time, a back test pattern obtained by inverting the test pattern of the checker board shown in FIG. 4 with bits is output from the flip-flop circuit 12 as data of the expected read value of the RAM, as in the writing of the RAM in step S6. The data is compared with the data, and a comparison result indicating match / mismatch is output.
[0030]
Next, in step S10, it is determined whether or not there is a mismatch as a result of the comparison. If there is a mismatch, the test ends with a problem. If there is no mismatch, the test ends with no problem, and the quality of the RAM is determined. .
[0031]
As described above, the RAM test data generation circuit 1 according to the present embodiment is configured by a simple circuit including the detection circuit and the flip-flop circuit in which the control data and the initial value data are set. Based on the matrix configuration, data of the checker board test pattern and its back test pattern can be generated.
[0032]
FIG. 6 is a block diagram showing a second embodiment of the RAM test data generation circuit of the present invention. Referring to FIG. 6, the RAM test data generation circuit 1 of this embodiment includes a detection circuit 11 and a shift register circuit 13, and is connected to a plurality of RAMs or comparison means via an address bus or a data bus. It is shown.
[0033]
The detection circuit 11 is the same as the block in the RAM test data generation circuit 1 of the first embodiment described with reference to FIG. 1, and at the time of a test, control data is set, and a RAM access cycle corresponding to the set value is detected. The detection signal is output.
[0034]
The shift register circuit 13 has an 8-bit configuration similarly to the data bus. At the time of testing, each bit is set or reset based on 1-bit control data from the data bus, and the initial value data is replaced with an alternative bit inversion pattern. In the inactive period of the detection signal of the detection circuit 11, the shift rotation is performed for each input of the clock signal corresponding to the RAM access cycle. Bus output as data. Further, depending on the test sequence control, the output test pattern data is directly output to the comparing means without passing through the data bus, and is used as read expected value data.
[0035]
Next, the operation of the RAM test data generation circuit of the present embodiment will be described with reference to the drawings. As in the first embodiment, the control is performed based on the test sequence control of the RAM and the example of the memory cell array described with reference to FIGS. FIG. 7 is a timing chart showing an operation example of the RAM test data generation circuit of the present embodiment.
[0036]
At the time of the test, first, in step S1 of the test sequence control of FIG. 2, a value “7h” is set as control data in the control register 111 and the down counter 112 corresponding to the number of rows 8 of the cell array of the RAM to be tested. The value data “10000000” is set in the shift register circuit 13, and the down counter 112 is reset.
[0037]
In step S2, writing to the RAM is performed. In writing to the RAM, an ascending address signal is supplied from the address bus to the RAM, and a clock signal is supplied to the down counter 112 and the shift register circuit 13 in accordance with the access cycle of the RAM. Since the down counter 112 has a zero value and the detection signal is “1”, the down counter 112 sets the value “7h” set in the control register 111 at the first clock signal input, and the shift register circuit 13 The down counter 112 counts down every time a clock signal is input without the shift rotation, and the shift register circuit 13 performs a shift rotation. Each bit output of the shift register circuit 13 outputs data as test pattern data. Output to the bus and written to RAM. At this time, when the down counter 112 counts down every time a clock signal is input and reaches a zero value, the detection signal becomes “1”, and the shift rotation of the shift register circuit 13 is skipped at the next clock signal input.
[0038]
FIG. 8 is an explanatory diagram showing an example of a test pattern written in the cell array of the RAM. As shown in FIG. 8, data of a diagonal test pattern in which an alternative bit inversion pattern of each column is diagonally arranged in a bit direction and a column direction of input / output data is written in a cell array of a RAM.
[0039]
In step S3, the value “7h” is set again as control data in the control register 111 and the down counter 112, and the initial value data “10000000” is set in the shift register circuit 13 again.
[0040]
In step S4, the RAM is read. In this RAM reading, an ascending address signal is supplied from the address bus to the RAM in accordance with the access cycle of the RAM, the RAM is read, and the read data is output to the comparing means via the data bus. . At the same time, similarly to the writing in the RAM, the diagonal test pattern shown in FIG. 8 is output from the shift register circuit 13 as the data of the expected reading value of the RAM, and is compared with the read data by the comparing means, and a comparison indicating match / mismatch is performed. The result is output.
[0041]
In step S5, it is determined whether or not there is a mismatch as a result of the comparison. If there is a mismatch, the test ends with a problem.
[0042]
Next, in step S6, the value "7h" is set as control data in the control register 111 and the down counter 112, and the initial value data "011111111" is set in the shift register circuit 13. In step S7, as in step S2. , RAM writing is performed. At this time, since the set value of the shift register circuit 13 is inverted, the test pattern to be written is a back test pattern in which the diagonal test pattern shown in FIG.
[0043]
In step S8, the value “7h” is set again as control data in the control register 111 and the down counter 112, and the initial value data “0111111111” is set in the shift register circuit 13. In step S9, as in step S4, The RAM is read, and the read data is output to the comparing means via the data bus. At the same time, similarly to the writing of the RAM in step S6, the back test pattern obtained by bit-inverting the diagonal test pattern shown in FIG. 8 is output from the shift register circuit 13 as data of the expected read value of the RAM. The data is compared with the data, and a comparison result indicating match / mismatch is output.
[0044]
Next, in step S10, it is determined whether or not there is a mismatch as a result of the comparison. If there is a mismatch, the test ends with a problem. If there is no mismatch, the test ends with no problem, and the quality of the RAM is determined. .
[0045]
As described above, the RAM test data generation circuit 1 of the present embodiment is configured by a simple circuit including the detection circuit in which the control data and the initial value data are set and the shift register circuit. The diagonal test pattern and the data of the back test pattern can be generated based on the matrix configuration, and the alternative bit inversion pattern of each column is formed diagonally with respect to the bit direction and the column direction of the input / output data. Of the row recorder and column decoder can be detected.
[0046]
In the RAM test data generation circuits 1 of the first and second embodiments, the detection circuit 11 has been described as including the down counter 112. However, as a modified example of the detection circuit 11, instead of the down counter 112, a control register It is also possible to provide an address detection circuit that selects a plurality of lower bits of the address signal corresponding to the set value of 111 and outputs a logical product signal or a logical sum signal of each bit as a detection signal.
[0047]
Further, in the RAM test data generation circuit 1 of the first and second embodiments, the detection circuit 11 has been described as including the control register 111. However, when the RAM test data generation circuit can be arranged near a plurality of RAMs to be tested, As a modified example of the detection circuit 11, instead of the control register 111, a selection signal of each RAM is directly input, a plurality of lower-order bits of the address signal are selected corresponding to the selection signal of each RAM, and an AND signal of each bit is selected. Alternatively, an address detection circuit that outputs a logical sum signal as a detection signal can be provided, and the circuit area of the RAM test data generation circuit can be further reduced.
[0048]
【The invention's effect】
As described above, the RAM test data generation circuit according to the present invention is configured by a simple circuit in which control data and initial value data are set, and a checker board is provided for a plurality of RAMs based on a matrix configuration of a RAM cell array. Alternatively, data of a diagonal test pattern and back test pattern data can be generated.
[0049]
For this reason, the circuit area of the RAM test data generation circuit is reduced and the cost of the semiconductor integrated circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a RAM test data generation circuit of the present invention.
FIG. 2 is a flowchart illustrating an example of a procedure of test sequence control for testing a RAM.
FIG. 3 is an explanatory diagram showing a configuration example of a memory cell array of a RAM to be tested.
4 is a timing chart showing an operation example of the RAM test data generation circuit in FIG. 1; FIG. 5 is an explanatory diagram showing an example of a test pattern written in a cell array of the RAM in FIG. 3;
FIG. 6 is a block diagram illustrating a RAM test data generation circuit according to a second embodiment of the present invention.
FIG. 7 is a timing chart showing an operation example of the RAM test data generation circuit of FIG. 6;
FIG. 8 is an explanatory diagram showing an example of a test pattern written in a cell array of the RAM.
FIG. 9 is a block diagram showing an example of a test circuit in a conventional semiconductor memory device.
[Explanation of symbols]
Reference Signs List 1 RAM test data generation circuit 4 Self-test circuit 5 Memory cell array 6 Transfer gate 7 Data register 8 Row decoder 9 Comparison circuit 11 Detection circuit 12 Flip-flop circuit 13 Shift register circuit 41 Micro ROM
42 row address generator 43 register address generator 44 pattern generator 45 controller

Claims (6)

In a RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test, control data is set at a time of the test and an access cycle of the RAM corresponding to the set value is detected. A detection circuit that outputs
A flip-flop circuit, which is provided with an initial value data at the time of a test and inverts every RAM access cycle during an inactive period of the detection signal and outputs a bus as each bit output of the data of the test pattern. In a RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test, control data is set at a time of the test and an access cycle of the RAM corresponding to the set value is detected. A detection circuit that outputs
A RAM having a shift register circuit in which initial value data is set in an alternative bit inversion pattern at the time of a test, and a shift register circuit shift-rotates every RAM access cycle during an inactive period of the detection signal and outputs each bit output as data of the test pattern on a bus; Test data generation circuit. The detection circuit, a control register in which the control data is set during a test,
3. The RAM test data generation circuit according to claim 1, further comprising: a down counter that counts down every RAM access cycle during a test, outputs the detection signal with a zero value, and sets the set value in a next RAM access cycle. The detection circuit selects a control register in which the control data is set at the time of test, and a plurality of lower-order bits of an address signal corresponding to a set value of the control register at the time of test, and outputs a logical product signal or a logical sum signal of each bit. 3. The RAM test data generation circuit according to claim 1, further comprising an address detection circuit that outputs the detection signal. In a RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test, a plurality of lower-order bits of an address signal are selected at a test corresponding to a selection signal of the RAM, and An address detection circuit that outputs a logical product signal or a logical sum signal as a detection signal,
A flip-flop circuit in which initial value data is set during a test and which is inverted every RAM access cycle during an inactive period of the detection signal;
An output circuit that outputs the output of the flip-flop circuit as each bit output of the data of the test pattern and outputs the output as a bus. In a RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test, a plurality of lower-order bits of an address signal are selected at a test corresponding to a selection signal of the RAM, and An address detection circuit for outputting a logical product signal or a logical sum signal as a detection signal, and a shift register for shifting and rotating every RAM access cycle during an inactive period of the detection signal in which initial value data is set in an alternative bit inversion pattern during a test Circuit and
An output circuit for outputting each bit output of the shift register circuit as data of the test pattern and outputting the data as a bus.

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