JP2002184196A - Ram test data generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost of a semiconductor integrated circuit by reducing the circuit area of a RAM test data generating circuit incorporated as one of test functions. SOLUTION: This circuit is provided with: a detecting circuit 11 in which control data are set at the time of test and which detects the access cycle of a RAM corresponding to the set value and outputs the detection signal; a flip-flop circuit 12 in which initial value data are set at the time of test and which is reversed for each RAM access cycle during the non-activation period of a detection signal; and an output circuit 13 for outputting to a bus the output of this flip-flop circuit 12 as each bit output of the data of a test pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a RAM test data generation circuit, and more particularly to a RAM test data generation circuit built in a semiconductor integrated circuit together with a RAM.

[0002]

2. Description of the Related Art In recent years, with the development of process technology, for example, as an instruction cache or a data cache,
Multiple RAs with different capacities, each of 16K bytes or more
Semiconductor integrated circuits incorporating M are increasing. For this reason, in consideration of the operation of the CPU and other circuits built into the semiconductor integrated circuit together with the RAM, the test pattern design becomes difficult because the RAM is tested, and the test pattern design man-hour is increased, and the test pattern becomes longer. , The test time is also longer.

As a countermeasure against this, RA in a semiconductor integrated circuit is
It has been proposed to incorporate a test circuit for self-testing M.

FIG. 9 shows, for example, Japanese Patent Application Laid-Open No. Hei 4-31589.
FIG. 10 is a block diagram showing an example of a test circuit in the semiconductor memory device disclosed in Japanese Patent Application Publication No. 9-09. Referring to FIG.
This conventional semiconductor memory device includes a self-test circuit 4, a memory cell array 5, a transfer gate 6, a data register 7, a row decoder 8,
The comparison circuit 9 is provided, and the self-test circuit 4 further includes a micro ROM 41, a row address generation unit 42, a register address generation unit 43, a pattern generation unit 44, and a control unit 45. In this conventional semiconductor memory device, each block other than the memory cell array 5 and the row decoder 8 is a block of a test circuit added exclusively for testing.

The operation of this conventional semiconductor memory device will be briefly described. At the time of a test, first, test pattern data is written in the memory cell array 5 according to a test program stored in the micro ROM 41. At this time, the data of the test pattern is serially output from the pattern generator 44 to the data register 7, and written serially in accordance with the register address from the register address generator 43. Next, the row address is output from the row address generator 42 to the row decoder 8 and the control unit 45
, The data or inverted data of the data register 7 is simultaneously written to each cell of the selected row via the transfer gate 6. At this time,
When the data of the test pattern is changed corresponding to the row address, it is performed by changing the data of the data register 7 based on the outputs of the pattern generator 44 and the register address generator 43.

Next, data is read from the memory cell array 5 in accordance with the test program stored in the micro ROM 41. At this time, the data of the test pattern used as the read expectation value is
Are serially output to the data register 7, written serially in accordance with the register address from the register address generator 43, and output to the comparison circuit 9. Next, the row address is output from the row address generator 42 to the row decoder 8, the data of each cell in the selected row of the memory cell array 5 is simultaneously read, and the inversion control and the transfer control of the controller 45 The read data or the inverted data is output to the comparison circuit 9 via the transfer gate 6, is compared with the test pattern data of the data register 4, and the comparison result is output.

This conventional semiconductor memory device has a micro R
In accordance with the test program stored in the OM 41, the register address generator 43, the pattern generator 44, and the controller 4
5, the data register 7 and the transfer gate 6 operate to generate test pattern data, and the test pattern design man-hour at the time of testing becomes unnecessary. In addition, the memory cell array 5
, Each cell of the selected row is written at the same time, read at the same time, and compared with the data of the expected read value, thereby reducing the test time.

[0008]

The above-mentioned conventional semiconductor memory device is a semiconductor integrated circuit dedicated to storage, and when a block is added exclusively for testing, the effect is large. However, in a semiconductor integrated circuit including a plurality of RAMs having different capacities, it is necessary to generate test patterns and data of expected read values based on the matrix configuration of the RAM cell array, and a test circuit is incorporated for each of the plurality of RAMs. As a result, an increase in overhead due to the test circuit cannot be ignored and there is a problem that the cost of the semiconductor integrated circuit increases.

In addition, many CPUs and other circuits built in a semiconductor integrated circuit together with a plurality of RAMs have a function that can replace blocks added exclusively for testing. There is also a problem of avoiding and making testing more efficient. For example, the address generating means and the comparing means at the time of testing can be respectively replaced by counter means and calculating means in a CPU or other circuits. When the semiconductor integrated circuit has a built-in ROM, the test sequence controlling means at the time of testing comprises: It can be replaced by mounting a test program in a part of the ROM.

Further, depending on the semiconductor integrated circuit, the efficiency of the RAM test is increased and the cost is increased by adding only a RAM test data generation circuit for internally generating the data of the RAM test pattern at the time of the test and externally controlling the test. There is also a demand to control

Therefore, an object of the present invention is to at least reduce the circuit area of a RAM test data generation circuit built in as one of the test functions and reduce the cost of a semiconductor integrated circuit.

[0012]

SUMMARY OF THE INVENTION Therefore, the present invention provides a semiconductor integrated circuit which is built in a semiconductor integrated circuit together with a RAM.
In a RAM test data generation circuit for generating data of an AM test pattern, a detection circuit for setting control data during a test and detecting an access cycle of the RAM corresponding to the set value and outputting a detection signal; Data is set and R is set during the inactive period of the detection signal.
And a flip-flop circuit that inverts every AM access cycle and outputs a bus as each bit output of the test pattern data.

Further, the present invention provides a semiconductor integrated circuit having a RAM.
A RAM test data generation circuit which is built in and generates test pattern data of the RAM at the time of a test, wherein a control data is set at the time of the test, and a detection circuit which detects an access cycle of the RAM corresponding to the set value and outputs a detection signal And a shift register circuit in which initial value data is set in an alternative bit inversion pattern at the time of a test, and a shift register is rotated in each RAM access cycle during an inactive period of the detection signal and outputs each bit output as data of the test pattern on a bus. Have.

Further, the detection circuit includes a control register in which the control data is set at the time of a test,
A down counter that counts down every M access cycles, outputs the detection signal with a zero value, and sets the set value in the next RAM access cycle.

The detection circuit selects a control register in which the control data is set at the time of a test, and a plurality of lower-order bits of an address signal corresponding to a set value of the control register at the time of the test, and outputs a logical product signal of each bit. Or an address detection circuit that outputs a logical sum signal as the detection signal.

Further, the present invention provides a semiconductor integrated circuit having a RAM.
A RAM test data generating circuit which is built in the RAM and generates the data of the test pattern of the RAM at the time of a test. An address detection circuit for outputting a sum signal as a detection signal; a flip-flop circuit for setting initial value data during a test and inverting every RAM access cycle during an inactive period of the detection signal; An output circuit for outputting each bit of the pattern data as a bus output.

Further, the present invention provides a semiconductor integrated circuit having a RAM.
A RAM test data generating circuit which is built in the RAM and generates the data of the test pattern of the RAM at the time of a test. An address detection circuit for outputting a sum signal as a detection signal, a shift register circuit for initializing data set in an alternative bit inversion pattern during a test, and performing a shift rotation for each RAM access cycle during an inactive period of the detection signal; And an output circuit for outputting each bit output of the register circuit as data of the test pattern and outputting a bus.

[0018]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a RAM test data generation circuit according to the present invention. Referring to FIG. 1, a RAM test data generation circuit 1 according to this embodiment
Comprises a detection circuit 11 and a flip-flop circuit 12,
It is shown that it is connected to a plurality of RAMs or comparison means via an address bus or a data bus.

The detection circuit 11 includes a control register 111 and a down counter 112. At the time of a test, control data is set, a RAM access cycle corresponding to the set value is detected, and a detection signal is output. The control register 111 is set with control data via a data bus at the time of a test, and the down counter 112 counts down each time a clock signal corresponding to a RAM access cycle is input at the time of a test, and flips the detection signal at a zero value. The setting value of the control register 111 is set at the next clock signal input.

In the test, the flip-flop circuit 12 is set with initial value data via a data bus during a test, and inverts each time a clock signal is input during an inactive period of the detection signal by the detection circuit 11, to thereby detect the detection signal. It is output to the data bus as each bit output of the test pattern data without being inverted during the active period. Further, depending on the test sequence control, the output test pattern data is directly output to the comparing means without passing through the data bus, and is used as read expected value data.

Next, the operation of the RAM test data generation circuit of the present embodiment will be described with reference to the drawings. FIG.
FIG. 5 is a flowchart illustrating an example of a procedure of a test sequence control for testing one RAM illustrated in FIG. 1. However,
It is assumed that this test sequence control and RAM address generation are performed in blocks not shown in FIG. FIG. 3 is an explanatory diagram showing a configuration example of a memory cell array of a RAM to be tested. This RAM is provided with a memory cell array in which eight bits of data are input / output and eight memory cell arrays of eight rows × 4 columns are arranged in parallel in accordance with the number of bits of the input / output data, and each cell constituting the memory cell array is provided. Shows the address. FIG.
FIG. 5 is a timing chart showing an operation example of the RAM test data generation circuit of the present embodiment.

At the time of the test, first, in step S1 of the test sequence control shown in FIG. 2, a value "7h" is set in the control register 111 as control data corresponding to the number of rows 8 of the cell array of the RAM to be tested. Data “0” is set in the flip-flop circuit 12, and the down counter 112 is reset.

In step S2, writing to the RAM is performed. In writing to the RAM, address signals in ascending order are supplied from the address bus to the RAM, and clock signals are supplied to the down counter 112 and the flip-flop circuit 12, corresponding to the access cycle of the RAM.
The down counter 112 has a zero value and the detection signal is “1”.
Therefore, at the input of the first clock signal, the down counter 112 sets the value “7” set in the control register 111.
h ″ is set, the flip-flop circuit 12 does not invert, and the down counter 112 counts down, the flip-flop circuit 12 performs inversion and the output of the flip-flop circuit 12 every time a clock signal is input next. The test pattern data to be output as each bit is output to the data bus and written to the RAM, and at this time, as shown in FIG. Becomes "1", and the inversion of the flip-flop circuit 12 is skipped at the next clock signal input.

FIG. 5 is an explanatory diagram showing an example of a test pattern written in the cell array of the RAM. As shown in FIG. 5, a test pattern of a checker board in which data of adjacent cells are inverted from each other is written in a cell array of a RAM.

In step S3, the value "7h" is set again as control data in the control register 111, the initial value data "0" is set in the flip-flop circuit 12, and the down counter 112 is reset.

In step S4, the RAM is read. In this RAM reading, an ascending address signal is supplied from the address bus to the RAM in accordance with the access cycle of the RAM, the RAM is read, and the read data is output to the comparing means via the data bus. . At the same time, the test pattern of the checker board shown in FIG. 4 is output from the flip-flop circuit 12 as the data of the expected read value of the RAM, and is compared with the read data by the comparing means to indicate the match / mismatch, as in the writing of the RAM. The comparison result is output.

In step S5, it is determined whether or not there is a mismatch as a result of the comparison. If there is a mismatch, the test ends with a problem.

Next, at step S6, the control register 11
The value "7h" is set to 1 as control data, the initial value data "1" is set to the flip-flop circuit 12, and writing to the RAM is performed in step S7, as in step S2. At this time, since the set value of the flip-flop circuit 12 is inverted, the test pattern to be written is a back test pattern in which the test pattern of the checker board shown in FIG.

In step S8, the control register 11
The value “7h” is set to 1 as control data, and “1” is set to the flip-flop circuit 12, and step S9
Then, as in step S4, the RAM is read,
The read data is output to the comparing means via the data bus. At the same time, similarly to the writing of the RAM in step S6, the back test pattern obtained by inverting the bit of the test pattern of the checker board shown in FIG. 4 is output from the flip-flop circuit 12 as data of the expected read value of the RAM. The data is compared with the data, and a comparison result indicating match / mismatch is output.

Next, in step S10, it is determined whether or not there is a mismatch as a result of the comparison. If there is a mismatch, the test ends as a problem, and if there is no mismatch, the test ends as a no problem and the quality of the RAM is checked. Is determined.

As described above, the RAM test data generation circuit 1 of the present embodiment is composed of a simple circuit including the detection circuit and the flip-flop circuit in which the control data and the initial value data are set. Based on the matrix configuration of the RAM cell array, the data of the test pattern of the checker board and the test pattern behind it can be generated.

FIG. 6 is a block diagram showing Embodiment 2 of the RAM test data generation circuit of the present invention. Referring to FIG. 6, the RAM test data generation circuit 1 of the present embodiment
Is provided with a detection circuit 11 and a shift register circuit 13 and is connected to a plurality of RAMs or comparison means via an address bus or a data bus.

The detection circuit 11 is the same as the block in the RAM test data generation circuit 1 according to the first embodiment described with reference to FIG. 1. Control data is set at the time of testing, and a RAM access cycle corresponding to the set value is set. Detect
The detection signal is output.

The shift register circuit 13 has an 8-bit configuration like the data bus. At the time of testing, each bit is set or reset based on 1-bit control data from the data bus, and the initial value data is selected. Each bit output is set in a bit inversion pattern and shifts and rotates every time a clock signal corresponding to a RAM access cycle is input during the inactive period of the detection signal of the detection circuit 11, and does not rotate during the active period of the detection signal. Bus output as test pattern data. Further, depending on the test sequence control, the output test pattern data is directly output to the comparing means without passing through the data bus, and is used as read expected value data.

Next, the operation of the RAM test data generation circuit of this embodiment will be described with reference to the drawings. As in the first embodiment, the control is performed based on the test sequence control of the RAM and the example of the memory cell array described with reference to FIGS. FIG. 7 is a timing chart showing an operation example of the RAM test data generation circuit of the present embodiment.

At the time of the test, first, in step S1 of the test sequence control of FIG. 2, a value "7h" is set in the control register 111 and the down counter 112 as control data corresponding to the number of rows 8 of the cell array of the RAM to be tested. Then, the initial value data “10000000” is set in the shift register circuit 13 and the down counter 112 is reset.

In step S2, writing to the RAM is performed. In writing to the RAM, address signals in ascending order are supplied to the RAM from the address bus and clock signals are supplied to the down counter 112 and the shift register circuit 13 in accordance with the access cycle of the RAM. Since the down counter 112 has a zero value and the detection signal is “1”, the down counter 112 sets the value “7h” set in the control register 111 upon the first clock signal input.
Is set, the shift register circuit 13 does not perform the shift rotation, and the down counter 112 counts down every time a clock signal is input next, the shift register circuit 13 performs the shift rotation, and the shift register circuit 13 performs the shift rotation.
Are output to the data bus as test pattern data and written to the RAM. At this time,
When the down counter 112 counts down every time the clock signal is input and reaches a zero value, the detection signal becomes “1”, and the shift register circuit 1 is input when the next clock signal is input.
The shift rotation of 3 is skipped.

FIG. 8 is an explanatory diagram showing an example of a test pattern written in the cell array of the RAM. As shown in FIG. 8, diagonal test pattern data in which an alternative bit inversion pattern of each column is diagonally arranged in the bit direction and the column direction of input / output data is written in the cell array of the RAM.

In step S3, the value "7h" is set again in the control register 111 and the down counter 112 as control data, and the initial value data "10000000" is set.
Is set in the shift register circuit 13.

In step S4, the RAM is read. In this RAM reading, an ascending address signal is supplied from the address bus to the RAM in accordance with the access cycle of the RAM, the RAM is read, and the read data is output to the comparing means via the data bus. . At the same time, similarly to the writing in the RAM, the diagonal test pattern shown in FIG. 8 is output from the shift register circuit 13 as the data of the expected value to be read from the RAM, and is compared with the read data by the comparing means, and the comparison indicating match / mismatch is performed. The result is output.

In step S5, it is determined whether or not there is a mismatch as a result of the comparison. If there is a mismatch, the test ends with a problem.

Next, at step S6, the control register 11
1 and the value “7” as control data in the down counter 112.
h ”is set, and the initial value data“ 0111111111 ”is set.
Is set in the shift register circuit 13 and the step S7
Then, as in step S2, writing to the RAM is performed. At this time, since the set value of the shift register circuit 13 is inverted, the test pattern to be written is a back test pattern in which the diagonal test pattern shown in FIG.

At step S8, the control register 11
The value “7h” is set as control data in the “1” and the down counter 112, and the initial value data “01111111” is set.
1 "is set in the shift register circuit 13 and the step S
In step 9, as in step S4, the RAM is read, and the read data is output to the comparing means via the data bus. At the same time, a back test pattern obtained by bit inversion of the diagonal test pattern shown in FIG. 8 is output from the shift register circuit 13 as data of an expected value to be read from the RAM, as in the writing of the RAM in step S6, and read by the comparing means. The data is compared with the data, and a comparison result indicating match / mismatch is output.

Next, in step S10, it is determined whether or not there is a mismatch as a result of the comparison. If there is a mismatch, the test is terminated as having a problem. If there is no mismatch, the test is terminated as having no problem. Is determined.

As described above, the RAM test data generation circuit 1 of the present embodiment is composed of a simple circuit including the detection circuit in which the control data and the initial value data are set and the shift register circuit. Based on the matrix configuration of the RAM cell array, a diagonal test pattern and data of a back test pattern can be generated, and an alternative bit inversion pattern of each column is formed diagonally with respect to a bit direction and a column direction of input / output data. , A row recorder and a column decoder in the RAM can be detected as being redundantly selected.

In the RAM test data generation circuit 1 of the first and second embodiments, the detection circuit 11 has been described as including the down counter 112.
As a modified example of the above, instead of the down counter 112, an address for selecting a plurality of lower-order bits of an address signal corresponding to the set value of the control register 111 at the time of a test and outputting a logical product signal or a logical sum signal of each bit as a detection signal It is also possible to provide a detection circuit.

In the RAM test data generation circuit 1 of the first and second embodiments, the detection circuit 11
11 has been described, but a plurality of RAs to be tested
If the RAM test data generation circuit can be arranged near M, as a modification of the detection circuit 11, the control register 1
Instead of 11, a selection signal of each RAM is directly input, a plurality of lower-order bits of an address signal are selected corresponding to the selection signal of each RAM, and an AND signal or an OR signal of each bit is output as a detection signal. An address detection circuit can be provided, and the circuit area of the RAM test data generation circuit can be further reduced.

[0048]

As described above, the RA according to the present invention is used.
The M test data generation circuit is composed of a simple circuit in which control data and initial value data are set.
On the other hand, based on the matrix configuration of the RAM cell array, it is possible to generate a checkerboard or diagonal test pattern and data of the back test pattern.

As a result, the circuit area of the RAM test data generation circuit is reduced, and the cost of the semiconductor integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a RAM test data generation circuit of the present invention.

FIG. 2 is a flowchart illustrating a procedure example of a test sequence control for testing a RAM;

FIG. 3 is an explanatory diagram showing a configuration example of a memory cell array of a RAM to be tested.

FIG. 4 is a timing chart showing an operation example of the RAM test data generation circuit of FIG. 1;

FIG. 5 is an explanatory diagram showing an example of a test pattern written in a cell array of the RAM in FIG. 3;

FIG. 6 is a block diagram showing Embodiment 2 of a RAM test data generation circuit of the present invention.

FIG. 7 is a timing chart showing an operation example of the RAM test data generation circuit of FIG. 6;

FIG. 8 is an explanatory diagram showing an example of a test pattern written in a cell array of the RAM.

FIG. 9 is a block diagram showing an example of a test circuit in a conventional semiconductor memory device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 RAM test data generation circuit 4 self-test circuit 5 memory cell array 6 transfer gate 7 data register 8 row decoder 9 comparison circuit 11 detection circuit 12 flip-flop circuit 13 shift register circuit 41 micro ROM 42 row address generation section 43 register address generation section 44 Pattern generation unit 45 Control unit

Claims (6)

[Claims] 1. A RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test, wherein the control data is set at a time of the test and the RAM corresponds to the set value.
A detection circuit for detecting an access cycle and outputting a detection signal; and a bus output as each bit output of the data of the test pattern, wherein initial value data is set at the time of testing and inverted during each RAM access cycle during an inactive period of the detection signal. And a flip-flop circuit for performing the test. 2. A RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM during a test, wherein the control data is set during a test and the RAM corresponds to the set value.
And a detection circuit for detecting the access cycle of each of the above and outputting a detection signal. During a test, initial value data is set in an alternative bit inversion pattern, and during a period of inactivity of the detection signal, shift rotation is performed for each RAM access cycle to output each bit. And a shift register circuit that outputs a bus as test pattern data. 3. A control register in which the control data is set at the time of a test, the detection circuit counts down every RAM access cycle at the time of the test, and outputs the detection signal at a zero value. 3. The RAM test data generation circuit according to claim 1, further comprising: 4. The control circuit according to claim 1, wherein said detection circuit selects a control register in which said control data is set during a test, and selects a plurality of lower-order bits of an address signal in accordance with a set value of said control register during a test, and outputs a logical product signal of each bit. 3. The RAM test data generation circuit according to claim 1, further comprising: an address detection circuit that outputs a logical sum signal as the detection signal. 5. A RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM at the time of a test, wherein a plurality of lower-order bits of an address signal are corresponded to a selection signal of the RAM at the time of a test. An address detection circuit for selecting and outputting a logical product signal or a logical sum signal of each bit as a detection signal; a flip-flop circuit in which initial value data is set during a test and which is inverted every RAM access cycle during an inactive period of the detection signal; And an output circuit for outputting the output of the flip-flop circuit as each bit output of the data of the test pattern and outputting the output as a bus. 6. A RAM test data generation circuit which is built in a semiconductor integrated circuit together with a RAM and generates data of a test pattern of the RAM during a test, wherein a plurality of lower-order bits of an address signal are corresponding to a selection signal of the RAM during a test. An address detection circuit for selecting and outputting a logical product signal or a logical sum signal of each bit as a detection signal, and an initial value data set in an alternative bit inversion pattern during a test, and a RAM access cycle during an inactive period of the detection signal. A RAM test data generation circuit, comprising: a shift register circuit that performs a shift rotation; and an output circuit that outputs each bit output of the shift register circuit as data of the test pattern and outputs a bus.