JP2005050393A - Semiconductor device and its failure detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its failure detection method capable of inspecting the failure of a cell of a nonvolatile memory part in the use state by a user. <P>SOLUTION: This semiconductor device and its failure detection method are provided with a plurality of electrically rewritable nonvolatile memory cell arrays 11 arranged in the column and row direction, an access circuit 12 for accessing to the nonvolatile memory cell array 11 to write and read data, a test data storage memory 14 for holding test data 21 constituted with bit pattern, and a comparator circuit 15 for comparing the test data 21 with inspection read-out data 23 read out from the nonvolatile memory cell array 11 for inspecting the failure of the cell of the nonvolatile memory cell array 11 to output a determination signal 24 for showing "coincidence" or "non-coincidence" in this comparison. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a plurality of electrically rewritable nonvolatile memory cells and a failure detection method thereof.
[0002]
[Prior art]
In a conventional semiconductor device having an electrically rewritable nonvolatile memory cell array, a basic program and data are often stored in the nonvolatile memory cell array, so that a memory cell test is performed before shipment. In a system using such a semiconductor device, when a failure occurs in the nonvolatile memory cell, a fatal error is often generated, which may cause a serious problem that the entire system crashes.
[0003]
In particular, in recent years, with the advent of SOC (System on Chip), memory-embedded logic ICs equipped with a nonvolatile memory cell array have increased, and this memory cell test has become increasingly important.
[0004]
For this reason, in the conventional semiconductor device, in order to ensure the reliability of the nonvolatile memory cell array, an expensive test device is used and a memory test before shipment is performed over a long time.
[0005]
Even after shipment, non-volatile memory cells store information by charge injected into the floating gate through an oxide film, resulting in an increase in the number of rewrites and a deterioration in memory cell operating characteristics. There is an essential problem of doing.
[0006]
In order to cope with the aging of the nonvolatile memory cell, a method has been proposed in which overwriting of the memory cell is detected at the time of user use after shipment, and the threshold value is corrected appropriately. That is, there is a means for detecting a threshold abnormality due to overwriting, and when overwriting is detected, Patent Document 1 discloses a method of performing writing again after erasing a memory cell. Japanese Patent Application Laid-Open No. H11-228688 describes a method that uses both the means and the latch circuit for saving data.
[0007]
However, none of these methods is sufficient to ensure the reliability of the memory cell. That is, erroneous writing and data corruption due to inter-cell interference or the like cannot be detected in the user usage state. In order to detect such a cell failure, it is necessary to repeatedly inspect the memory cell array with test data having several bit patterns. However, it is difficult to perform such inspection in a user use state.
[0008]
[Patent Document 1]
JP-A-8-153398
[0009]
[Patent Document 2]
Japanese Patent Laid-Open No. 2000-100980
[0010]
[Problems to be solved by the invention]
As described above, the conventional semiconductor device and the failure detection method thereof have a problem that it is difficult to ensure the reliability of the nonvolatile memory cell in a user use state.
[0011]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of inspecting a cell failure of a nonvolatile memory unit in a user use state and a failure detection method thereof.
[0012]
[Means for Solving the Problems]
According to one aspect of the present invention, a plurality of electrically rewritable nonvolatile memory cells arranged in the row and column directions, and access means for accessing the nonvolatile memory cells to write and read data; Test data holding means for holding test data constituted by a bit pattern; and the test data generated by the access means from the test data holding means for generating a test address for a fault test of the nonvolatile memory cell From the test data holding means, and control means for controlling the access means to output test read data read from the test address of the nonvolatile memory cell. Received from the test data received and the access means Comparing the test data read, the semiconductor device is provided, characterized in that it comprises a comparing means for outputting a determination signal indicating their "match" or "mismatch".
[0013]
According to another aspect of the present invention, a plurality of electrically rewritable nonvolatile memory cells arranged in the row and column directions;
Access means for accessing the nonvolatile memory cell to write and read data, test data holding means for holding test data constituted by a bit pattern, and generating an inspection address, and inspecting the nonvolatile memory cell A failure detection method for a semiconductor device, comprising: a control unit that controls an address to perform a failure inspection; and a comparison unit that compares the test data received from the test data holding unit and the data received from the access unit, An access write means writes the test data received from the test data holding means to the test address of the non-volatile memory cell, and a test memory write step with a predetermined time interval from the test write step. Test memory cell A test readout step for outputting the test readout data read from the test to the comparison unit, and the comparison unit compares the test data with the test readout data, and outputs a determination signal indicating “match” or “mismatch”. There is provided a failure detection method for a semiconductor device, comprising a determination step of outputting to the control means.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments (hereinafter referred to as embodiments) of a semiconductor device and a failure detection method thereof according to the present invention will be described with reference to the drawings.
[0015]
(First embodiment)
FIG. 1 is a circuit block diagram showing a semiconductor device according to the first embodiment of the present invention. Here, the part mainly related to the cell failure inspection performed at the time of data writing to the nonvolatile memory unit 13 is shown.
[0016]
The semiconductor device according to the first embodiment of the present invention includes a nonvolatile memory cell array 11 in which electrically rewritable nonvolatile memory cells are arranged in the row and column directions, and a row decoder and a column decoder for accessing these memory cells. Including an access circuit 12, a non-volatile memory cell array 11 and a non-volatile memory unit 13 having an access circuit 12, a test data storage memory 14 for holding test data 21 used for cell failure inspection, and a non-volatile memory unit for cell failure inspection A comparison circuit 15 for comparing and checking the test read data 23 received from the test data 13 and the test data 21 received from the test data storage memory 14, a control circuit 16 for controlling these circuits to perform a cell fault test, and a cell fault is found. Failure address that stores the failure address 26 It has a paid memory 17.
[0017]
The control circuit 16 outputs the test address 19 and the write data 20 to the nonvolatile memory unit 13 based on the received input signal 18, and outputs the selection signal 22 of the test data 21 to the test data storage memory 14.
[0018]
The test data storage memory 14 outputs the test data 21 to the nonvolatile memory unit 13 and the comparison circuit 15 based on the selection signal 22 from the control circuit 16.
[0019]
The nonvolatile memory unit 13 outputs inspection read data 23 to the comparison circuit 15 based on the inspection address 19 and the test data 21.
[0020]
The comparison circuit 15 compares the test data 21 and the inspection read data 23 and outputs a determination signal 24 indicating “match” or “mismatch” to the control circuit 16.
[0021]
Further, when the determination signal 24 is “mismatch”, the control circuit 16 outputs a cell failure detection signal 25 to notify the user of the cell failure, and outputs the failure address 26 to the failure address storage memory 17.
[0022]
Next, the operation of each unit will be described.
[0023]
The non-volatile memory unit 13 includes a non-volatile memory cell array 11 and an access circuit 12, and reads data from the non-volatile memory cell array 11 and writes data to the non-volatile memory cell array 11 in accordance with requests from the control circuit 16. .
[0024]
In the nonvolatile memory cell array 11, electrically rewritable memory cells that store information by charges injected into a floating gate through an oxide film are arranged in the row and column directions, and the access circuit 12 stores data in byte units. Reading and writing are performed.
[0025]
The access circuit 12 has a verify function at the time of writing, and appropriately controls the writing time to the nonvolatile memory cell array 11 so that overwriting does not occur in a normal writing sequence.
[0026]
The test data storage memory 14 is a read-only memory (hereinafter referred to as ROM), and test data 21 is written in advance before product shipment. The test data 21 is a bit pattern in which “0” and “1” are alternately arranged, and is composed of a pair of data that are inverted patterns.
[0027]
FIG. 2 is an image diagram showing the test data 21 according to the first embodiment of the present invention. Here, as an example, test data A27 of “55H” and test data B28 of “AAH” are shown. Hereinafter, the hexadecimal number is represented by adding “H” at the end.
[0028]
The comparison circuit 15 is an 8-bit logic circuit that compares the test data 21 from the test data storage memory 14 and the test read data 23 from the nonvolatile memory unit 13 in bit units. If all these 8 bits match, “match” is output to the control circuit 16 as a determination signal 24, and if even one bit is different, “not match” is output to the control circuit 16.
[0029]
The failure address storage memory 17 is a register circuit that temporarily stores the failure address 26 received from the control circuit 16. The stored failure address 26 is output to the outside as necessary.
[0030]
The control circuit 16 receives an address, data, and a processing command as the input signal 18, and generates a test address 19, write data 20, a selection signal 22, and the like based on these. The test address 19 and the write data 20 are supplied to the nonvolatile memory unit 13, and the selection signal 22 is supplied to the test data storage memory 14. Further, when the determination signal 24 received from the comparison circuit 15 is “mismatch”, the control circuit 16 outputs the test address 19 at that time to the failure address storage memory 17 as the failure address 26, and the cell failure detection signal 25. Output to the outside.
[0031]
Next, a failure detection method for the semiconductor device having the above-described configuration, that is, a cell failure inspection in writing data to the nonvolatile memory unit 13 will be described.
[0032]
FIG. 3 is a flowchart showing a semiconductor device failure detection method according to the first embodiment of the present invention. Here, the portion related to the data writing to the nonvolatile memory unit 13 and the cell failure inspection performed at that time is shown.
[0033]
The failure detection method for a semiconductor device according to the first embodiment of the present invention includes an initialization step 31 for generating an inspection address 19, an inspection A step 32 for performing a cell failure inspection with test data A27, and a cell failure inspection with test data B28. A test B step 33 for performing a data write, a write step 34 for performing original data writing, an error processing step 35 for performing processing when a cell failure is found, and an error notification step 36 for informing the outside of the cell failure.
[0034]
Further, the inspection A step 32 includes an inspection writing A step 37, an inspection reading A step 38, and a determination A step 39. The inspection B step 33 includes an inspection writing B step 40, an inspection reading B step 41, and a determination B. Step 42 consists of steps.
[0035]
In the initialization step 31, the control circuit 16 receives the write command, the write address, and the write data 20 as the input signal 18, generates an address for performing a cell failure inspection based on these, and generates a nonvolatile memory as the inspection address 19. Supply to the memory unit 13.
[0036]
The generation of such an address is determined based on a logical address logically assumed for the user to access the nonvolatile memory cell array 11 and a physical arrangement at the layout level of the nonvolatile memory cell array 11. Required because the physical address is different.
[0037]
In the inspection A step 32, the control circuit 16 outputs a selection signal 22 for selecting the test data A27 to the test data storage memory 14, and uses the test data A27 to inspect the memory cell at the inspection address 19.
[0038]
That is, first, in the test write A step 37, the control circuit 16 operates to write the test data A27 received by the access circuit 12 to the test address 19 of the nonvolatile memory cell array 11.
[0039]
Next, in the test read A step 38, the control circuit 16 causes the access circuit 12 to read data from the test address 19 at a certain time interval and output this to the comparison circuit 15 as test read data 23. Operate. Here, if there is a failure in the memory cell at the test address 19, the read test read data 23 has a different value from the original test data A27.
[0040]
Next, in the determination A step 39, the comparison circuit 15 compares the test data A27 and the inspection read data 23 bit by bit and outputs the result to the control circuit 16 as a determination signal 24. Based on the received determination signal 24, the control circuit 16 proceeds to the inspection B step 33 if “match” (OK), and proceeds to the error processing step 35 if “not match” (NG).
[0041]
In the inspection B step 33, the control circuit 16 outputs the selection signal 22 of the test data B28 to the test data storage memory 14, and, like the inspection A step 32, the test data B28 is used to break down the memory cell at the inspection address 19. inspect.
[0042]
The inspection writing B step 40 and the inspection reading B step 41 are the same as the inspection writing A step 37 and the inspection reading A step 38, respectively, except that the test data B28 is used.
[0043]
Further, the determination B step 42 is the same as the determination A step 39 except that if the determination signal 24 is “match” (OK), the process proceeds to the writing step 34.
[0044]
Test data B28 = "AAH" is a bit inversion pattern of test data A27 = "55H". This is to detect a so-called fixing failure in which the memory cell is fixed to “0” or “1”.
[0045]
Further, in order to detect the influence of inter-cell interference, “55H” and “AAH” in which “0” and “1” are alternately arranged are used as the test data 21, and between the writing and reading of the test data 21 Is provided with a certain time interval.
[0046]
If there is no problem in the check A step 32 and the check B step 33 (OK), in the write step 34, the control circuit 16 operates so that the access circuit 12 writes the write data 20 to the check address 19 in a normal write sequence.
[0047]
If a cell failure is detected in the inspection A step 32 or the inspection B step 33 (NG), the process proceeds to the error processing step 35. In the error processing step 35, the control circuit 16 interrupts the writing to the nonvolatile memory cell array 11, and outputs the test address 19 at that time to the failure address storage memory 17 as the failure address 26 for storage.
[0048]
In error processing step 35, the control circuit 16 outputs a cell failure detection signal 25 to notify the user that data could not be written due to a cell failure.
[0049]
When a block write command is given as a processing command (so-called block mode), the control circuit 16 sequentially generates a physical address necessary for writing data and supplies it to the nonvolatile memory unit 13 to cause the cell failure described above. It operates to repeatedly execute inspection and data writing congestion.
[0050]
In this way, by checking the memory cell immediately before data writing, higher reliability of written data can be guaranteed.
[0051]
According to the first embodiment, since a cell failure is inspected using the test data 21 held in the test data storage memory 14 immediately before data is written to the nonvolatile memory cell array 11, it has high reliability. A semiconductor device can be realized.
[0052]
In addition, since the cell failure inspection is performed using the pair of test data 21 having an appropriate bit pattern in consideration of the influence of the memory cell fixation failure and the inter-cell interference, the failure detection method of the semiconductor device with high reliability Can be realized.
[0053]
Furthermore, since the cell failure detection signal 25 and the failure address 26 are notified to the user, the user can respond to the cell failure according to the importance of the data, and a flexible semiconductor device for the user system and its failure detection method are realized. be able to.
[0054]
In the first embodiment described above, the test data storage memory 14 is a ROM. However, the present invention is not limited to this and may be an EEPROM. In that case, it is also possible to configure the user so that arbitrary test data 21 can be set. Alternatively, the test data storage memory 14 may be a register circuit or the like, and the test data 21 stored in a part of the nonvolatile memory cell array 11 may be read out to the test data storage memory 14 immediately after the power is turned on.
[0055]
Furthermore, although the test data 21 uses “55H” and “AAH” as a pair, the present invention is not limited to this, and address scramble and data scramble determined by the layout design of the nonvolatile memory cell array 11 are used. Based on this, a plurality of appropriate bit patterns can be selected. For example, a bit pattern having a failure rate higher than a predetermined reference value in cell failure inspection during development may be adopted as the test data 21.
[0056]
Further, when the nonvolatile memory unit 13 is a batch erase type, since the area is erased before data writing, the cell failure inspection at the time of writing may be only in one direction, not necessarily a pair test. Data 21 need not be used.
[0057]
Furthermore, in the first embodiment described above, the pair of test data 21 that are bit-inverted is held in the test data storage memory 14, but the present invention is not limited to this. 16 may be configured to generate.
[0058]
Furthermore, in the first embodiment described above, the cell failure inspection method in writing data in byte units has been shown. However, the present invention is not limited to this, and is applied to a block mode in which the same data is written in a certain area. You can also That is, the test address 19 is sequentially generated from the write start address and the number of write bytes received as the input signal 18, and the test write flow shown in FIG.
[0059]
(Second Embodiment)
The second embodiment of the present invention is applied to a case where a cell failure inspection is performed on an arbitrary memory cell that is determined to be important by a user immediately after power-on. In addition to the configuration of the first embodiment, cell data is temporarily saved. The evacuation means is provided.
[0060]
FIG. 4 is a circuit block diagram showing a semiconductor device according to the second embodiment of the present invention. Here, the part mainly related to the cell failure inspection of the nonvolatile memory unit 53 is shown.
[0061]
A semiconductor device according to the second embodiment of the present invention includes a nonvolatile memory cell array 51 in which electrically rewritable nonvolatile memory cells are arranged in the row and column directions, and a row decoder and a column decoder for accessing these memory cells. Including the access circuit 52, the nonvolatile memory cell array 51 including the nonvolatile memory cell array 51 and the access circuit 52, the test data storage memory 54 that holds the test data 61 used for the cell failure inspection, and the inspection address 60 during the cell failure inspection. A data saving memory 55 for saving cell data; a comparison circuit 56 for comparing and comparing the test read data 63 received from the nonvolatile memory unit 53 and the test data 61 received from the test data storage memory 54 for cell fault testing; A control circuit 5 for controlling these circuits in order to perform cell failure inspection , And has a fault address storage memory 58 for storing the fault address 66 when the cell failure is found.
[0062]
The control circuit 57 outputs the test address 60 to the nonvolatile memory unit 53 based on the received input signal 59 and outputs the selection signal 62 of the test data 61 to the test data storage memory 54.
[0063]
The test data storage memory 54 outputs the test data 61 to the nonvolatile memory unit 53 and the comparison circuit 56 based on the selection signal 62 from the control circuit 57.
[0064]
The nonvolatile memory unit 53 outputs inspection read data 63 to the comparison circuit 56 based on the inspection address 60 and the test data 61. Further, the nonvolatile memory unit 53 outputs the cell data at the inspection address 60 to the data saving memory 55 as the saving data 67 prior to the cell failure inspection.
[0065]
The data saving memory 55 outputs the saving data 67 saved after the cell failure inspection to the nonvolatile memory unit 53.
[0066]
The comparison circuit 56 compares the test data 61 and the inspection readout data 63 and outputs a determination signal 64 indicating “match” or “mismatch” to the control circuit 57.
[0067]
In addition, when the determination signal 64 is “mismatch”, the control circuit 57 outputs a cell failure detection signal 65 to notify the user of the cell failure, and outputs the failure address 66 to the failure address storage memory 58.
[0068]
Except for the data saving memory 55 and the control circuit 57, the configuration and operation of each unit are the same as those in the first embodiment, and thus detailed description thereof is omitted. The difference from the first embodiment is that a cell failure inspection is performed on the nonvolatile memory cell array 51 in which data is already stored, and the data stored in the inspection address 60 is replaced with the cell failure inspection. In the meantime, it is temporarily stored in the data save memory 55 as save data 67.
[0069]
The data saving memory 55 is a register circuit that temporarily stores the saving data 67 received from the nonvolatile memory unit 53. The saving data 67 is stored in the nonvolatile memory cell array by the access circuit 52 of the nonvolatile memory unit 53 after the cell failure inspection is completed. 51 is written back to the inspection address 60.
[0070]
The control circuit 57 receives an address and a processing command as the input signal 59 and generates a test address 60 and a selection signal 62 based on these. The inspection address 60 is supplied to the nonvolatile memory unit 53, and the selection signal 62 is supplied to the test data storage memory 54. In addition, when the determination signal 64 received from the comparison circuit 56 is “mismatch”, the control circuit 57 outputs the test address 60 at that time to the failure address storage memory 58 as the failure address 66, and outputs the cell failure detection signal 65. Output to the outside.
[0071]
Next, a failure detection method for the semiconductor device having the above-described configuration, that is, a cell failure inspection of the nonvolatile memory unit 53 will be described.
[0072]
FIG. 5 is a flowchart showing a failure detection method for a semiconductor device according to the second embodiment of the present invention. Here, the part mainly related to the cell failure inspection of the nonvolatile memory unit 53 is shown. Further, the test data 61 used for the cell failure inspection is the same test data A27 and test data B28 as in the first embodiment.
[0073]
In the semiconductor device failure detection method according to the second embodiment of the present invention, the cell failure test is performed by the initialization step 71 for generating the test address 60, the save step 72 for saving the cell data of the test address 60, and the test data A27. A test A step 73 to be performed, a test B step 74 to perform a cell fault test using the test data B28, a write back step 75 to write back the saved data 67 to the test address 60, an error processing step 76 to perform a process when a cell fault is found, And an error notification step 77 for notifying the outside of the cell failure.
[0074]
Further, the inspection A step 73 includes an inspection writing A step 78, an inspection reading A step 79, and a determination A step 80, and an inspection B step 74 includes an inspection writing B step 81, an inspection reading B step 82, and a determination B. Step 83 consists of steps.
[0075]
In the initialization step 71, the control circuit 57 receives the cell test command and the address as the input signal 59, generates a test address 60 based on these, and supplies the test address 60 to the nonvolatile memory unit 53.
[0076]
In the save step 72, the control circuit 57 operates so that the access circuit 52 reads the cell data of the test address 60 of the nonvolatile memory cell array 51 and the data save memory 55 temporarily stores it as the save data 67.
[0077]
Since the inspection A step 73 and the inspection B step 74 are substantially the same as those in the first embodiment, detailed description thereof will be omitted. The difference from the first embodiment is that when the determination signal 64 is “match” in the determination B step 83 (OK), the process proceeds to a write-back step 75 in which the saved data 67 is written to the nonvolatile memory cell array 51. It is.
[0078]
In the write back step 75, the control circuit 57 outputs the saved data 67 temporarily stored in the data saving memory 55 in the saving step 72 to the nonvolatile memory unit 53, and the access circuit 52 outputs the saved data 67 to the test address of the nonvolatile memory cell array 51. Operate to write to 60.
[0079]
If a cell failure is detected in the inspection A step 73 or the inspection B step 74 (NG), the process proceeds to the error processing step 76. Since the error processing step 76 and the error notification step 77 are the same as those in the first embodiment, description thereof will be omitted.
[0080]
Similar to the block mode in the first embodiment, when a block inspection command is given, the control circuit 57 operates to generate and supply the inspection address 60 sequentially and repeatedly execute the cell failure inspection described above. To do.
[0081]
In this way, cell failure inspection can be performed on the address designated by the user without destroying the cell data. For example, when the above inspection flow is applied to an inspection immediately after the power is turned on, the reliability of the system can be reduced in a short inspection time by limiting the inspection area to a highly important memory cell area that may cause a system crash. Can be secured.
[0082]
In addition, by disclosing the processing command for performing cell failure inspection in the user area to the user, the user can execute cell failure inspection from the application as necessary. Can be configured.
[0083]
According to the second embodiment, by temporarily storing data in the data saving memory 55, the test data 61 held in the test data storage memory 54 is used without destroying the data in the nonvolatile memory cell array 51. Thus, a cell failure can be inspected at any time, so that a highly reliable semiconductor device can be realized.
[0084]
In addition, since the cell failure inspection is performed in consideration of the influence of the memory cell fixation failure and inter-cell interference using the paired test data 61 having an appropriate bit pattern, a highly reliable failure detection method for a semiconductor device Can be realized.
[0085]
Further, since the cell failure detection signal 65 and the failure address 66 are notified to the user, the user can cope with the cell failure according to the importance of the data, and a flexible semiconductor device for the user system and its failure detection method are realized. be able to.
[0086]
In the second embodiment described above, the data saving memory 55 is a register circuit. However, the present invention is not limited to this, and for example, a RAM (Random Access Memory) using volatile memory cells. It can also be configured.
[0087]
In the second embodiment described above, the test data storage memory 54 is a ROM. However, as in the first embodiment, the present invention is not limited to this.
[0088]
Further, the test data 61 can select a plurality of appropriate bit patterns as in the first embodiment, or the pair of test data 61 is not necessarily used.
[0089]
Further, as in the first embodiment, the control circuit 57 can generate the bit inversion pattern.
[0090]
Furthermore, as in the first embodiment, the present invention can also be applied to a block inspection mode in which a certain region is continuously inspected for cell failures.
[0091]
(Third embodiment)
The third embodiment of the present invention is applied to area data writing in which the same data is written to a predetermined area, and the influence of inter-cell interference in the nonvolatile memory cell array 11 can be detected more precisely. In the third embodiment, a plurality of test data 21 having different patterns for each physical address and its inverted pattern are used.
[0092]
FIG. 6 is an image diagram showing an inspection data map of the semiconductor device according to the third embodiment of the present invention. Here, an area consisting of 6 bytes of 3 rows and 2 columns is shown.
[0093]
6A is an image diagram in which the test data 21 is written so that the cell data becomes a checker pattern at the physical layout level of the nonvolatile memory cell array 11, and FIG. 6B is an image diagram of the inverted pattern. is there.
[0094]
Writing 1 byte to the nonvolatile memory cell array 11 is 8-bit writing continuous in the row direction at the physical layout level. In FIG. 6, the horizontal direction is the row direction and the vertical direction is the column direction. That is, the row selection lines are arranged in the horizontal direction and the column selection lines are arranged in the vertical method.
[0095]
In the physical address (hereinafter represented as [0101] using a hexadecimal number), the upper 8 bits represent the physical row address, and the lower 8 bits represent the physical column address. Therefore, as shown in FIG. 6, [0100] is arranged below [0000] (in the column direction), and further [0200] is arranged below it. [0001] is arranged on the right side (row direction) of [0000], [0101] is arranged on the right side of [0100], and [0201] is arranged on the right side of [0200].
[0096]
In order to form a checker pattern as shown in FIG. 6A in such a region, test data A27 = “55H” is written in [0000], [0001], [0200], and [0201], Test data B28 = "AAH" may be written in [0100] and [0101]. Similarly, in order to form the inverted pattern of FIG. 6B, test data B28 = “AAH” is written in [0000], [0001], [0200], and [0201], and [0100] and [0101] Test data A27 = "55H" may be written.
[0097]
In the checker pattern formed in this way, the cell failure detection sensitivity is higher than that of the first embodiment. This is because the same test data 21 is repeatedly written in the block mode described in the first embodiment, so that the stripe pattern, that is, the adjacent cells in the vertical direction have the same data, whereas the checker pattern described above performs the inspection. This is because, in any memory cell except for the peripheral portion of the region, the four cells on the top, bottom, left, and right are inverse data and are easily affected by inter-cell interference.
[0098]
The circuit block diagram of the semiconductor device according to the third embodiment of the present invention is the same as FIG. 1 shown in the first embodiment, and the description is omitted.
[0099]
Next, a semiconductor device failure detection method according to the third embodiment will be described.
[0100]
FIG. 7 is a flowchart showing a failure detection method for a semiconductor device according to the third embodiment of the present invention. Here, the portion related to the area data writing to the nonvolatile memory portion 13 and the cell failure inspection performed at that time is shown.
[0101]
A failure detection method for a semiconductor device according to the third embodiment of the present invention includes an initialization step 91 for generating a start address of a cell failure inspection, an inspection A step 92 for performing a cell failure inspection with a checker pattern, and a cell failure with an inversion pattern. A test B step 93 for performing a test, a write step 94 for performing original data writing, an error processing step 95 for performing processing when a cell fault is found, and an error notifying step 96 for notifying the outside of the cell fault are configured.
[0102]
The inspection A step 92 includes an area writing A step 97, an inspection reading A step 98, a determination A step 99, and an end determination A step 100. The inspection B step 93 includes an area writing B step 101, an inspection reading B, and the like. It comprises step 102, determination B step 103, and end determination B step 104.
[0103]
In the initialization step 91, the control circuit 16 receives the area write command, the write start address, the number of write bytes, and the write data 20 as the input signal 18, and generates an address for starting the cell failure inspection based on these. The inspection address 19 is supplied to the nonvolatile memory unit 13.
[0104]
In the inspection A step 92, the control circuit 16 sequentially outputs the selection signal 22 necessary for forming the checker pattern shown in FIG. 6A to the test data storage memory 14, and uses the test data 21 to perform predetermined processing. The memory cell area is checked for failure.
[0105]
That is, first, in the area write A step 97, the control circuit 16 sequentially writes the test data 21 received by the access circuit 12 to the test address 19 of the nonvolatile memory cell array 11, for example, as shown in FIG. Operate. The generation of the test address 19 is performed in the same manner as in the block mode in the first embodiment.
[0106]
Next, in the test read A step 98, the control circuit 16 operates so that the access circuit 12 reads data from the test address 19 and outputs this as test read data 23 to the comparison circuit 15.
[0107]
Next, in decision A step 99, the comparison circuit 15 compares the test data 21 and the inspection read data 23 bit by bit, and outputs the result as a decision signal 24 to the control circuit 16. Based on the received determination signal 24, the control circuit 16 proceeds to the end determination A step 100 if “match” (OK), or to the error processing step 95 if “not match” (NG).
[0108]
Next, in the end determination A step 100, the control circuit 16 determines whether or not the determination A step 99 for the number of received write bytes has ended. If the end determination is “No”, the next inspection address 19 is output to the nonvolatile memory unit 13, and the processing proceeds to inspection reading A step 98. If the end determination is “Yes”, the process proceeds to inspection B step 93.
[0109]
In the inspection B step 93, the control circuit 16 sequentially outputs the selection signal 22 necessary for forming the inversion pattern shown in FIG. 6B to the test data storage memory 14, and uses the test data 21 to perform predetermined processing. The memory cell area is checked for failure.
[0110]
The area writing B step 101 and the inspection reading B step 102 are the same as the area writing A step 97 and the inspection reading A step 98, respectively, except that the test data 21 which is an inverted pattern is used.
[0111]
Further, the determination B step 103 is the same as the determination A step 99. Further, the end determination B step 104 is the same as the end determination A step 100A except that the process proceeds to the write step 94 when the failure inspection of the predetermined memory cell region ends (Yes), and the description thereof is omitted.
[0112]
If there is no problem in the check A step 92 and the check B step 93 (OK), in the write step 94, the control circuit 16 operates so that the access circuit 12 sequentially writes the write data 20 to the check address 19 in the normal write sequence. .
[0113]
If a cell failure is detected in the inspection A step 92 or the inspection B step 93 (NG), the process proceeds to the error processing step 95. Since the error processing step 95 and the error notification step 96 are the same as those in the first embodiment, the description thereof will be omitted.
[0114]
According to the third embodiment, in addition to the effects of the invention described in the first embodiment, it is possible to detect the influence of inter-cell interference in consideration of the physical arrangement of the memory cells, and to detect the cell failure with higher sensitivity. Can be realized.
[0115]
In the third embodiment described above, the end determination is performed based on the number of write bytes. However, the present invention is not limited to this. For example, the end determination may be received based on the write end address. it can.
[0116]
In the third embodiment described above, the cell failure inspection is performed on the write area using the checker pattern at the layout level. However, the present invention is not limited to this. High test patterns may be used.
[0117]
(Fourth embodiment)
The fourth embodiment of the present invention is applied to the case where a cell failure inspection is performed on an arbitrary memory cell area that the user determines to be important immediately after the power is turned on, and has substantially the same configuration as that of the second embodiment.
[0118]
Since the circuit block diagram of the semiconductor device according to the fourth embodiment of the present invention is almost the same as that of FIG. 4 shown in the second embodiment, detailed description thereof is omitted. The difference from the second embodiment is that the data saving memory 55 is composed of a RAM in order to temporarily store a large amount of saving data 67.
[0119]
Furthermore, in the fourth embodiment of the present invention, a specified memory cell region is inspected for failure using a checker pattern at the layout level, similarly to FIG. 6 shown in the third embodiment. The difference from the third embodiment is that the cell data of the corresponding designated area is temporarily stored in the data saving memory 55 before the cell failure inspection, and is written back after the cell failure inspection is completed.
[0120]
Next, a semiconductor device failure detection method according to the fourth embodiment will be described.
[0121]
FIG. 8 is a flowchart showing a semiconductor device failure detection method according to the fourth embodiment of the present invention. Here, the part mainly related to the cell failure inspection of the nonvolatile memory unit 53 is shown.
[0122]
The failure detection method for a semiconductor device according to the third embodiment of the present invention includes an initialization step 111 for generating a start address for cell failure inspection, an area saving step 112 for saving cell data in a specified area, and a cell failure using a checker pattern. Inspection A step 113 for performing inspection, inspection B step 114 for performing cell failure inspection with an inversion pattern, area writing back step 115 for writing back saved data 67, error processing step 116 for performing processing when a cell failure is found, and cell It comprises an error notification step 117 for notifying the outside of the failure.
[0123]
The inspection A step 113 includes an area writing A step 118, an inspection reading A step 119, a determination A step 120, and an end determination A step 121, and the inspection B step 114 includes an area writing B step 122, an inspection reading B. It consists of step 123, determination B step 124, and end determination B step 125.
[0124]
In the initialization step 111, the control circuit 57 receives the area inspection command, the inspection start address, and the number of inspection bytes as the input signal 59, and generates an address for starting the cell failure inspection based on these.
[0125]
In the area saving step 112, the control circuit 57 sequentially generates the test address 60 based on the start address and the number of check bytes generated in the initialization step 111, while transferring the cell data in the nonvolatile memory cell array 51 area to the data saving memory. It operates to retreat to 55.
[0126]
The generation of the test address 60 is performed in the same manner as the block mode in the first embodiment.
[0127]
Since the inspection A step 113 and the inspection B step 114 are substantially the same as those in the third embodiment, the description thereof is omitted.
[0128]
If there is no problem in the inspection A step 113 and the inspection B step 114 (OK), in the area write-back step 115, the control circuit 57 stores the saved data 67 temporarily stored in the data saving memory 55 in the area saving step 112. The access circuit 52 of the unit 53 operates so as to write back to the original test address 60 of the nonvolatile memory cell array 51.
[0129]
If a cell failure is detected in the inspection A step 113 or the inspection B step 114 (NG), the process proceeds to the error processing step 116. Since the error processing step 116 and the error notification step 117 are the same as those in the first embodiment, description thereof will be omitted.
[0130]
According to the fourth embodiment, in addition to the effects of the invention described in the second embodiment, it is possible to detect the influence of inter-cell interference in consideration of the physical arrangement of the memory cells, and to detect a cell failure with higher sensitivity. Can be realized.
[0131]
In the first to fourth embodiments described above, the control circuit and the comparison circuit are independent logic circuits. However, the present invention is not limited to this, and includes a register circuit such as a failure address storage memory. The functions described above can be implemented using a CPU and its program. In this case, since the first to fourth embodiments can be implemented by changing the program, it is possible to realize a semiconductor device having more flexibility for the user system and its failure detection method.
[0132]
【The invention's effect】
As described above, according to the present invention, since appropriate test data is held in the test data storage memory, a semiconductor device capable of inspecting a cell failure in a nonvolatile memory unit in a user use state and a failure detection method thereof are provided. Can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is an image diagram showing test data according to the first embodiment of the present invention.
FIG. 3 is a flowchart showing a semiconductor device failure detection method according to the first embodiment of the present invention;
FIG. 4 is a circuit block diagram showing a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a flowchart showing a semiconductor device failure detection method according to a second embodiment of the present invention;
FIG. 6 is an image diagram showing an inspection data map of a semiconductor device according to a third embodiment of the present invention.
FIG. 7 is a flowchart showing a failure detection method for a semiconductor device according to a third embodiment of the present invention.
FIG. 8 is a flowchart showing a failure detection method for a semiconductor device according to a fourth embodiment of the present invention.
[Explanation of symbols]
11, 51 Nonvolatile memory cell array
12, 52 Access circuit
13, 53 Nonvolatile memory section
14, 54 Test data storage memory
15, 56 Comparison circuit
16, 57 Control circuit
17, 58 Fault address storage memory
18, 59 Input signal
19, 60 Inspection address
20 Write data
21, 61 Test data
22, 62 selection signal
23, 63 Inspection readout data
24, 64 judgment signal
25, 65 Cell failure detection signal
26, 66 Fault address
27 Test data A
28 Test data B
31, 71, 91, 111 Initialization step
32, 73, 92, 113 Inspection A step
33, 74, 93, 114 Inspection B step
34, 94 Writing step
35, 76, 95, 116 Error processing steps
36, 77, 96, 117 Error notification step
37, 78 Inspection writing A step
38, 79, 98, 119 Inspection readout A step
39, 80, 99, 120 Judgment A step
40, 81 Inspection writing B step
41, 82, 102, 123 Inspection readout B step
42, 83, 103, 124 Judgment B step
55 Data save memory
67 Saved data
72 evacuation step
75 Write-back step
97, 118 Area writing A step
100, 121 End determination A step
101, 122 area write B step
104, 125 End determination B step
112 Area save step
115 Area write back step

Claims (22)

A plurality of electrically rewritable nonvolatile memory cells arranged in the row and column directions;
Access means for accessing the nonvolatile memory cell to write and read data;
Test data holding means for holding test data constituted by bit patterns;
A test address of the nonvolatile memory cell is generated, and the test data held in the test data holding unit by the access unit is written to the nonvolatile memory cell of the test address, and then the nonvolatile memory cell is written by the access unit. Control means for controlling to output test read data read from the test address of the memory cell;
Comparing means for comparing the test data held in the test data holding means and the test read data read by the access means, and outputting a determination signal indicating their “match” or “mismatch”. A semiconductor device. 2. The semiconductor according to claim 1, wherein the plurality of nonvolatile memory cells, the access unit, the test data holding unit, the control unit, and the comparison unit are formed on the same semiconductor substrate. apparatus. The control means includes
The semiconductor device according to claim 1, wherein a failure detection signal is output when the determination signal is “mismatch”. The control means includes
2. The semiconductor device according to claim 1, wherein when the determination signal is “match”, the received write data is output to the access unit and controlled to be written to the test address. Further comprising saved data storage means for temporarily storing data read from the nonvolatile memory cell;
The control means includes
Before writing the test data to the nonvolatile memory cell, the access means saves the saved data read from the nonvolatile memory cell based on the inspection address to the saved data storage means,
2. The control according to claim 1, wherein when the determination signal is “match”, control is performed so that the saved data saved in the saved data storage unit is written back to the test address of the nonvolatile memory cell. Semiconductor device. The control means includes
A test start address and a test end address are received, and a plurality of the test addresses are sequentially generated based on the test start address and the test end address, and a predetermined region of the nonvolatile memory cell is continuously generated using the generated test addresses. 2. The semiconductor device according to claim 1, wherein the semiconductor device is controlled so as to be inspected for failure. The test data held in the test data holding means is
At least two test data with different bit patterns,
The control means includes
A test start address and a test end address are received, a plurality of the test addresses are sequentially generated based on the test start address and the test end address, and a region of the nonvolatile memory cell defined by the test start address and the test end address is a desired bit pattern A non-volatile memory cell that sequentially outputs a selection signal for selecting one of the test data to the test data holding means, and uses the generated test address and the selected test data. The semiconductor device according to claim 1, wherein the region is controlled so as to be inspected for failure. 8. The semiconductor device according to claim 7, wherein the desired bit pattern written in the area of the nonvolatile memory cell for a fault inspection is a checker pattern. A failure address storage means for temporarily storing the address;
The control means includes
2. The semiconductor device according to claim 1, wherein when the determination signal is “mismatch”, the inspection address is further output as a failure address to the failure address storage means. The test data held in the test data holding means is
A pair of test data each having a predetermined bit pattern and its bit inversion pattern,
The control means includes
A selection signal for sequentially selecting the pair of test data is output to the test data holding means, and the nonvolatile memory cells are further controlled to sequentially inspect for a failure with the pair of test data using the inspection address. The semiconductor device according to claim 1. The test data is
2. The semiconductor device according to claim 1, comprising a bit pattern in which “0” and “1” are alternately arranged. A failure detection method for a semiconductor device, comprising: a plurality of electrically rewritable nonvolatile memory cells arranged in a row and column direction; and access means for accessing the nonvolatile memory cells to write and read data. A test address generation step for generating a test address;
A test writing step of writing test data constituted by a bit pattern to the nonvolatile memory cell of the generated test address by the access means;
A test read step for reading test read data from the nonvolatile memory cell at the test address by the access means at a time interval from the test write step;
A determination step of comparing the test data with the inspection read data and outputting a determination signal indicating their “match” or “mismatch”;
A failure detection method for a semiconductor device, comprising: 13. The failure detection method for a semiconductor device according to claim 12, wherein each step is executed by an integrated circuit formed on the same semiconductor substrate including the plurality of nonvolatile memory cells and the access means. 13. The semiconductor device failure detection method according to claim 12, further comprising an error notification step in which the control means outputs a failure detection signal when the determination signal is "mismatch" in the determination step. 13. The method according to claim 12, further comprising: a write step of outputting the write data received by the control unit to the access unit and writing to the check address when the determination signal is “match” in the determination step. A method for detecting a failure of a semiconductor device according to claim 1. A failure detection method for a semiconductor device, further comprising save data storage means for temporarily storing data read from the nonvolatile memory cell,
Before the test writing step, a saving step for saving the saved data read from the nonvolatile memory cell by the access unit to the saved data storage unit based on the test address;
A write-back step of writing back the saved data saved in the saved data storage means to the test address of the nonvolatile memory cell when the judgment signal is “match” in the judging step; The semiconductor device failure detection method according to claim 12. Further comprising an inspection step comprising the inspection writing step, the inspection reading step, and the determination step;
The inspection step is repeated for a plurality of inspection addresses generated based on the inspection start address and inspection end address received by the control means, and a predetermined region of the nonvolatile memory cell is continuously inspected for failure. The method for detecting a failure of a semiconductor device according to claim 12. And further comprising an inspection step comprising the inspection readout step and the determination step,
The test data held in the test data holding means is
At least two test data with different bit patterns,
The inspection writing step includes:
An area writing step of selecting and writing the test data so that the area of the nonvolatile memory cell defined by the inspection start address and the inspection end address received by the control means has a desired bit pattern;
13. The failure detection method for a semiconductor device according to claim 12, wherein the inspection step is repeated for the region of the nonvolatile memory cell in which the desired bit pattern is written in the region writing step. 19. The failure detection method for a semiconductor device according to claim 18, wherein the desired bit pattern written into the nonvolatile memory cell in the area writing step is a checker pattern. A failure detection method for a semiconductor device further comprising a failure address storage means for temporarily storing an address,
13. The error processing step further comprising: when the determination signal is “mismatch” in the determination step, the control means stores the inspection address as a failure address in the failure address storage means. The failure detection method of the semiconductor device as described. Further comprising an inspection step comprising the inspection writing step, the inspection reading step, and the determination step;
The test data held in the test data holding means is
A pair of test data each having a predetermined bit pattern and its bit inversion pattern,
13. The failure of a semiconductor device according to claim 12, wherein the inspection step is repeated using the pair of test data sequentially selected by the control means, and the inspection address of the nonvolatile memory cell is inspected for failure. Detection method. The test data is
13. The method of detecting a failure in a semiconductor device according to claim 12, comprising a bit pattern in which “0” and “1” are alternately arranged.

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