CN114512171A - Memory storage device and operation method thereof - Google Patents
Memory storage device and operation method thereof Download PDFInfo
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- CN114512171A CN114512171A CN202011287061.2A CN202011287061A CN114512171A CN 114512171 A CN114512171 A CN 114512171A CN 202011287061 A CN202011287061 A CN 202011287061A CN 114512171 A CN114512171 A CN 114512171A
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- 230000005055 memory storage Effects 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000003745 diagnosis Methods 0.000 claims description 9
- 238000012795 verification Methods 0.000 claims description 7
- 230000002950 deficient Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000001351 cycling effect Effects 0.000 description 3
- 238000011017 operating method Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/835—Masking faults in memories by using spares or by reconfiguring using programmable devices with roll call arrangements for redundant substitutions
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
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Abstract
The invention provides a memory storage device and an operation method thereof. The memory cell array includes a plurality of regular memory blocks and a plurality of spare memory blocks. The spare fuse circuit includes a plurality of fuse sets recording a plurality of repair information. Each repair information is associated with a corresponding one of the spare memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory control circuit includes a plurality of judgment circuits. Each judgment circuit generates a hit signal according to the operation address, the repair address, the first enable bit and the second enable bit. When the target memory block is bad, the judgment circuit of the memory control circuit generates a hit signal, and the memory control circuit disables the bad spare memory block according to the hit signal.
Description
Technical Field
The present invention relates to electronic devices and methods, and more particularly, to a memory storage device and a method for operating the same.
Background
For an internal memory storage device, a cycling operation includes an erase operation and a program operation. Memory cells are often susceptible to degradation over multiple cycling operations, such as the reliability of the memory blocks may decrease, or the erase and program times may increase, i.e., the operating speed may slow. In addition, after many cycles, some of the bits in the cell may be out of specification due to premature wear. For example, in flash memory, cycling tends to create interface states at its drain junction and oxide traps at its tunnel oxide layer. However, these worn bits are difficult to cull out during the test phase, and for this reason, the prior art uses error correction codes to correct these damaged bits. However, this method causes other problems such as an increase in the size of the chip size, a decrease in the operating speed, or an increase in power consumption.
Disclosure of Invention
The invention provides a memory storage device and an operation method thereof, which can improve the reliability and the operation speed.
The memory storage device of the invention comprises a memory cell array, a spare fuse circuit and a memory control circuit. The memory cell array includes a plurality of normal memory blocks and a plurality of spare memory blocks. The regular memory blocks are used for storing data. The spare fuse circuit includes a plurality of fuse sets for recording a plurality of repair information. Each repair message is associated with one of the spare memory blocks. Each repair information includes a repair address, a first enable bit, and a second enable bit. The repair address indicates the location of the regular memory block to be replaced by the associated spare memory block. The first enable bit is used for recording the use state of the corresponding fuse set. The second enable bit is used to enable the corresponding spare memory block. The memory control circuit is coupled to the memory cell array and the spare fuse circuit. The memory control circuit is used for operating the target memory block according to the operation address and judging whether the target memory block is bad or not. The memory control circuit comprises a plurality of judgment circuits, and each judgment circuit generates a hit signal according to the operation address, the repair address, the first enable bit and the second enable bit. When the target memory block is bad, the judging circuit generates a hit signal, and the memory control circuit disables the bad spare memory block according to the hit signal.
The operation method of the memory device is suitable for the memory storage device comprising a plurality of normal memory blocks and a plurality of spare memory blocks. The operation method comprises the following steps: recording a plurality of repair information as described above; operating the target memory block according to the operation address and judging whether the target memory block is bad; when the target memory block is bad, generating a hit signal according to the operation address, the repair address, the first enable bit and the second enable bit; and disabling the bad spare memory block according to the hit signal.
Based on the above, after determining that the target memory block is bad, the memory control circuit of the invention generates a hit signal according to the operation address, the repair address, the first enable bit and the second enable bit, and disables the bad spare memory block according to the hit signal. Therefore, the operation speed and the reliability of the memory block are improved.
Drawings
Fig. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention;
FIG. 2 is an internal block diagram of the memory storage device of the embodiment of FIG. 1;
FIG. 3 shows an example of a configuration of repair information according to an embodiment of the invention;
FIG. 4 is an internal schematic diagram of a CAM circuit according to an embodiment of the invention;
FIG. 5 is a flowchart illustrating steps of a method of operating a memory storage device according to an embodiment of the invention;
FIG. 6 is a flowchart illustrating steps of a method of operating a memory storage device according to an embodiment of the invention;
FIG. 7 is a flowchart illustrating steps of a method of operating a memory storage device according to another embodiment of the invention;
fig. 8 is a flowchart illustrating a method of operating a memory storage device according to another embodiment of the invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. Fig. 2 is an internal block diagram of the memory storage device according to the embodiment of fig. 1. Referring to fig. 1 and 2, the memory storage device 100 includes a memory cell array 110, a redundant fuse (redundant fuse) circuit 120, and a memory control circuit 130. The memory control circuit 130 is coupled to the memory cell array 110 and the redundancy fuse circuit 120. The Memory storage device 100 may be a non-volatile Memory device such as a flash Memory, or a volatile Memory device such as a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM), and those skilled in the art may adopt an appropriate structure according to their actual requirements.
The memory cell array 110 includes a plurality of normal memory blocks 112_0 to 112_ N and a plurality of spare memory blocks 114_0 to 114_ M. The memory blocks 112_0 to 112_ N are used for storing data. N and M are each positive integers greater than 0, and typically N is greater than M. In one embodiment, N is equal to 255 for example, and M is equal to 7 for example, which means that the memory cell array 110 includes 256 normal memory blocks and 8 spare memory blocks, and the number thereof is not limited to the invention.
The spare fuse circuit 120 is used for recording one or more repair information. Each repair message includes a repair address ADD _ R to replace the regular memory block with the spare memory block. Specifically, the spare fuse circuit 120 includes a plurality of sets of fuses. The fuse is, for example, a nonvolatile electronic fuse. The fuses may also be part of the memory cell array 110 when the memory cell array 110 is comprised of non-volatile memory cells. Each set of fuses may correspond to one of the spare memory blocks 114_0 to 114_ M and may record one repair information. For example, the user may perform a testing procedure (e.g., wafer probe, product test, system power on self test, etc.) on the memory cell array 110 in advance to detect bad regular memory blocks among the regular memory blocks 112_0 to 112_ N. Moreover, the user can program the spare fuse circuit 120 (e.g., blow the fuse with a high voltage) through the memory control circuit 130 or an external tester to record the address of the bad regular memory block as a repair address on a set of fuses of the spare fuse circuit 120. In the embodiment, the pre-erased spare memory blocks 114_0 to 114_ M are used to replace the regular memory blocks corresponding to the one or more repair addresses recorded in the spare fuse circuit 120.
The repair information recorded in the spare fuse circuit 120 may include a first enable bit B1 and a second enable bit B2 in addition to the repair address. For example, fig. 3 shows an example of a configuration manner of the repair information according to an embodiment of the invention. Referring to fig. 3, in this example, repair information 200 and 210 is recorded on two fuse sets of the spare fuse circuit 120, respectively. Each repair information 200 and 210 includes a repair address ADD _ R, a first enable bit B1, and a second enable bit B2. In the present embodiment, the fuse sets are illustrated as two, and the number thereof is not limited to the invention.
The fuse set recorded with the repair information 210 corresponds to the spare memory block 114_ X. That is, the spare memory block 114_ X may replace the regular memory block with the repair address ADD _ R in the repair information 210. The first enable bit B1 of the repair information 210 is used to record the usage status of the corresponding fuse set. The second enable bit B2 is used to enable the corresponding spare memory block 114_ X. For example, the initial states of the first enable bit B1 and the second enable bit B2 may both be at a high logic level, indicating that the fuse set of the repair information 210 has been used to replace a bad regular memory block with the spare memory block 114_ X when the first enable bit B1 is programmed to a low logic level and the second enable bit B2 is at a high logic level. When the first enable bit B1 of repair information 210 is at a high logic level, it indicates that its fuse set is unused (in a usable state). When the second enable bit B2 of the repair information 210 is programmed to a low logic level, it indicates that the corresponding spare memory block 114_ X is disabled by being detected as bad. In the present embodiment, X is an integer greater than or equal to 0 and less than or equal to M, and the operation of the first enable bits B1 and B2 will be described in more detail in the following embodiments.
The memory control circuit 130 is coupled to the memory cell array 110 and the redundancy fuse circuit 120. As shown in fig. 2, the memory control circuit 130 includes a controller circuit 132, a Content Addressable Memory (CAM) circuit 134, a row decoder 136, and a column decoder 138. In one embodiment, the memory control circuit 130 may include other suitable circuits for cooperatively controlling data access, such as a Power On Reset (POR) circuit, a status register, a high voltage generator, a page address latch/counter, a byte address latch/counter, and the like, which are not limited in the present invention. In the embodiment of the present invention, the various circuits in the memory control circuit 130 can be respectively implemented by any suitable circuit structure in the technical field, and the present invention is not limited thereto.
In the present embodiment, the memory control circuit 130 is used to control the overall operations of the memory storage device 100, such as erase operation, soft program (soft program) operation, and diagnostic operation for memory blocks, so as to access the data stored in the memory blocks. For example, the controller circuit 132 may control the column decoder 136 and the row decoder 138 according to the operation address ADD _ O to select a memory block of data to be accessed and operate on the memory block.
In addition, the controller circuit 132 is coupled to the content addressable memory circuit 134. During a power up procedure, the controller circuit 132 loads repair information (e.g., repair information 200 and 210) recorded by the spare fuse circuit 120 into the CAM 134.
The CAM circuit 134 is configured to determine whether the operation address ADD _ O is the same as any one of the repair addresses (e.g., the repair address ADD _ R of the repair information 200 or 210) in the spare fuse circuit 120, determine whether the corresponding fuse set is used according to the first enable bit B1 in the corresponding repair information, and determine whether the corresponding spare memory block is enabled according to the second enable bit B2. The CAM circuitry 134 may generate a hit signal according to the determination.
For example, fig. 4 is a schematic diagram of an embodiment of a content addressable memory circuit. Referring to fig. 4, the content addressable memory circuit 134 includes a plurality of latches 300 and a plurality of judgment circuits. For simplicity and clarity of illustration, fig. 4 illustrates only one latch 300 of the CAM 134, and the associated fuse set 120 and judgment circuit. Each latch 300 may load repair information from one of the fuse sets of spare fuse circuit 120. Next, the controller circuit 132 determines whether there is an available fuse set for the spare fuse circuit 120. For example, the controller circuit 132 may determine whether any of the first enable bits B1 latched by the latches 300 is at a high logic level, and when any of the first enable bits B1 is at a high logic level), the controller circuit 132 determines that there is a fuse set available in the spare fuse circuit 120. When the controller circuit 132 determines that the spare fuse circuit 120 has available fuse sets, the CAM circuit 134 may determine whether the operation address ADD _ O obtained from the controller circuit 132 is the same as the repair address ADD _ R in the repair information by using each of the determination circuits, determine whether the corresponding fuse set is used according to the first enable bit B1 in the corresponding repair information, and determine whether the corresponding spare memory block is enabled according to the second enable bit B2. When the determining circuit determines that the operation address ADD _ O obtained from the controller circuit 132 is the same as the repair address ADD _ R, determines that the corresponding fuse set is used (e.g., the first enable bit B1 is at a low logic level), and determines that the corresponding spare memory block is enabled (e.g., the second enable bit B2 is at a high logic level), the determining circuit may generate the hit signal HT at a high logic level. The hit signal HT at a high logic level is used to change the logic state of the second enable bit B2 in the corresponding repair information, such as to program the second enable bit B2 to a low logic level, thereby disabling the corresponding spare memory block and enabling another spare memory block. The details will be described later. In the present embodiment, the determining circuit includes a plurality of exclusive nor gates 310, an inverter 320, and an and gate 330. Each latch 300 supplies a plurality of bits of the repair address ADD _ R in the repair information to the input terminals of the exclusive or gates 310, respectively, to be compared with a plurality of bits of the operation address ADD _ O, respectively. In addition, each latch 300 may provide the first enable bit B1 in the repair information to the input of the inverter 320 and the second enable bit B2 in the repair information to the input of the AND gate 330. The AND gate 330 receives the outputs of the XNOR gate 310 and the inverter 320 and the second enable bit B2 for performing a logical AND operation, and outputs the result as the hit signal HT.
Accordingly, the CAM circuit 134 loads the repair information from the fuse redundancy circuit 120 and compares the repair information to generate the corresponding hit signal HT. Those skilled in the art should appreciate the practical needs and analogy with the teaching of the embodiments of the present invention. In one embodiment, an OR gate may be utilized within the content addressable memory circuit 134 to receive all of the hit signals and generate a total hit signal. The hit total signal may be used to disable the normal memory block.
Fig. 5 is a flowchart illustrating a method of operating a memory storage device according to an embodiment of the invention. The operation method of the present embodiment is applicable to a flash memory, for example. Referring to fig. 2, fig. 3 and fig. 5, the following describes steps of the operating method of the present invention with various components in the memory storage device 100.
In step S100, the spare fuse circuit 120 records one or more repair messages (e.g., repair messages 200 and 210). Each repair message includes a repair address ADD _ R of the normal memory block to be replaced by the coupled spare memory block. For example, the repair information 210 includes a repair address ADD _ R to replace the normal memory block with the spare memory block 114_ X.
In step S110, the memory control circuit 130 (the controller circuit 132) operates the target memory block 116 according to the operation address ADD _ O and determines whether the target memory block 116 is bad. In the present embodiment, the target memory block 116 is a spare memory block 114_ X or a regular memory block 112_ Y. In the case where the repair address ADD _ R identical to the operation address ADD _ O is recorded in the current spare fuse circuit 120, it indicates that the spare memory block 114_ X has replaced the bad regular memory block, and the target memory block 116 at this time is the spare memory block 114_ X among the spare memory blocks 114_0 to 114_ M. In the case where any repair address ADD _ R identical to the operation address ADD _ O is not recorded in the current spare fuse circuit 120, the target memory block 116 is the normal memory block 112_ Y among the spare memory blocks 112_0 to 112_ N. In the present embodiment, Y is an integer greater than or equal to 0 and less than or equal to N.
Step S110 includes steps S112 and S114. In step S112, after receiving the instruction to erase the block at the operation address ADD _ O, the memory control circuit 130 (the controller circuit 132) performs an erase operation on the target memory block 116 according to the operation address ADD _ O and records the erase retry value α of the target memory block 116.
In step S114, the memory control circuit 130 (the controller circuit 132) determines whether the erase retry value α exceeds the first threshold T1. If the memory control circuit 130 determines that the erase retry value α does not exceed the first threshold T1, the memory control circuit 130 determines that the target memory block 116 is not bad and proceeds to step S120.
In step S120, the memory control circuit 130 completes the erase operation of the target memory block 116. Specifically, the controller circuit 132 applies erase pulses to the target memory blocks 116 to erase the data stored therein.
In step S130, the memory control circuit 130 (the controller circuit 132) determines whether the target memory block 116 passes the erase verification. In the present embodiment, if the target memory block 116 passes the erase verification, the controller circuit 132 ends the erase operation. If the target memory block 116 fails erase verification, the controller circuit 132 executes step S110 to determine whether the retry erase value α of the target memory block 116 exceeds the first threshold T1 again.
Returning to step S114, if the memory control circuit 130 determines that the erasure retry value α exceeds the first threshold T1, the memory control circuit 130 determines that the target memory block 116 is bad, and proceeds to step S140. In step S140, the memory control circuit 130 determines whether the operation address ADD _ O matches any of the repair addresses ADD _ R in the spare fuse circuit 120, and disables the defective spare memory block accordingly.
The detailed operation of step S140 is illustrated below. Fig. 6 is a flowchart illustrating a method of operating a memory storage device according to an embodiment of the invention. The operation method of the present embodiment may be included in step S140 of fig. 5. Referring to fig. 2, fig. 3 and fig. 6, the following describes steps of the operating method of the present invention with various components in the memory storage device 100.
In step S200, the memory control circuit 130 (controller circuit 132) determines whether there is an available fuse in the spare fuse circuit 120. Specifically, the controller circuit 132 may, for example, check whether any of the first enable bits B1 in the CAM circuits 134 represents a high logic level to determine whether there are any more available fuse sets.
If the memory control circuit 130 determines that the spare fuse circuit 120 does not have a fuse available, the operation is terminated.
If the memory control circuit 130 determines that the spare fuse circuit 120 has available fuses, in step S210, the content addressable memory circuit 134 determines whether the operation address ADD _ O is the same as any repair address ADD _ R in the spare fuse circuit 120, determines whether the corresponding fuse set is used according to the first enable bit B1 in the corresponding repair information, and determines whether the corresponding spare memory block is enabled according to the second enable bit B2. The details are as described above for the embodiment of fig. 4, and are not repeated herein.
If the CAM 134 determines that the operation address ADD _ O is the same as the repair address ADD _ R of the repair information 210, determines that the corresponding fuse set is used, and determines that the corresponding spare memory block is enabled, in step S220, the CAM 134 generates a hit signal indicating that the target memory block 116 that is currently operated according to the operation address ADD _ O and determined to be bad is the spare memory block 114_ X.
Next, in step S230, when the hit signal is generated, the controller circuit 132 changes the logic level of the recorded second enable bit B2 corresponding to the matched repair address ADD _ R to disable the corresponding spare memory block 114_ X. Specifically, the controller circuit 132 receives the hit signal from the CAM circuit 134, determines the corresponding fuse set 120 according to the address of the signal line from which the hit signal is sent, and programs the second enable bit B2 in the corresponding fuse set 120 to a low logic level to disable the spare memory block 114_ X corresponding to the corresponding repair information 210.
In step S240, the memory control circuit 132 records the new repair information in the available fuse set of the spare fuse circuit 120, so as to replace the target memory block 116 with the spare memory block corresponding to the available fuse set recorded with the new repair information. Specifically, the memory control circuit 132 may select one of the available fuse sets of the spare fuse circuit 120, record (program) the matched repair address ADD _ R in the selected available fuse set, and program the first enable bit B1 of the selected available fuse set to a low logic level. Thus, memory control circuit 132 may replace target memory block 116, which is disabled spare memory block 114_ X, with another pre-erased spare memory block.
Referring back to step S210, if the CAM 134 determines that the operation address ADD _ O is different from the repair address ADD _ R of the repair information 210 or that the logic states of the first enable bit B1 and the second enable bit B2 in the corresponding repair information are the same, the CAM 134 does not generate the high logic hit HT and proceeds to step S240. In detail, in step S210, if the content addressable memory circuit 134 determines that the operation address ADD _ O is different from the repair addresses ADD _ R of all the repair information 210, it indicates that the target memory block 116 currently operated according to the operation address ADD _ O is a bad regular memory block 112_ Y, but no repair information 210 equal to the operation address ADD _ O is recorded in the spare fuse circuit 120. Accordingly, the process proceeds to step S240. In step S210, if the content addressable memory circuit 134 determines that the operation address ADD _ O is the same as the repair address ADD _ R of any one of the repair messages 210, but the logic states of the first enable bit B1 and the second enable bit B2 in all the repair messages are the initial states, which indicates that the target memory block 116 currently operated according to the operation address ADD _ O is a bad normal memory block 112_ Y, but any spare memory block is not enabled to replace the bad memory normal block 112_ Y. Accordingly, the memory control circuit 132 programs the first enable bit B1 corresponding to the matched repair address ADD _ R to a low logic level to enable the corresponding spare memory block to replace the bad normal memory block 112_ Y (step S212).
In step S240, the memory control circuit 132 may create new repair information and record it in the spare fuse circuit 120. Thus, the memory control circuit 132 may replace the target memory block 116, which is a bad regular memory block 112_ Y, with another pre-erased spare memory block.
By the above-described operation method of the memory storage device, the memory control circuit 130 can disable the spare memory block 114_ X determined to be bad. Also, during the time interval of the erase operation specification, the memory control circuit 130 can replace the disabled spare memory block 114_ X with another spare memory block that is pre-erased. Therefore, the reliability and the operation speed of the memory block can be improved.
Fig. 7 is a flowchart illustrating a method of operating a memory storage device according to another embodiment of the invention. The operation method of the present embodiment is suitable for a memory device configured by a flash memory, for example. Referring to fig. 2, fig. 3 and fig. 7, the operation method of the flash memory device of the present embodiment is similar to the embodiment of fig. 5, and the main difference between the two embodiments is, for example, that the operation method of the embodiment of fig. 7 further determines whether the target memory block 116 is bad according to whether the soft program retry value β exceeds the second threshold T2. Therefore, in the present embodiment, the two parameter values for determining whether the target memory block 116 is bad include the erase retry value α and the soft program retry value β.
Specifically, in step S330, if the target memory block 116 passes the erase verification, the process proceeds to step S340.
In step S340, the memory control circuit 130 (the controller circuit 132) operates the target memory block 116 according to the operation address ADD _ O and determines whether the target memory block 116 is bad.
Step S340 includes steps S342 and S344. In step S342, after receiving the instruction to soft program the block of the operation address ADD _ O, the controller circuit 132 performs the soft program operation on the target memory block 116 according to the operation address ADD _ O and records the soft program retry value β of the target memory block 116.
In step S344, the memory control circuit 130 (the controller circuit 132) determines whether the soft programming retry value β exceeds the second threshold value T2. If the memory control circuit 130 determines that the retry value β does not exceed the second threshold T2, the memory control circuit 130 determines that the target memory block 116 is not bad and proceeds to step S350.
In step S350, the memory control circuit 130 (the controller circuit 132) completes the programming operation of the target memory block 116. The soft programming operation is, for example, to apply a soft programming voltage to the word lines in the block that is less than the voltage applied during normal programming, thereby providing a driving force for injecting charge into the memory cells to shift the threshold voltage toward the positive direction. Soft programming voltages are lower than typical programming voltages, making it relatively easier to inject charge into memory cells that are over-erased, and harder to inject charge into memory cells that have a threshold voltage near the upper limit. The soft programming operation of the present embodiment may be taught, suggested, and embodied sufficiently by one of ordinary skill in the art.
In step S360, the memory control circuit 130 (the controller circuit 132) determines whether the target memory block 116 passes the soft program verification. In the present embodiment, if the target memory block 116 passes the soft program verification, the controller circuit 132 ends the soft program operation. If the target memory block 116 fails the soft program verification, the controller circuit 132 executes step S340 to determine whether the retry value β of the target memory block 116 exceeds the second threshold T2 again.
Returning to step S344, if the memory control circuit 130 determines that the retry value β exceeds the second threshold T2, the memory control circuit 130 determines that the target memory block 116 is bad, and proceeds to step S370. In step S370, the memory control circuit 130 determines whether the operation address ADD _ O matches any of the repair addresses ADD _ R in the spare fuse circuits 120, and disables the defective spare memory blocks accordingly.
In addition, steps S300, S310, S312, S314, S320, S330 and S370 in the embodiment of the present invention are respectively the same as or similar to steps S100, S110, S112, S114, S120, S130 and S140 in the previous embodiment, and thus the detailed contents thereof are not repeated herein.
By the above-described operation method of the memory storage device, the memory control circuit 130 can disable the spare memory block 114_ X determined to be bad. Also, during the time interval of the erase operation or soft programming operation specification, the memory control circuit 130 can replace the disabled spare memory block 114_ X with another spare memory block that is pre-erased. Therefore, the reliability and the operation speed of the memory block can be improved.
Fig. 8 is a flowchart illustrating a method of operating a memory storage device according to another embodiment of the invention. Different from the foregoing embodiments, the operation method of the present embodiment is suitable for a storage device formed by volatile memory elements such as a dynamic random access memory and a static random access memory. Referring to fig. 2, fig. 3 and fig. 8, the following describes steps of the operating method of the present invention with various components in the memory storage device 100.
In step S400, the spare fuse circuit 120 records one or more repair messages (e.g., repair messages 200 and 210). Each repair information 200 and 210 includes a repair address ADD _ R.
In step S410, the memory control circuit 130 operates the target memory block 116 according to the operation address ADD _ O and determines whether the target memory block 116 is bad.
Step S410 includes steps S412 and S414. In step S412, after receiving the instruction to diagnose the block of the operation address ADD _ O, the memory control circuit 130 (the controller circuit 132) performs a diagnosis operation on the target memory block 116 according to the operation address ADD _ O. In the present embodiment, the diagnosis operation may determine whether the target memory block 116 is bad, for example, which may be sufficient to obtain sufficient teaching, suggestion and implementation descriptions from the general knowledge in the technical field.
In step S414, the memory control circuit 130 determines whether the target memory block 116 is bad according to the result of the diagnosis operation. If the memory control circuit 130 determines that the target memory block 116 is bad, the process proceeds to step S440. The step S440 is the same as or similar to the step S140 of the previous embodiment, and therefore the detailed description thereof is omitted here.
If the memory control circuit 130 determines that the target memory block 116 is not bad, the process proceeds to step S420. In step S420, the memory control circuit 130 (the controller circuit 132) increments the operation address ADD _ O.
Next, in step S430, the memory control circuit 130 (the controller circuit 132) determines whether the incremented operation address ADD _ O exceeds the address threshold γ. In the present embodiment, if the controller circuit 132 determines that the incremented operation address ADD _ O exceeds the address threshold γ, the controller circuit 132 ends the diagnostic operation. If the controller circuit 132 determines that the incremented operation address ADD _ O does not exceed the address threshold γ, the controller circuit 132 executes step S410 to determine whether the target memory block 116 operated according to the incremented operation address ADD _ O is bad again.
In summary, the memory control circuit of the present invention further determines whether the current operating address matches any of the repair addresses recorded in the spare fuse circuit after determining that the target memory block is defective. Therefore, the memory control circuit of the present invention can find out the bad regular memory block, and can also find out the bad spare memory block and disable the bad spare memory block, so as to improve the operation speed and reliability of the memory block.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (18)
1. A memory storage device, comprising:
a memory cell array including a plurality of regular memory blocks configured to store data and a plurality of spare memory blocks;
a spare fuse circuit comprising a plurality of fuse sets configured to record a plurality of repair information, wherein each of the repair information is associated with a corresponding one of the plurality of spare memory blocks, and each of the repair information comprises:
a repair address configured to indicate a location of the regular memory block to be replaced by the associated spare memory block;
a first enable bit configured to record a use state of a corresponding one of the plurality of fuse sets; and
a second enable bit configured to enable a corresponding one of the plurality of spare memory blocks; and
a memory control circuit coupled to the memory cell array and the spare fuse circuit, and configured to operate a target memory block according to an operation address and determine whether the target memory block is defective, the memory control circuit including a plurality of determination circuits, each of the determination circuits generating a hit signal according to the operation address, the repair address, the first enable bit, and the second enable bit,
when the target memory block is bad, the judging circuit of the memory control circuit generates the hit signal, and the memory control circuit disables the bad spare memory block according to the hit signal.
2. The memory storage device of claim 1, wherein the memory control circuit determines whether an available fuse set exists in the plurality of fuse sets according to the first enable bit when the target memory block is bad, and the memory control circuit records new repair information in the spare fuse circuit after the hit signal is generated to replace the target memory block with the spare memory block associated with the new repair information when the available fuse set exists in the spare fuse circuit.
3. The memory storage device of claim 2, wherein the memory control circuitry comprises:
a content addressable memory circuit including the plurality of judgment circuits and a plurality of latches respectively coupled to the plurality of judgment circuits, wherein the plurality of latches are configured to load the plurality of repair information from the spare fuse circuit, each of the plurality of judgment circuits is configured to generate the hit signal when it is judged that the operation address is the same as any one of the repair addresses in the spare fuse circuit, a corresponding one of the plurality of fuse sets has been used, and a corresponding one of the plurality of spare memory blocks is enabled; and
a controller circuit, coupled to the CAM circuit, configured to provide the operation address to the CAM circuit, and change a logic level of the second enable bit in the repair information corresponding to the repair address recorded by the spare fuse circuit, which is the same as the operation address, according to the hit signal, so as to disable the corresponding spare memory block.
4. The memory storage device of claim 3 wherein during power up, the controller circuit loads the plurality of repair information from the spare fuse circuit into the plurality of latches of the content addressable memory circuit.
5. The memory storage device of claim 1, wherein each of the decision circuits comprises:
a plurality of exclusive-OR gates configured to compare the operation address with the repair address;
an inverter configured to receive the first enable bit and output an inverted value of the first enable bit; and
an AND gate configured to receive outputs of the plurality of XNOR gates, an inverted value of the first enable bit, and the second enable bit, and generate the hit signal.
6. The memory storage device according to claim 1, wherein the memory control circuit performs a diagnosis operation on the target memory block according to the operation address, determines whether the target memory block is defective according to a result of the diagnosis operation, and increments the operation address to perform the diagnosis operation on a next memory block if the target memory block is not defective.
7. The memory storage device of claim 1, wherein the memory control circuit performs an erase operation on the target memory block according to the operation address and records an erase retry value of the target memory block, the memory control circuit determines whether the erase retry value exceeds a first threshold, and if the erase retry value exceeds the first threshold, the memory control circuit determines that the target memory block is bad.
8. The memory storage device of claim 7, wherein if the erasure retry value does not exceed the first threshold, the memory control circuitry completes the erase operation of the target memory block and determines whether the target memory block passes erase verification.
9. The memory storage device of claim 7 wherein the memory control circuitry further performs a soft programming operation on the target memory block according to the operation address and records a soft programming retry value of the target memory block, the memory control circuitry determines whether the soft programming retry value exceeds a second threshold, and the memory control circuitry determines that the target memory block is bad if the soft programming retry value exceeds the second threshold.
10. The memory storage device of claim 9, wherein if the erasure retry value does not exceed the second threshold, the memory control circuit completes the soft programming operation of the target memory block and determines whether the target memory block passes soft program verification.
11. An operation method of a memory storage device, wherein the memory storage device comprises a plurality of normal memory blocks and a plurality of spare memory blocks, and the plurality of memory blocks are used for storing data, the operation method comprises the following steps:
recording a plurality of repair information, wherein each repair information is associated with one of the plurality of spare memory blocks, and each repair information comprises:
a repair address configured to indicate a location of the regular memory block to be replaced by the associated spare memory block;
a first enable bit configured to record a use state of a fuse among the spare fuse circuits; and
a second enable bit configured to enable the spare memory block;
operating a target memory block according to an operation address, and judging whether the target memory block is bad or not;
when the target memory block is bad, generating a hit signal according to the operation address, the repair address, the first enable bit and the second enable bit; and
disabling the bad spare memory block according to the hit signal.
12. The method of operation of a memory storage device of claim 11, further comprising:
before generating the hit signal, judging whether an available fuse set exists in the plurality of fuse sets according to the first enable bit.
13. The method of operation of a memory storage device of claim 12, further comprising:
when the spare fuse circuit has the available fuse set, after disabling the bad spare memory block, the memory control circuit records new repair information in the spare fuse circuit to replace the target memory block with the spare memory block associated with the new repair information.
14. The method of claim 11, wherein generating the hit signal comprises:
determining whether the operation address is the same as any of the recorded repair addresses, determining whether a corresponding one of the plurality of fuse sets has been used according to the first enable bit in the repair information corresponding to the repair address that is the same as the operation address, and determining whether the corresponding one of the plurality of spare memory blocks is enabled according to the second enable bit; and
generating the hit signal when the operation address is the same as the recorded repair address, a corresponding one of the plurality of fuse sets has been used, and a corresponding one of the plurality of spare memory blocks is enabled,
wherein disabling the bad spare memory block according to the hit signal comprises: when the hit signal is generated, changing a logic level of the second enable bit in the repair information corresponding to the repair address which is recorded to be the same as the operation address to disable the corresponding spare memory block.
15. The method of claim 11, wherein generating the hit signal comprises:
comparing the operation address with the repair address through a plurality of exclusive-nor gates;
receiving the first enable bit through an inverter and outputting an inverted value of the first enable bit; and
and receiving the outputs of the plurality of exclusive OR gates, the inverted value of the first enable bit and the second enable bit through an AND gate, and generating the hit signal.
16. The method of claim 11, wherein the target memory block is operated according to the operation address, and the step of determining whether the target memory block is bad comprises:
performing diagnosis operation on the target memory block according to the operation address; and
judging whether the target memory block is bad according to the result of the diagnosis operation,
wherein the method of operation further comprises:
and if the target memory block is not bad, incrementing the operation address to perform the diagnosis operation on the next memory block.
17. The method of claim 11, wherein the target memory block is operated according to the operation address, and the step of determining whether the target memory block is bad comprises:
performing an erasing operation on the target memory block according to the operation address, and recording an erasing retry value of the target memory block;
judging whether the erasing retry value exceeds a first critical value;
if the retry erasure value exceeds the first critical value, determining that the target memory block is bad; and
if the retry erasure value does not exceed the first threshold, the erasure operation of the target memory block is completed, and whether the target memory block passes the erasure verification is determined.
18. The method of claim 17, wherein the target memory block is operated according to the operation address, and the step of determining whether the target memory block is bad further comprises:
performing soft programming operation on the target memory block according to the operation address, and recording a soft programming retry value of the target memory block;
judging whether the soft programming retry value exceeds a second critical value;
if the soft programming retry value exceeds the second critical value, determining that the target memory block is bad; and
if the retry erasure value does not exceed the second threshold, completing the soft programming operation of the target memory block, and determining whether the target memory block passes soft programming verification.
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