KR20140131207A - Semiconductor memory device having fuse programming circuit and fuse programming method therefore - Google Patents

Abstract

Disclosed is a semiconductor memory device which programs a fail address in a fuse array and, when another fail address is generated, retrieves unused fuses without relying on previous repair information to program. The semiconductor memory device comprises: a fuse array having a plurality of fuses to program a fail address for memory cell repair; and a fuse programming circuit which retrieves idle fuses in a fuse array and programs another fail address generated additionally.

Description

[0001] The present invention relates to a semiconductor memory device having a fuse programming circuit and a fuse programming method therefor,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory field, and more particularly, to a semiconductor memory device having a fuse programming circuit and a fuse programming method therefor.

If any one of a large number of memory cells in a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as "DRAM") is defective, the semiconductor memory device does not perform the desired function properly and is processed as a defective product. However, when a defect occurs in a small number of memory cells, it is inefficient in terms of yield to discard the semiconductor memory device as a defective product.

Therefore, when a defective cell among the memory cells in the memory device is provided, a redundant memory cell is provided in the semiconductor memory device, and these defective memory cells are replaced with redundant memory cells, . Thus, an improvement in the yield can be achieved.

A repair operation of a semiconductor memory device using a redundancy memory cell is to replace a defective memory cell with a spare memory cell in a row / column basis. When the defective memory cell is found through the test after the wafer is processed, fail address programming is performed to program the corresponding address through a fuse or the like. Therefore, when an address indicating a defective word line is input during repair in a row unit, the defective word line is replaced with a spare word line by the fail address program.

Fail address programming can often be performed through a fuse, such as an anti-fuse. The fail address can be programmed by raising the anti-fuse in the fuse array upon occurrence of a fail address for memory cell repair.

Failed address programming for repairing defective memory cells in the test operation when the memory cells are found to be defective is performed by ramping up the anti-fuses. After the fail address programming is performed once, defective memory cells may newly exist in a subsequent test process or after the product shipment.

In this way, when a new fail address is additionally generated, the fail address programming needs to be performed additionally. When fail address programming is additionally performed, the anti-fuse used in the previous fail address program must be excluded from the new program. Therefore, it is usually necessary to know the previous repair information beforehand so that the program can be further executed to the unused anti-fuses that have not participated in the previous fail address program.

Dependent upon previous repair information, once the fail address has been programmed into the fuse array and another fail address has been additionally generated, requires creation and securing of a database for previous repair information. Also, an increase in test time and test steps for the repair operation may occur.

An object of the present invention is to provide a semiconductor memory device capable of finding an unused fuse in a previous program and programming an additional fail address irrespective of previous repair information even when a fail address is additionally generated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a system and method for automatically finding a redundancy resource and programming an additional fail address to idle fuses without having previous repair information upon the occurrence of an additional fail address once the fail address has been programmed A method for programming a fuse.

According to an aspect of the present invention, there is provided a semiconductor memory device including:

A fuse array having a plurality of fuses for causing a fail address for memory cell repair to be programmed; And

Wherein the failure address in the fuse array does not depend on previous repair information indicating position information of the programmed fuses when the fail address is once programmed into the fuse array and another fail address subsequently occurs, And a fuse programming circuit for searching for idle fuses in the fuse array and for programming the further generated fail address to the retrieved idle fuses.

According to an embodiment in accordance with the inventive concept, the fuse array may be an anti-fuse array comprising a plurality of anti-fuses.

According to an embodiment in accordance with the inventive concept, the fuse programming circuit comprises:

A fuse row decoder for selecting a row of said fuses;

A fuse column decoder for selecting a row of the fuses;

A fuse sensing unit for sensing the presence or absence of fusing of the fuses;

A determination circuit for searching for an idle fuse among the fuses in response to a fuse sensing signal of the fuse sensing unit; And

And a program controller coupled to the fuse row decoder, the fuse column decoder, and the decision circuit, for generally controlling the search of the idle fuses and the execution of the program of the idle fuses.

According to an embodiment in accordance with the inventive concept, the fuse column decoder comprises:

According to the control of the program controller, the scan operation of the idle fuses may apply a scanning voltage to a selected column of the fuses.

According to an embodiment in accordance with the inventive concept, the fuse column decoder comprises:

According to the control of the program controller, the program operation of the idle fuses may apply a rupture voltage to a selected column of the idle fuses.

According to an embodiment in accordance with the inventive concept, the fuse row decoder comprises:

In the search of the idle fuses, an enable signal is received from the program controller, and when the idle fuses are searched, a hold signal may be received.

According to an embodiment in accordance with the inventive concept, the program controller may be enabled if the further fail address is further generated.

According to another aspect of the present invention, there is provided a semiconductor memory device including:

A memory cell array including a plurality of memory cells;

An anti-fuse array having a plurality of anti-fuses for causing a fail address for memory cell repair of the memory cell array to be programmed; And

Wherein, after the fail address is once programmed into the anti-fuse array by causing some anti-fuses of the anti-fuses to be programmed, and further another fail address is generated, a previous repair And a fuse programming circuit that, without the need for information, retrieves idle anti-fuses among the anti-fuses and programs the further generated fail address to the retrieved idle anti-fuses.

According to an embodiment of the present invention, the memory cell array may include a spare cell block having a normal cell block having the plurality of memory cells and a plurality of spare memory cells for repairing the memory cells have.

According to an embodiment in accordance with the inventive concept, the fuse programming circuit comprises:

A fuse row decoder for selecting a row of said anti-fuses;

A fuse column decoder for selecting a row of the anti-fuses;

A fuse sensing unit for sensing the presence or absence of the anti-fuse;

A determination circuit for searching for an idle anti-fuse among the anti-fuses in response to a fuse sensing signal of the fuse sensing unit; And

And a program controller coupled to the fuse row decoder, the fuse column decoder, and the decision circuit, for generally controlling the search of the idle anti-fuses and the execution of the program of the idle anti-fuses.

According to an embodiment in accordance with the inventive concept, the fuse column decoder comprises:

According to the control of the program controller, in the search operation of the idle anti-fuses, a scanning voltage may be applied to a selected column of the anti-fuses.

According to an embodiment in accordance with the inventive concept, the fuse column decoder comprises:

According to the control of the program controller, the program operation of the idle anti-fuses may apply a rupture voltage to a selected column of the idle anti-fuses.

According to an embodiment in accordance with the inventive concept, the fuse row decoder comprises:

In the searching operation of the idle anti-fuses, an activation signal may be received from the program controller, and when the idle anti-fuses are detected, a hold signal may be received.

According to the embodiment of the present invention, when the another fail address is generated as N (N is a natural number equal to or greater than 2), the program controller determines that the program for the N other fail addresses is one command input And can be controlled to be performed.

According to still another aspect of the present invention, there is provided a method of programming a fuse,

Store the further fail address if, after a fail address has been programmed in the fuse array having a plurality of fuses for memory cell repair, another fail address is additionally generated;

Searching for idle fuses in the fuse array that are not used for programming the fail address in the fuse array without having previous repair information indicating position information of the fuses programmed within the fuse array;

If the idle fuses are searched, the stored idle fuses are programmed with another stored fail address.

According to an embodiment in accordance with the inventive concept, the further fail address may be temporarily stored in the fail address memory.

According to an embodiment in accordance with the inventive concept, the retrieved idle fuses may be unused or unfused unused fuses.

According to an embodiment in accordance with the inventive concept, the retrieved idle fuses may be anti-fuses that are routed by providing a program voltage.

According to an embodiment in accordance with the concept of the present invention, when the idle fuses are retrieved, the scanning operation for retrieval can be held for the fuse program at its retrieval location.

According to an embodiment of the present invention, the voltage applied to the row of the fuse array at the time of the search and the voltage applied to the row of the fuse array at the time of the program may be at different levels.

According to the embodiment of the present invention, when another fail address is additionally generated in N (N is a natural number of 2 or more), the program for the N other fail addresses is executed by receiving one command input .

According to the embodiment of the present invention, when the further fail address is additionally generated by N (N is a natural number of 2 or more), the program for the N other fail addresses receives N command inputs manually .

According to still another aspect of the present invention, there is provided an anti-

Receiving the further fail address when another fail address is additionally generated after a fail address for memory cell repair is programmed into the anti-fuse array by some of the plurality of anti-fuses being routed;

Searching for the unrestrained idle anti-fuses among the anti-fuses, without previous repair information indicating position information of the some anti-fuses ruptured;

In the case of retrieving the idle anti-fuses, the retrieved idle anti-fuses are roughed so that the stored another fail address is further programmed into the anti-fuse array.

According to an embodiment in accordance with the inventive concept, the search of the idle anti-

Selecting rows and columns of said anti-fuses;

And detecting the presence or absence of the anti-fuse in turn.

According to an embodiment in accordance with the inventive concept, the program of idle anti-

Selecting rows and columns of the idle anti-fuses among the anti-fuses;

And applying a program current to the selected idle anti-fuses. According to the embodiment of the present invention, when another fail address is additionally generated in N (N is a natural number of 2 or more), the program for the N other fail addresses receives the command input no more than 2 times .

According to the embodiment of the present invention, when the further fail address is additionally generated in N (N is a natural number of 2 or more), the program for the N other fail addresses is N or N or less And can be performed by receiving input.

According to an embodiment in accordance with the inventive concept, the search for the fuse programming and the program can be performed automatically in the DRAM at the further occurrence of the fail address.

According to an embodiment in accordance with the inventive concept, one fuse box line of the anti-fuse array can be composed of anti-fuses that are greater than the number of bits of the fail address.

According to an exemplary configuration of the present invention, it is possible to search for unused fuses in a previous repair in the fuse array and to program another fail address that has been generated, without relying on previous repair information. In addition, test time and test steps for repair work are shortened.

1 is a schematic block diagram of a semiconductor memory device according to the concept of the present invention;
Fig. 2 is a flow chart of operation control of the fuse programming circuit in Fig. 1; Fig.
3 is a specific block diagram of the fuse programming circuit of FIG.
FIG. 4 is an exemplary circuit diagram illustrating a fuse sensing operation of the fuse sensing unit in FIG. 3; FIG.
Figure 5 is an illustration of an anti-fuse circuit in the anti-fuse array of Figure 1;
6 is an operational timing diagram of the fuse programming circuit of Fig.
FIG. 7 is a circuit block diagram illustrating an exemplary low repair operation of FIG. 1; FIG.
FIG. 8 is a configuration example of an anti-fuse array showing an example in which an additional bit is included in the anti-fuse array of FIG. 3; FIG.
Figure 9 is an example configuration of an anti-fuse array showing an example of including additional bits in the anti-fuse array of Figure 3;
10 is a block diagram illustrating an application of the present invention applied to a memory system;
11 is a block diagram illustrating an application example of the present invention applied to a mobile device.
12 is a block diagram showing an application example of the present invention applied to an optical I / O schema;
13 is a block diagram illustrating an application of the present invention applied to a trough silicon via (TSV);
14 is a block diagram showing an application example of the present invention applied to an electronic system;
15 is a block diagram showing an application example of the present invention mounted on a semiconductor wafer;

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent from the following description of preferred embodiments with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, without intention other than to provide an understanding of the present invention.

In this specification, when it is mentioned that some element or lines are connected to a target element block, it also includes a direct connection as well as a meaning indirectly connected to the target element block via some other element.

In addition, the same or similar reference numerals shown in the drawings denote the same or similar components as possible. In some drawings, the connection relationship of elements and lines is shown for an effective explanation of the technical contents, and other elements or circuit blocks may be further provided.

Each embodiment described and exemplified herein may also include its complementary embodiment, and details regarding the basic data access operation and the anti-fuse program and repair operation for the DRAM are described in detail to avoid obscuring the gist of the present invention Please note that it is not.

1 is a schematic block diagram of a semiconductor memory device according to the concept of the present invention.

Referring to FIG. 1, a semiconductor memory device 100, such as a DRAM, may include a fuse programming circuit 200 and an anti-fuse array 300.

In order to perform a data read operation and a data write operation, the semiconductor memory device 100 may include a memory cell array including a plurality of memory cells.

The anti-fuse array 300 has a plurality of anti-fuses to allow a fail address for memory cell repair of the memory cell array to be programmed.

The fuse programming circuit 200 may be configured such that, after the fail address has been programmed into the anti-fuse array by some anti-fuses being routed, and another fail address is additionally generated, The unrepaired idle anti-fuses among the anti-fuses are searched without previous repair information indicating position information of the fuses. In addition, the fuse programming circuit 200 programs the another fail address to the retrieved idle anti-fuses.

After the programming is first performed using anti-fuses, a fail address may be further generated due to additional defects in the memory cell. In such a case, it becomes necessary to further program using the anti-fuse. When an additional program is executed, an unused idle redundancy anti-fuse must be found in the existing repair, so that the anti-fuse used in the previous program is prevented from being programmed. Therefore, when performing the additional program, previous repair information indicating the position information of the anti-fuses participating in the previous program has been required. To obtain the previous repair information, a database should be created and the created database should be managed.

However, the fuse programming circuit 200 of FIG. 1 has the capability to automatically detect idle anti-fuses that are not used in the previous program among the anti-fuses and to program the generated additional fail address to the detected idle anti-fuses . Thus, the need to secure previous repair information is eliminated.

In addition, N programs can be automatically executed even if a command is received at the time of re-program execution, and the programming time and the test step can be shortened.

FIG. 2 is a flowchart of operation control of the fuse programming circuit in FIG. 1; FIG.

Referring to FIG. 2, it is checked in step S10 whether or not a fail address is additionally generated. If the fuse programming circuit 200 is activated and receives the another fail address, it is recognized that there is an additional occurrence of the fail address, i.e., the occurrence of another fail address.

If a fail address is additionally generated, the fuse programming circuit 200 automatically scans the redundancy resource without previous repair information in step S20. Here, the redundancy resource means unused anti-fuses not participating in the previous program.

In step S30, it is checked whether the redundancy resource is searched. If the redundancy resource is searched, step S40 is performed.

In step S40, the fuse programming circuit 200 programs another fail address to the redundancy resource. That is, in step S40, the unused anti-fuses are spoiled. The search and the program can be performed at once if the fail address generated is N (N is a natural number of 2 or more).

3 is a specific block diagram of the fuse programming circuit of FIG.

3, the fuse programming circuit 200 includes a fuse row decoder 230, a fuse column decoder 220, a fuse sensing section 240, a decision circuit 250, and a program controller 210 .

The fuse row decoder 230 selects a row of anti-fuses in the anti-fuse array 300.

The fuse column decoder 220 selects a row of anti-fuses in the anti-fuse array 300.

The fuse sensing unit 240 senses whether or not the anti-fuses are turned off.

The determination circuit 250 searches for the idle anti-fuses among the anti-fuses in response to the fuse sensing signal of the fuse sensing unit 240.

The program controller 210 is coupled to the fuse row decoder 230, the fuse column decoder 220, and the decision circuit 250 and is operable to perform a search of the idle anti-fuses and a program execution of the idle anti- Overall control.

The anti-fuse array 300 includes a plurality of fuse box lines 300-1, 300-2, ..., 300-n. One fuse box line 300-1 can program one fail address.

For example, assume that the fuse box lines 300-1, 300-2, and 300-3 are all used in a previous repair operation. When the fail address is additionally generated, the semiconductor memory device 100 generates the enable signal (Enable). Accordingly, the program controller 210 is activated and receives a fail address (FA). The fail address (FA) is a fail address to be further programmed, which can be applied in a plurality of ways. The fail address (FA) is stored in the fail address memory of the program controller (210). The fail address memory may be a storage register.

The program controller 210 controls the operation of automatically scanning the redundancy resource without previous repair information. The fuse programming circuit 200 applies the enable signal EN to the fuse row decoder 230 via line L20 to search for unused antifuses that have not participated in the previous program. In addition, the fuse programming circuit 200 applies a scanning control signal SCS to the fuse column decoder 220 via a line L10. Accordingly, the switch SW10 of the fuse column decoder 220 applies the scan voltage SCA-V to the selected column of the anti-fuse array 300. [ In addition, the fuse row decoder 230 applies activation pulses, which sequentially activate the fuse box lines 300-1, 300-2, and 300-3 of the anti-fuse array 300, as shown in FIG.

6 is an operational timing diagram of the fuse programming circuit of Fig. In FIG. 6, the waveforms RDP0, R, ..., RDPn represent the activation pulses. It can be seen that the fuse box lines 300-1, 300-2, and 300-3 are sequentially activated as the waveforms RDP0, R, ..., RDPn are sequentially shifted.

Referring again to FIG. 3, the fuse sensing unit 240 sequentially senses the fuse box lines 300-1, 300-2, and 300-3 to detect whether or not the anti-fuses are deteriorated. The specific operation of the fuse sensing unit 240 will be described later with reference to FIG.

Since the fuse box lines 300-1, 300-2, and 300-3 are all used in the previous repair operation as a result of the sensing operation of the fuse sensing unit 240, the fuse sensing signals SA0, SA1, Are all output as a logic high signal. Therefore, the output (OUT) of the decision circuit 250, which appears through line L30, is also output as a search failure signal.

The fuse sensing unit 240 senses that the fuse box line 300-n has not been used in the previous repair operation as a result of sensing the fuse box line 300-n, Is outputted as a logic low signal, as shown in waveform SAn in the section T1 of Fig. Thus, the output OUT of the decision circuit 250, which appears through line L30, is output as a search success signal. Here, the search failure signal may be a logic low if the search success signal is logic high.

Upon successful detection, the program controller 210 outputs a hold signal (HOLD) requesting the fuse row decoder 230 to interrupt the scanning operation via the line L20. Accordingly, the fuse row decoder 230 holds the activated state of the fuse box line 300-n. Meanwhile, the program controller 210 deactivates the scanning control signal SCS through the line L10. Accordingly, the switch SW10 of the fuse column decoder 220 applies the rupture voltage RU-V for the program to the selected row of the anti-fuse array 300. [ The anti-fuses in the fuse box line 300-n are routed according to the fail address stored in the fail address memory. Eventually, after the unused fuses in the previous program are automatically searched, the stored fail address is programmed through the searched anti-fuses.

When the program for the fuse box line 300-n is completed, if another fail address remains in the fail address memory, the above-described scan operation and the above-described program operation are resumed.

As a result, the search and the program can be performed at once if the fail address generated is N (N is a natural number of 2 or more). However, this is merely an example, and a program operation may be performed manually by a user in units of one fail address.

4 is an exemplary circuit diagram for explaining a fuse sensing operation of the fuse sensing unit in FIG.

Referring to FIG. 4, the fuse sensing unit 240 is connected to the first program unit 300a and the second program unit 300b of the anti-fuse array 300. FIG.

4, the first program section 300a includes a first anti-fuse AF11 connected between the first voltage terminal VN11 and the output node N1 of the first signal CS1, The program section 300b includes an example in which the second anti-fuse AF12 is connected between the second voltage terminal VN12 and the output node N2 of the second signal CS2.

The first program unit 300a may include a first anti-fuse AF11, a first switching transistor TS11, and a first program transistor TP1. The first anti-fuse AF11 is connected to the first voltage terminal VN11 and the first switching transistor TS11 is connected between the second end of the first anti-fuse AF11 and the output of the first signal CS1 And is connected between the node N1. A sensing enable signal SEN is applied to the gate of the first switching transistor TS11. The first program transistor TP1 is connected between the second stage of the first anti-fuse AF11 and ground, and the program signal PGM is applied to the gate.

The second program section 300b may be implemented by including a second anti-fuse AF12, a second switching transistor TS12, and a second program transistor TP2. The second anti-fuse AF12 is connected to the second voltage terminal VN12 at its first end and the second switching transistor TS12 is connected to the output of the second end of the second anti-fuse AF12 and the output of the second signal CS2 Node N2. A sensing enable signal SEN is applied to the gate of the second switching transistor TS12. The second program transistor TP2 is connected between the second stage of the second anti-fuse AF12 and ground, and the program signal PGM is applied to the gate.

The fuse sensing unit 240 includes a first PMOS transistor PM11, a second PMOS transistor PM12, a third PMOS transistor PM13, a first NMOS transistor NM11, a second NMOS transistor NM12, and an inverter INV ). ≪ / RTI > Since the third PMOS transistor PM13 and the second NMOS transistor NM12 perform one inverter function, the fuse sensing unit 240 has a latch structure in which two inverters are interconnected. The second PMOS transistor PM12 and the first NMOS transistor NM11 are for setting the initial states of the first latch node NO1 and the second latch node.

A voltage for pulling down the first latch node NO1 is applied to the first voltage terminal VN11 and a voltage for pulling up the second latch node NO2 is applied to the second voltage terminal VN12 . For example, during a sensing operation, a ground voltage may be applied to the first voltage terminal VN11 and a power voltage VDD may be applied to the second voltage terminal VN12.

Before the power-up signal PVCCH is activated to a logic high, the second PMOS transistor PM12 is turned on and the first NMOS transistor NM11 is turned off, so that the first latch node NO1 is turned to logic high, (NO2) is set to logic low.

If the first and second anti-fuses AF11 and AF12 are not programmed, even if the switching transistors TS11 and TS12 are turned on by the activation of the sensing enable signal SEN, the voltage terminals VN11 and VN12 The electrical connection of the latch nodes NO1 and NO2 is interrupted. Thus, the second latch node NO2 is stabilized to a logic low, and the sensing output signal SOUT remains at a logic low.

On the other hand, when the first and second anti-fuses AF11 and AF12 are programmed, the switching transistors TS11 and TS12 are turned on by the activation of the sensing enable signal SEN to turn on the voltage terminals VN11 and VN12, And the latch nodes NO1 and NO2 are electrically connected. A relatively low pulldown voltage is applied to the first voltage terminal VN11 and a relatively high pullup voltage is applied to the second voltage terminal VN12 so that the voltage of the first latch node NO1 changes to a logic low, The voltage of the node NO2 changes to a logic high. Thus, the second latch node NO2 is stabilized to a logic high, and the sensing output signal SOUT remains a logic high.

As described above, the sensing output signal SOUT of the fuse sensing unit 240 is output as a logic low when not programmed, and outputted as a logic high when programmed. Thus, it is possible to determine whether or not the anti-fuse is programmed.

In searching for the presence or absence of the program of the first anti-fuse AF11, the second anti-fuse AF12 functions as a reference anti-fuse and may be a pre-grounded fuse.

Figure 5 is an illustration of an anti-fuse circuit in the anti-fuse array of Figure 1;

5, the anti-fuse circuit may include an anti-fuse 9, a pull-up transistor NM1, a pull-down transistor NM2, a level detector 2 and a pull-down control circuit 7. Further, the anti-fuse circuit 10i may further include an inverter 8 for inverting the voltage of the node N1.

The anti-fuse 9 has a first terminal to which a program voltage VPG is applied. The pull-up transistor NM1 is connected between the second terminal of the anti-fuse 9 and the node N1 and connects the node N1 to the program voltage VPG when the anti-fuse 9 is programmed .

The pull-down transistor NM2 couples the node N1 to the ground voltage GND in response to the pull-down control signal PDC. The level detector 2 compares the detection reference voltage VDET with the voltage VA of the node N1 and generates a detection output signal DETO. The detection output signal DETO has a voltage level that is logic "low" when the voltage VA of the node N1 is greater than the detection reference voltage VDET and the voltage VA of the node N1 is the detection reference voltage VDET Quot; high "voltage level. ≪ / RTI >

The pull-down control circuit 7 receives the fuse input signal FUSI0 and the detection output signal DETO and performs an AND operation. The pull-down control circuit 7 generates a pull-down control signal PDC. The fuse output signal FUSO0 is a signal in which the voltage VA of the node N1 is inverted by the inverter 8.

Although the inverter 8 is shown as one in the drawing, an odd number or an even number of inverters may be added according to a necessary logic state.

Although the anti-fuse output signal in FIG. 5 is assumed to have a logic high during programming, it may also have a logic low due to the acceleration / deceleration of the inverter.

In general, when using a laser fuse, the program is implemented by cutting a fuse composed of metal lines with a laser. However, there is a restriction that a certain interval between the fuse and the fuse must be ensured in order to prevent damage by the laser fuse. Regardless of the evolution of memory fabrication process technologies such as metal oxide semiconductor (MOS) processes, laser fuses have limitations in increasing the degree of integration and become unusable once the memory chips are packaged.

On the other hand, an electrical fuse and an anti-fuse are programmed using an electrical signal. That is, it can be used after packaging because it activates or deactivates the fuse by an electrical signal, and the size of the fuse circuit can be reduced together with the reduction of the process scale.

A program using an E-fuse is performed by applying a high current to the fuse. The E-fuse can be roughened by external control signals even after packaging, but a relatively large-sized driver is required to allow a large amount of current to flow through the E-fuse.

On the other hand, the anti-fuse program is performed by applying a high voltage to both ends of the fuse, unlike the E-fuse. Generally, the anti-fuse is implemented as a capacitor element. When a high voltage is applied to both ends of the anti-fuse, the dielectric inside the capacitor is destroyed and functions as a conductor. Like the E-fuse, the anti-fuse is routed by externally applying control signals after packaging.

Although an anti-fuse is described as being used in the embodiment of the present invention, an E-fuse can be used as well.

FIG. 7 is a circuit block diagram illustrating the low repair operation of FIG. 1 by way of example.

7, a semiconductor memory device may include an anti-fuse array 300, a P / S converter 310, an address decoder 150, a low redundancy unit 160, and a memory cell array 110 .

The memory cell array 110 includes a normal cell block 120 having normal memory cells connected to the normal word lines NWL1 to NWLn and a memory cell array 120 having redundancy memory cells connected to the spare word lines SWL1 to SWL3 And a spare cell block 130.

The anti-fuse array 300 includes a plurality of anti-fuses in the fuse box lines 300-1, 300-2, and 300-3.

The parallel-to-serial converter 310 converts the parallel fail data output through the anti-fuse array 300 into serial data.

The address decoder 150 decodes the input address to generate a decoding normal address.

The low redundancy unit 160 compares the decoding normal address with the fail address. The low redundancy unit 160 causes the spare word line to be activated when the decoding normal address and the fail address coincide with each other.

7, assuming that a fail is generated in the normal word line NWL3 of the normal cell block 120, the row address for selecting the normal word line NWL3 is set to the fuse box line in the anti-fuse array 300, Is programmed as a fail address by using the address register 300-1. Accordingly, when a row address for selecting the normal word line NWL3 is applied during the memory access operation, the spare word line SWL1 in the spare cell block 130 is activated instead of activating the normal word line NWL3 Activated. As a result, the defective normal word line is repaired by the repair operation to the spare word line.

Assume that after a program using the fuse box line 300-1 is once performed, a defect is newly generated in one of the memory cells connected to, for example, the normal word line NWL4 in a test process at the shipping stage of the product . In such a case it is usually necessary to know which fuse box lines of the fuse box lines 300-1, 300-2, 300-3 in the anti-fuse array 300 have been programmed, i.e. previous repair information. However, in the embodiment of the present invention, the unused fuse box lines are retrieved from the previous program through the operation of the fuse programming circuit 200 as described with reference to FIG. 3 without having previous repair information, Address can be programmed.

Therefore, the program for the fuse box line 300-1 is excluded at the time of the additional program, and the further generated another fail address can be programmed using, for example, the fuse box line 300-2 have.

When a row address for selecting the normal word line NWL4 is applied in the memory access operation, the spare word line SWL2 in the spare cell block 130 is activated instead of activating the normal word line NWL4. As a result, the defective normal word line is further repaired to the spare word line by an additional repair operation.

As a result, the test user does not need to inquire the previous repair history, and the trouble of creating the repair history database is eliminated.

FIG. 8 is a configuration example of an anti-fuse array showing an example in which an additional bit is included in the anti-fuse array of FIG. 3; FIG.

Referring to Fig. 8, the anti-fuse array 300 includes n (n is a natural number of 2 or more) fuse box lines 300-1, 300-2, ..., 300-n. Each fuse box line (eg, 300-1) consists of m (m is a natural number greater than or equal to 3) anti-fuses. The master bit a1 of the m anti-fuses is used as an additional bit. The additional bit is utilized as a flag bit indicating whether the fuse box line 300-1 is an idle resource or not. For example, if the master bit a1 which is the flag bit is "0 ", it is regarded as a resource of a programmable fuse box line. On the other hand, if the master bit a1 as a flag bit is "1 ", it is regarded as a fuse box line that has already been programmed and is no longer treated as an available resource. M-A (where A is the number of additional bits) bits excluding one additional bit of the m bits of the fuse box line 300-1 may be equal to or greater than the number of address bits of the fail address. For example, if the number of address bits of the fail address is 13 bits, the m-A bits of the fuse box line 300-1 are provided as at least 13 bits.

In the case of FIG. 8, the search of the idle fuses is performed by sequentially scanning the master bit a1 arranged at the most significant bit (MSB) of the fuse box lines 300-1, 300-2, ..., 300-n . That is, the operation of searching for the idle fuses in the anti-fuse array 300 when another additional fail address has occurred is implemented by sensing the master bit a1 of the fuse box line. 8, since the information of the master bit a1 of the third fuse box line 300-3 among the fuse box lines 300-1, 300-2, ..., 300-n is "0", the fuse box line 300-3) are primarily retrieved as idle resources. After the desired fail address information is programmed in the third fuse box line 300-3, the flag information of the master bit a1 of the third fuse box line 300-3 is changed to "1". When the search operation is started again after the program operation, since the information of the master bit a1 of the fifth fuse box line 300-5 is "0 ", the fuse box line 300-5 is searched for secondary do.

Thus, by setting a single additional bit to the flag information bit, the fuse box line usable as an idle resource can be searched relatively easily, without needing to sense all the bits in the fuse box line.

9 is a configuration example of an anti-fuse array showing an example including additional bits in the anti-fuse array of FIG.

9, the anti-fuse array 300 includes n (n is a natural number of 2 or more) fuse box lines 300-1, 300-2, ..., 300-n, as in FIG. Each fuse box line (eg, 300-5) consists of m (m is a natural number greater than or equal to 3) anti-fuses. Among the m anti-fuses, the master bit a1 and the m-th bit a7, which is the least significant bit, are used as additional bits. The additional bits are utilized as flag bits indicating whether the fuse box line 300-5 is an idle resource or not. For example, if both the master bit a1 and the m-th bit a7, which are flag bits, are "0 ", they are regarded as resources of the programmable fuse box line. On the other hand, if either one of the master bit a1 and the m-th bit a7, which are flag bits, is "1 ", it is regarded as a previously programmed fuse box line and is no longer treated as available resources. M-A (where A is the number of additional bits) bits excluding the additional bits of the m bits of the fuse box line 300-5 may be equal to or greater than the number of address bits of the fail address. For example, if the number of address bits of the fail address is 13 bits, the m-A bits of the fuse box line 300-5 are provided as at least 13 bits.

In the case of FIG. 9, the search of the idle fuses is performed by comparing the master bit a1 and the least significant bit (LSB) arranged at the MSBs of the fuse box lines 300-1, 300-2, ..., 300- And the m-th bit a7 arranged in the bit-by-bit manner. That is, the operation of searching for the idle fuses in the anti-fuse array 300 when another additional fail address is generated is implemented by sensing the master bit a1 and the m-th bit a7 of the fuse box line . 9, the information of the master bit a1 and the m-th bit a7 of the fifth fuse box line 300-5 among the fuse box lines 300-1, 300-2, ..., 300- Are all "0" s and thus are retrieved as idle resources. At least one of the master bit a1 and the m-th bit a7 of the fifth fuse box line 300-5 is set to " 1 ". When the search operation starts again after the program operation, the fuse box line in which the information of the master bit a1 and the information of the m-th bit a7 are both "0" is scanned.

Thus, setting the two bits of additional bits as flag information bits makes it possible to reliably and easily retrieve the fuse box lines usable as idle resources, without having to sense all the bits in the fuse box line.

As described above, in FIG. 8, a single bit is used as an additional bit for the idle resource scan. In FIG. 9, 2 bits are used as additional bits for the idle resource scan. However, in order to increase the reliability, It is needless to say that the number of flag information bits can be extended.

10 is a block diagram illustrating an application of the present invention applied to a memory system.

Referring to FIG. 10, the memory system may include a controller 1000 and a dynamic random access memory (DRAM) 2000. The DRAM 2000 may be connected to the controller 1000 via the system bus B1 to receive data, addresses, and commands. In addition, the DRAM 2000 may provide the data read from the memory cell to the controller 1000 through the system bus B1.

The controller 1000 may be connected to an unshown host via a predetermined interface.

The DRAM 2000 may have a circuit configuration as shown in FIG.

Thus, within the memory system, the DRAM 2000 can retrieve unused idle fuses in the fuse array and program another fail address that has been generated, without relying on previous repair information. Thus, the test time and test steps for the repair operation of defective memory cells are shortened. Therefore, the implementation cost of the memory system including the DRAM 2000 is reduced.

11 is a block diagram showing an application example of the present invention applied to a mobile device.

11, a mobile device such as a notebook or portable electronic device includes a microprocessing unit 1100 (MPU), a display 1400, an interface unit 1300, a DRAM 2000, and a solid state drive 3000 .

The MPU 1100, the DRAM 2000, and the SSD 3000 may be manufactured or packaged into one chip as the case may be. As a result, the DRAM 2000 and the flash memory 3000 may be embedded in the mobile device.

When the mobile device is a portable communication device, the interface unit 1300 may be connected to a modem and a transceiver that perform communication data transmission / reception and data modulation / demodulation functions.

The MPU 1100 controls all operations of the mobile device according to a preset program.

The DRAM 2000 is connected to the MPU 1100 and can function as a buffer memory or a main memory of the MPU 1100. The DRAM 2000 can search for unused idle fuses in the fuse array and program another fail address that is generated further, without relying on previous repair information when an additional fail address is generated. Therefore, since the generation and maintenance of the database for the previous repair information is not necessary, the test time and the test steps of the repair work are shortened. Therefore, the implementation cost of the mobile device including the DRAM 2000 is reduced.

The flash memory 3000 may be a NOR type or NAND type flash memory.

The display 1400 may have a touch screen as a liquid crystal having a backlight or an element such as a liquid crystal or an OLED having an LED light source. The display 1400 functions as an output device for displaying images such as characters, numbers, and pictures in color.

Although the mobile device has been described as a mobile communication device, it may function as a smart card by adding or subtracting components when necessary.

The mobile device may be connected to an external communication device via a separate interface. The communication device may be a digital versatile disc (DVD) player, a computer, a set top box (STB), a game machine, a digital camcorder, or the like.

Although it is not shown in the drawing, the mobile device may be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Do.

The chip forming the mobile device can be mounted using various types of packages. For example, the chip can be used as a package in package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in- Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC) ), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) and Wafer-Level Processed Stack Package Can be packaged as a package.

Meanwhile, although a flash memory is employed in FIG. 11, various kinds of nonvolatile storage may be used.

The non-volatile storage may store data information having various data types such as text, graphics, software codes, and the like.

The non-volatile storage may include, for example, an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM, a spin transfer torque MRAM, a conductive bridging RAM CBRAM), FeRAM (Ferroelectric RAM), PRAM (Phase Change RAM), OBR (Ovonic Unified Memory), Resistive RAM (RRAM or ReRAM), Nanotube RRAM, Polymer RAM ), A nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory .

12 is a block diagram showing an application example of the present invention applied to an optical I / O schema.

Referring to FIG. 12, a memory system 30 employing a high-speed optic I / O includes a chipset 40 and memory modules 50 and 60 as a controller mounted on a PCB substrate 31. The memory modules 50 and 60 are inserted into the slots 35_1 and 35_2 provided on the PCB substrate 31, respectively. The memory module 50 includes a connector 57, DRAM memory chips 55_1 to 55_n, an optical I / O input section 51, and an optical I / O output section 53.

The optical I / O input unit 51 may include a photo-electric conversion element, for example, a photodiode, for converting an applied optical signal into an electrical signal. Therefore, the electric signal output from the photo-electric conversion element is received by the memory module 50. The optical I / O output unit 53 may include an electro-optical conversion element, for example, a laser diode, for converting an electric signal output from the memory module 50 into an optical signal. If necessary, the optical I / O output unit 53 may further include an optical modulator for modulating a signal output from the light source.

The optical cable 33 is responsible for optical communication between the optical I / O input unit 51 of the memory module 50 and the optical transmission unit 41_1 of the chipset 40. The optical communication may have a bandwidth of several tens of Gigabits per second or more. The memory module 50 may receive signals or data from the signal lines 37 and 39 of the chipset 40 through the connector 57 and transmit the signals or data through the optical cable 33 Speed data communication with the chipset 40. On the other hand, the resistors Rtm provided in the unshown lines 37 and 39 are termination resistors.

12, the DRAM memory chips 55_1-55_n according to the concept of the present invention can be mounted in the memory system 30 employing the optical I / O structure.

Thus, within the memory system 30, the DRAM memory chips 55_1-55_n can retrieve unused idle fuses in the fuse array, without having previous repair information upon the occurrence of an additional fail address, Another fail address can be programmed. Therefore, since the generation and maintenance of the database for the previous repair information is not necessary, the test time and the test steps of the repair work are shortened.

In FIG. 12, the chipset 40 may have an intensive access detection unit 210. The centralized access detecting unit 210 generates an intensive access detection signal when the number of times of application of the frequently applied address exceeds a predetermined threshold value.

The chipset 40 may prevent or mitigate corruption of data held in memory cells of neighboring memory regions adjacent to a specific memory region when the lumped-access detection signal is generated.

For example, when a specific word line, a specific bit line, or a specific memory block of a volatile semiconductor memory such as a DRAM is intensively accessed, deterioration of memory cell data may be caused. That is, the memory cells of neighboring word lines adjacent to a specific word line, adjacent bit lines adjacent to a specific bit line, or memory cells of an adjacent memory block adjacent to a specific memory block can lose cell data due to centralized access. It is necessary to eliminate or avoid such address concentration and to prevent or alleviate cell data loss.

When the DRAM memory chips 55_1 to 55_n of the memory modules 50 and 60 are accessed in a memory page unit, a column unit, or a bank unit, the centralized access detecting unit 210 monitors access concentration.

In the case where the memory system of Fig. 12 is referred to as an SSD, the DRAM memory chips 55_1-55_n may be used as a yaw data buffer.

13 is a block diagram illustrating an application example of the present invention applied to a trough silicon via (TSV).

Referring to the structure of the stacked memory device 500 of FIG. 13, a plurality of memory chips 520, 530, 540 and 550 are vertically stacked on the interface chip 510. Here, a plurality of through silicon vias 560 are formed through the memory chips 520, 530, 540 and 550. The three-dimensional stack package type memory device 500 vertically stacking a plurality of memory chips on the interface chip 510 using TSV technology is advantageous for high speed, low power consumption, and miniaturization while storing a large amount of data. Structure.

13, since the interface chip 510 can include the centralized access detecting unit 210, it is possible to efficiently prevent or mitigate deterioration of data in the DRAMs in the plurality of memory chips 520, 530, 540 and 550 .

In the stacked memory device as shown in FIG. 13, DRAMs according to the concept of the present invention can be mounted. Therefore, when the fail address is additionally programmed in the DRAMs constituting the plurality of memory chips 520, 530, 540 and 550, unused anti-fuses not participating in the program of the previous program are automatically searched in the fuse array irrespective of the previous repair information And another fail address generated may be programmed into the retrieved unused anti-fuses. Therefore, since the generation and maintenance of the database for the previous repair information is not necessary, the test time and the test steps of the repair work are shortened. Therefore, the implementation cost of the stacked memory device is reduced.

14 is a block diagram showing an application example of the present invention applied to an electronic system. As shown in Fig. 14, the electronic system includes an input device 3100, an output device 3300, a processor 3200, and a memory device 3400. The memory device 3400 includes the DRAM 100 as shown in FIG. It should also be noted that the DRAM 100 may be integrated into any one of the input device 3100, the output device 3300, and the processor 3200.

Even in the case of FIG. 14, since the DRAM 100 has a fuse programming circuit, in the case where an additional fail address is generated after the program of the fail address is once executed, the previous repair It is possible to search for the idle fuses that have not been used for the first time and to program another fail address that has been generated. Therefore, the burden of acquiring previous repair information and generating new repair information is eliminated.

15 is a block diagram showing an application example of the present invention mounted on a semiconductor wafer.

Referring to FIG. 15, a memory device 100 such as the above-described DRAM is processed on a semiconductor wafer 1300. It should be understood that the memory device 100 may also be fabricated on a wide variety of other semiconductor substrates. As described herein, the memory device 100 includes a fuse programming circuit 200 and an anti-fuse array 300. Therefore, in the event that an additional fail address is generated after the program of the fail address has been once executed, it is possible to search for unused fuses in the previous repair in the fuse array without having previous repair information, Can be programmed. Therefore, the burden of securing the previous repair information is eliminated.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. For example, without departing from the technical idea of the present invention, when the matter is different, the circuit configuration of FIG. 3 may be changed or added to search for idle fuses in the fuse array, You will be able to program the fuses.

Although the present invention has been described in the context of a DRAM including a DRAM memory cell, the present invention can be applied to other semiconductor memory devices requiring a fuse program without being limited thereto.

Description of the Related Art [0002]
100: semiconductor memory device
200: Fuse programming circuit
300: anti-fuse array

Claims (10)

A fuse array having a plurality of fuses for causing a fail address for memory cell repair to be programmed; And
Wherein the failure address in the fuse array does not depend on previous repair information indicating position information of the programmed fuses when the fail address is once programmed into the fuse array and another fail address subsequently occurs, And a fuse programming circuit to search for idle fuses in the fuse array and to program the further generated fail address to the retrieved idle fuses.
The semiconductor memory device of claim 1, wherein the fuse array is an anti-fuse array comprising a plurality of anti-fuses.
2. The circuit of claim 1, wherein the fuse programming circuit comprises:
A fuse row decoder for selecting a row of said fuses;
A fuse column decoder for selecting a row of the fuses;
A fuse sensing unit for sensing the presence or absence of fusing of the fuses;
A determination circuit for searching for an idle fuse among the fuses in response to a fuse sensing signal of the fuse sensing unit; And
And a program controller coupled to the fuse row decoder, the fuse column decoder, and the decision circuit for generally controlling the search of the idle fuses and the execution of the program of the idle fuses.
The semiconductor memory device according to claim 3, wherein the fuse column decoder comprises:
And a scanning voltage is applied to a selected column of the fuses in a search operation of the idle fuses under the control of the program controller.
A memory cell array including a plurality of memory cells;
An anti-fuse array having a plurality of anti-fuses for causing a fail address for memory cell repair of the memory cell array to be programmed; And
Wherein, after the fail address is once programmed into the anti-fuse array by causing some anti-fuses of the anti-fuses to be programmed, and further another fail address is generated, a previous repair And a fuse programming circuit for retrieving the non-corrupted anti-fuses among the anti-fuses and programming the further generated fail address to the retrieved idle anti-fuses.
6. The semiconductor memory device of claim 5, wherein the memory cell array comprises a normal cell block having the plurality of memory cells and a spare cell block having a plurality of spare memory cells for repairing the memory cells.
Store the further fail address if, after a fail address has been programmed in the fuse array having a plurality of fuses for memory cell repair, another fail address is additionally generated;
Searching for idle fuses in the fuse array that are not used for programming the fail address in the fuse array without having previous repair information indicating position information of the fuses programmed within the fuse array;
And programming the stored idle fuses if the stored idle fuses are searched.
8. The method according to claim 7, wherein a scanning operation for retrieval when the idle fuses are retrieved is held for a fuse program at the retrieval position.
Receiving the further fail address when another fail address is additionally generated after a fail address for memory cell repair is programmed into the anti-fuse array by some of the plurality of anti-fuses being routed;
Searching for the unrestrained idle anti-fuses among the anti-fuses, without previous repair information indicating position information of the some anti-fuses ruptured;
And when the idle anti-fuses are searched, rerun the retrieved idle anti-fuses so that the stored another fail address is further programmed into the anti-fuse array.
A memory cell array including a plurality of memory cells;
An anti-fuse array having a plurality of anti-fuses, the anti-fuses including additional bits to allow a fail address for memory cell repair of the memory cell array to be programmed; And
Wherein, after the fail address is once programmed into the anti-fuse array by causing some anti-fuses of the anti-fuses to be programmed, and further another fail address is generated, a previous repair And a fuse programming circuit for searching the idle anti-fuses, which are not ruptured among the anti-fuses, using the additional bits and for programming the further generated fail address to the retrieved idle anti-fuses, Memory device.

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