JP2008217268A - Write-protection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a write-protection device that reliably stores data from a processor in a storage device for storing data from the processor by diagnosing the storage device. <P>SOLUTION: The write-protection device stores test data in a first register, causes the processor to write the test data read from the first register into a second register, and permits the processor to write data into a third register after a data determination means compares the test data in the first register and the data in the second register to find their matching. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an apparatus for storing data from a processor, and more particularly to a write protection apparatus in which data writing is controlled by control of the processor.

  Conventionally, as a method for checking in advance whether data processed by a processor (hereinafter referred to as a CPU) is reliably stored in a storage device, the CPU writes different test data to all addresses of the storage device, and sequentially writes the test data. There has been a method of diagnosing whether the storage device operates correctly by comparing the read data and the written data.

  In this diagnosis method, in order to reduce the type of test data used for diagnosis of the storage device and the number of tests, the CPU writes the data whose sign is inverted to the specific address of the storage device and the other address, and the written data When the read data matches, there is a method in which the storage area is judged to be normal and writing is performed. reference).

In addition, a fixed value (key data) is written from a CPU to a specific storage unit (referred to as a key data register), and immediately after the key data stored in another storage unit matches the written data, the CPU There is a method in which writing to the storage device is judged to be normal and writing to the storage device is performed, and if there is a mismatch, the writing is stopped and data storage is protected (see Patent Document 2).
JP 2002-312252 A JP 2003-150448 A

  If the data processed by the CPU is mistakenly stored, correct power control using power control data that plays an important role in the storage device is not performed, and the storage device does not operate normally.

  In addition, if the CPU that controls the storage device malfunctions, abnormal access to the reset control register of the storage device may occur, which may cause a great obstacle to the operation of the entire system using the storage device.

  For this reason, it is necessary to provide a protection function in writing to the storage device and to minimize the occurrence of a failure when the CPU malfunctions.

  In the conventional solution described above, the method based on the comparison between the write data and the data stored in the storage device enables writing to the storage unit by writing data to a specific storage unit. Depending on the state, there is a possibility that the write protection cancellation function may be bypassed and an abnormal access to the storage unit may be performed. Therefore, the protection function is not sufficient, and its enhancement is a problem.

  Accordingly, one object of the present invention is to diagnose the operation of a storage device that stores data from a processor (CPU), and to provide a device in which data from the processor is reliably stored in the storage device.

  In addition, it is a result derived | led-out by each structure shown in the best form for implementing invention mentioned later not only the said objective, Comprising: The effect which is not acquired by the prior art is also one of the other objectives of this invention. Can be positioned.

(1) In the present invention, the test data is stored in the first register, the test data read from the first register by the processor is written in the second register, and the data judging means and the test data in the first register A write protection device is used in which the processor data is permitted to be written to the third register when the two register data match.

  Preferably, a write protection device is used in which each of the first register and the second register has one storage address.

  Preferably, the data judging means uses a write protection device characterized by comparing data stored in the two registers via a line directly connected to the first register and the second register.

Preferably, when the test data stored in the first register matches the data read by the processor from the first register and written to the second register, the data is written to the third register. A write protection device is used, wherein the processor is allowed to read data.
(2) A data protection device in which data judged as important by the processor among the data of the processor is written in the register 3 based on the write permission, and data judged not important is written in the register 4 without the write permission. Use.
(3) In the present invention, the test data is stored in the first register, the data obtained by inverting each bit of the test data read from the first register by the processor is written in the second register, and the data determination means is the first register. A write protection device is used in which when the data obtained by inverting each bit of the test data of the register of the second register matches the data of the second register, the processor data is permitted to be written to the third register.

(4) The first register and the second register each have one storage address, and the address number of the second register is obtained by inverting each bit of the address number of the first register. A write protector characterized by an address number is used.

  According to the present invention, it is possible to provide a write protection device capable of reliably writing data from a processor to a storage device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Example 1)
In the first embodiment, only when the test data stored in the first register (hereinafter referred to as register A) matches the test data in the second register (hereinafter referred to as register B) from which the test data in register A is read and written. Data writing to a third register (hereinafter referred to as a protection register) is permitted.

  FIG. 1 shows the configuration of the write protection device according to the first embodiment, and FIG. 2 shows the flow of write control.

・ "Configuration of write protector"
In FIG. 1, 101 is a write protection device, 102 is a CPU, 103 is a storage device, 104 is an address decoding unit, 105 is a logical sum unit, 106 is a data determination unit, 107 is a register A, 108 is a register B, and 109 is a test. A data generation unit, 110 is a protection register, 111 is a no-protection register, 112, 113, and 114 are buffers, and 115, 116, 117, and 118 are gates, respectively.

・ "Write control flow"
In FIG. 2, S201 is a step for starting writing, S202 is a step for generating write data by the CPU 102, S203 is a step for determining whether the write data is protected data, S204 is a step for writing to the unprotected register 111, and S205 is a register. A step of reading test data of A107, S206 is a step of writing test data from the register A107 into the register B108, S207 is a step of comparing the test data stored in the register A107 and the test data stored in the register B108, and S208 is A step of notifying the CPU 102 of an abnormality, S209 indicates a step of prohibiting writing to the protection register 110, and S210 indicates a step of permitting writing to the protection register 110.

  Based on the flow of write control in FIG. 2, the write control operation in the first embodiment will be described using the configuration diagram in FIG.

  In the following steps, the CPU 102 controls the writing and reading of data to and from the storage device 103.

  Write control is started in step S201.

  In step S202, write data to be stored by the CPU 102 is generated. At this time, the CPU 102 designates the address of the protection register 110 as a write destination for important data affecting the entire system (not shown) including the write protection device 101, and there is no protection for data with low importance. The address of the register 111 is designated.

  In step S203, the address decoding unit 104 checks the write destination address to determine whether the write data should be protected (hereinafter protected data) or not protected (hereinafter unprotected data).

  Step S204 is a case where step S203 is No and it is determined that there is no protection data. The address decoding unit 104 transmits the address designated by the CPU 102 to the no protection register 111, and the data from the CPU 102 is written.

  Step S205 is a case where it is determined that the protected data is Yes in step S203, and the CPU 102 reads the test data from the register A107. The register A 107 is supplied with random test data from the test data generation unit 109 and stores it as data A.

  In step S206, the CPU 102 writes the data A read out in step S205 into the register B108 and stores it as data B in the register B108.

  In step S207, the data determination unit 106 compares the data A stored in the register A 107 with the data B stored in the register B 108 in hardware. That is, in this data comparison, the CPU 102 does not perform writing and reading processing, and the data determination unit 106 directly compares the data.

  Step S208 is a case where step S207 is No and data A and data B are different, and indicates that an error has occurred in the writing and reading processing. Therefore, the data determination unit 106 notifies the CPU 102 of the occurrence of an abnormality, and the protection register The gate 117 that controls the address signal to 110 is notified of write prohibition.

  In step S209, the CPU 102 having received the notification of the occurrence of the abnormality prohibits data writing to the protection register 110 and issues an alarm to the administrator or the like.

  Step S210 is a case where step S207 is Yes and data A and data B match, indicating that the writing and reading processes are normal. Therefore, the data determination unit 106 sends an address signal to the CPU 102 and the protection register 110. The write permission is transmitted to the gate 117 to be controlled. The CPU 102 that has received the notification of normal writing and reading instructs the address decoding unit 104 to write data to the protection register 110 by a bus control signal.

  When step S210 ends, the process returns to step S202, and the next data processing is repeated.

  Accordingly, the protection data is written into the protection register 110 only when the above steps are followed and writing is permitted.

  Since unprotected data does not pass through the entire process, the unprotected register 111 is written in a short time.

・ "Write operation to register"
A data write operation from the CPU 102 to the protection register 110 and the non-protection register 111 after the determination of whether or not writing is possible will be described with reference to the configuration diagram of FIG.

  When the data generated by the CPU 102 is unprotected data, the CPU 102 designates one address number in the unprotected register 111 as a write destination address to the address decoding unit 104. The address decoding unit 104 notifies the unprotected register 111 of the write destination address number, and the CPU 102 transmits data to be stored to the unprotected register 111 via the buffer 112. The unprotected register 111 writes and stores the data at a designated address.

  When the data generated by the CPU 102 is protection data, the CPU 102 designates one address in the protection register 110 as a write destination address to the address decoding unit 104. The address decoding unit 104 notifies the protection register 110 of the write destination address number, and the CPU 102 transmits data to be stored to the protection register 110 via the buffer 112.

  When the data determination unit 106 outputs a write permission signal, the gate 117 is opened, the address designation signal from the address decoding unit 104 is connected to the protection register 110, and data is written to the protection register 110.

  Therefore, the writing of data from the CPU 102 to the protection register 110 is executed only when the process starts from S202 of FIG. 2 and passes through the step of S210.

  That is, permission to write to the protection register 110 according to the flow of FIG. 2 is obtained when the CPU 102, the address decoding unit 104, the register A 107, the register B 108, and the address bus, data bus, and bus control signal system that connect them operate normally. To be done.

  In the above flow, the protection register 110 itself is not used, but the storage device 103 is formed by one minute semiconductor chip, and one part of the address of the protection register 110 is used as the address of the register A 107 and the register B 108. It can be regarded as set.

  Therefore, if the register A 107 and the register B 108 are normal, it can be confirmed that the protection register 110 placed under the same environmental conditions (external noise, temperature, etc.) on one chip manufactured under the same conditions is normal.

  Further, the address of the register A 107 and the register B 108 used in the flow of FIG. 2 is one and each set of data stored in both addresses is compared once, so the writing process can be performed in a short time. Yes.

・ "Read operation from register"
Reading data from each register will be described with reference to the block diagram of FIG.

  The CPU 102 outputs a data read command and the stored register address number to the address decoding unit 104 by a bus control signal.

  The address decoding unit 104 sends a read command signal to the gate corresponding to the address number commanded from the CPU 102. The gate that has received the read command signal reads data from the corresponding register address.

  For example, data read from the protection register 110 is read from a designated address by a read command signal commanded to the gate 116.

  The read data is taken out by the logical sum unit 105 and input to the CPU 102 via the buffer 113.

  Since the data read at a time is one of the non-protection register 111, the protection register 110, and the register A 107, each read data can be taken out by the logical sum unit 105 by the logical sum of these data.

  Since the data determination unit directly takes out the data of the register B108 in hardware, the reading process by the CPU 102 is not required.

  In the description so far, for the reading from the protection register 110, the operation check at the time of writing is not performed, but reading control for correctly reading the data may be performed.

  FIG. 3 shows a flow for performing the read control.

  In FIG. 3, S301 is a step of starting reading, S302 is a step of generating read data in the CPU, S303 is a step of determining whether the read data is protected data, S304 is a step of reading from the unprotected register, and S305 is a register A Step S306 is a step of writing data from the register A to the register B, S307 is a step of comparing the data stored in the register A with the data stored in the register B, and S308 notifies the CPU of the abnormality. S309 indicates a step of prohibiting reading from the protection register, and S310 indicates a step of permitting reading from the protection register.

  Based on the flow of read control in FIG. 3, the read control operation in the first embodiment will be described using the configuration diagram in FIG.

  In the following steps, the CPU 102 controls the writing and reading of data from the storage device 103.

  In step S301, read control is started.

  In step S302, data to be read out is generated in the CPU. At this time, the important data affecting the entire system (not shown) including the write protection device is designated with the address of the protection register 110, and the data with less importance is designated with the address of the unprotected register 111. .

  In step S303, the address decoding unit 104 checks the read destination address number to determine whether the read data is protected data or unprotected data.

  Step S304 is a case where step S303 is No and it is determined that the data is unprotected, and the address decoding unit 104 notifies the address of the unprotected register 111 designated by the CPU 102, and the data is read and taken into the CPU 102.

  Step S305 is a case where step S303 is Yes and it is determined as protection data, and the CPU 102 reads test data from the register A107. The register A 107 is supplied with random test data from the test data generation unit 109 and stores it as data A.

  In step S306, the CPU 102 writes the data A read in step S205 to the register B108 and stores it as data B.

  In step S307, the data determination unit 106 compares the data A stored in the register A107 and the data B stored in the register B108 in hardware. In this data comparison, the CPU 102 does not perform writing and reading processing, and the direct data determination unit 106 performs data comparison.

  Step S308 is a case where step S307 is No and data A and data B are different, and indicates that an error has occurred in the writing and reading processing. Therefore, the data determination unit 106 notifies the CPU 102 of the occurrence of the abnormality, and the protection register Read prohibition is transmitted to the gate 116 that controls the address signal 110 (not shown in FIG. 1).

  In step S309, the CPU 102 that has received the notification of the occurrence of the abnormality prohibits data reading from the protection register 110 and issues an alarm to the administrator or the like.

  Step S310 is a case where step S307 is Yes and data A and data B match, and indicates that the writing and reading processes are normal. Therefore, the data determination unit 106 controls the CPU 102 and the address signal of the protection register 110. Read permission is transmitted to the gate 116.

  In step S310, the CPU 102 that has received notification of normal writing and reading instructs the address decoding unit 104 to read data from the protection register 110 by a bus control signal.

  When step S310 ends, the process returns to step S302 to repeat the next data processing.

Therefore, the protection data is read from the protection register 110 only when the above steps are followed and the reading is permitted.
(Example 2)
In the second embodiment, the inverted data of the test data stored in the first register (register A) matches the test data of the second register (register B) written by reading and inverting the data of the register A. Only when is data writing to the protection register permitted.

  FIG. 4 shows the configuration of the write protection apparatus according to the second embodiment, and FIG. 5 shows the flow of write control.

・ "Configuration of write protector"
In FIG. 4, 401 is a write protection device, 402 is a CPU, 403 is a storage device, 404 is an address decoding unit, 405 is a logical sum unit, 406 is a data determination unit, 407 is a register A, 408 is a register B, and 409 is a test. A data generation unit, 410 is a protection register, 411 is a non-protection register, 412, 113 are buffers, 414 is an inversion buffer, 415, 416, 417, and 418 are gates, respectively.

  1 differs from FIG. 1 of the embodiment in that 414 is an inverting buffer.

・ "Write control flow"
In FIG. 5, S501 is a step of starting writing, S502 is a step of generating write data by the CPU 402, S503 is a step of determining whether the write data is protected data, S504 is a step of writing to the unprotected register 411, and S505 is a register. A step of reading test data of A407, S506 is a step of inverting and writing data from register A407 to register B408, and S507 is a step of comparing the test data stored in register B408 with the inverted data of test data stored in register A407 S508 is a step of notifying the CPU 402 of an abnormality, S509 is a step of prohibiting writing to the protection register 410, and S510 is a step of allowing writing to the protection register 410. It is.

  Based on the flow of write control in FIG. 5, the write control operation in the second embodiment will be described with reference to the configuration diagram in FIG.

  In the following steps, the CPU 402 controls the writing and reading of data to the storage device 403.

  Write control is started in step S501.

  In step S502, write data to be stored by the CPU 402 is generated. At this time, the CPU 402 gives the address of the protection register 410 as a write destination for important data affecting the entire system (not shown) including the write protection device, and the no-protection register 411 for data with low importance. Give the address.

  In step S503, the address decoding unit 404 checks the write destination address to determine whether the write data should be protected (hereinafter protected data) or not protected (hereinafter unprotected data).

  Step S504 is a case where step S503 is No and it is determined that there is no protection data. The address decoding unit 404 transmits the address designated by the CPU 402 to the no protection register 411, and the data from the CPU 402 is written.

  Step S505 is a case where step S503 is determined as Yes and protection data, and the CPU 402 reads test data from the register A407. The register A 407 is supplied with random test data from the test data generation unit 409 and stores it as data A.

  In step S506, the CPU 402 inverts the data A read in step S505, writes the data A in the register B408, and stores the data A in the register B408 as data B.

  FIG. 6 shows an example of data A stored in the register A407 and data B stored by inverting the data A in the register B408.

  FIG. 6 shows a case where the data A (D61) stored in the register A407 is hexadecimal data and is AAAA. Hexadecimal data A is 1010 shown in D62 in the binary data physically transmitted.

  Data A is inverted and written into the register B408 to become data B (D63).

  When the binary data 1010 of D62 is inverted, it becomes 0101, which becomes 5 of the hexadecimal data.

  That is, the data B written by inverting the data AAAA of the data A correctly becomes 5555.

  In step S507, the data determination unit 406 compares the data A stored in the register A407 with the data B stored in the register B408 in hardware. That is, in this data comparison, the CPU 402 does not perform writing and reading processing, and the direct data determination unit 406 directly compares the data. The data A stored in the register A 407 is inverted in bit by the inversion buffer 414 and compared with the data B in the data determination unit 406.

  FIG. 7 shows an example of the data B written in the register B 408 due to an error on the data bus in reading the data A stored in the register A 407.

  FIG. 7 shows a case where the data A (D71) stored in the register A407 is hexadecimal data and is AAAA. A of hexadecimal data is 1010 of binary data shown in binary data D72 in hardware.

  When the CPU 402 reads out data A from the register A407 and an error occurs in which the data bus fixes the 16th bit to 0, the binary data D74 in FIG. 7 is obtained, so the hexadecimal data is 2AAA.

  Even if the CPU 402 inverts the data D77 correctly and writes it correctly to the register, the data B becomes the binary data D76, and the hexadecimal data becomes D555.

  The binary data obtained by correctly inverting the data AAAA in the register A407 is 5555, which is compared with the binary data D555 in the register B408 and does not match.

  Step S508 is a case where Step S507 is No and data A and data B are different, and indicates that an error has occurred in the writing and reading processing. Therefore, the data determination unit 406 notifies the CPU 402 of the occurrence of the abnormality and protects it. The write prohibition is transmitted to the gate 417 that controls the address signal to the register 410.

  In step S509, the CPU 402 that has received the notification of the occurrence of an abnormality prohibits data writing to the protection register 410 and issues an alarm to the administrator or the like.

  Step S510 is a case where Step S507 is Yes and the data A and the data B match, and indicates that the writing and reading processes are normal. Therefore, the data determination unit 406 outputs the address signal to the CPU 402 and the protection register 410. The write permission is transmitted to the gate 417 to be controlled.

  In step S510, the CPU 402 that has received the notification of normal writing and reading instructs the address decoding unit 404 to write data to the protection register 410 using a bus control signal.

  When step S510 ends, the process returns to step S502, and the next data processing is repeated.

  Accordingly, the protection data is written into the protection register 410 only when the above steps are followed and writing is permitted.

  In the second embodiment, the data A in the register A407 and the data B written in the register B408 are different but inverted data. Therefore, the comparison between the two data does not involve the data inversion processing by the CPU 402, and the data A is By performing bit inversion by the inversion buffer 414 in hardware, it can be easily performed in a short time.

  Further, since the unprotected data does not pass through the entire process, the unprotected register 411 is written in a short time.

・ "Write operation to register"
After the determination of whether or not writing is possible, the data write operation from the CPU 402 to the protection register 410 and the non-protection register 411 will be described with reference to the configuration diagram of FIG.

  When the data generated by the CPU 402 is unprotected data, the CPU 402 designates one address in the unprotected register 411 as a write destination address to the address decoding unit 404. The address decoding unit 404 notifies the unprotected register 411 of the write destination address and transmits data to be stored to the unprotected register 411 via the buffer 412. The unprotected register 111 writes and stores the data at a designated address.

  When the data generated by the CPU 402 is protection data, the CPU 402 designates one address in the protection register 410 as a write destination address to the address decoding unit 404. The address decoding unit 404 notifies the protection register 410 of the write destination address, and the CPU 402 transmits data to be stored to the protection register 410 via the buffer 412.

  When the data determination unit 406 outputs a write permission signal, the gate 417 is opened, the address designation signal from the address decoding unit 404 is connected to the protection register 410, and data is written to the protection register 410.

  Therefore, the writing of data from the CPU 402 to the protection register 410 is executed only when the processing starts from S502 in FIG. 5 and passes through the step of S510.

  Therefore, the permission to write to the protection register 410 according to the flow of FIG. 5 is that the CPU 402, the address decoding unit 404, the register A407, the register B408, and the address bus, data bus, and bus control signal system that connect them operate normally. If done.

  In the above flow, the protection register 410 itself is not used, but the storage device 403 is formed by one minute semiconductor chip, and a part of the address of the protection register 410 is set as the address of the register A407 and the register B408. Can be considered.

Therefore, if the register A 407 and the register B 408 are normal, it can be confirmed that the protection register 410 placed under the same environmental conditions (external noise, temperature, etc.) on one chip manufactured under the same conditions is normal.

  Furthermore, the register A407 and the register B408 used in the flow of FIG. 5 each have one address, and a set of data stored in both addresses is compared once, so the writing process can be performed in a short time. Yes.

・ "Read operation from register"
Reading data from each register will be described with reference to the block diagram of FIG.

  The CPU 402 outputs a data read command and the stored register address to the address decoding unit 404 by a bus control signal. The address decoding unit 404 sends a read command signal to the gate corresponding to the address commanded from the CPU 402.

  The gate that has received the read command signal reads data from the corresponding register address.

  For example, data read from the protection register 410 is read from a specified address by a read command signal commanded to the gate 416.

  The read data is extracted by the logical sum unit 405 and input to the CPU 402 via the buffer 413.

  Since the data read at one time is any one of the non-protection register 411, the protection register 410, and the register A407, each read data can be extracted from the logical sum unit 405 by their logical sum.

  The data in the register B 408 is directly taken out by the data determination unit, so that the reading process by the CPU 402 is not required.

  In the description so far, for the reading from the protection register 410, the operation check at the time of writing is not performed, but reading control for correctly reading the data may be performed.

  The case where the read control is performed is the same as that in the first embodiment, and the description thereof is omitted.

・ "Write control by address designation with address number reversed"
In the second embodiment, an address number obtained by inverting the address number specified in the register A407 may be used for addressing in the register B408.

  In this case, since the CPU 402 performs address designation to the register A 407 and the register B 408, the configuration of the write protection device is the same as in FIG. 4, and the feature is that the read and write destination address numbers are inverted.

  FIG. 8 is a detailed flow of FIG. 4, and a write control flow for inverting the address number will be described with reference to FIG.

  The flow in this case is basically the same as that in FIG. 5, but is characterized by addressing to the register A 407 and the register B 408, and the details after step S503 in FIG. 5 are shown in detail.

  In FIG. 8, step S801 is a step in which the write protection device 401 is placed in the IDLE (pause) state and writing is prohibited, step S802 is a step in which the register A407 fetches test data and holds it as data A, and step S803 is a step in which the CPU 402 performs data processing. The step of reading A, step S804 is a step in which the CPU 402 issues a test data write command, step S805 is a step of determining whether or not the commanded address number is in the register B, and step S806 is a step in which the CPU 402 inverts the data and registers B408. Is stored as write data B in step S807, inversion of data A is determined to match data B, step S808 notifies the CPU 402 of the abnormality, and write protector 401 is identified as ID. A step of resetting to the E state, a step S809 is a step of permitting writing, a step S810 is a step of instructing the CPU 402 to write information data, a step S811 is a step of determining whether the address instructed to write is a protection register, or a step S812 is A step of writing to the protection register and a step S813 respectively show a step of resetting to the IDLE (pause) state. After step S813, the process returns to step S502 in FIG. 5 and corresponds to the next write data generation by the CPU 402.

  The operation of inverting and specifying the write address number in the second embodiment will be described with reference to the write control flow of FIG. 8 and the configuration diagram of FIG.

  In the following steps, the CPU 402 controls the writing and reading of data to the storage device 403.

  Step S801 indicates the start from the processing in the case where the data commanded by the CPU 402 to write in step S503 in FIG. 5 is protected data, and the write protection device 401 is in a write-inhibited state and is referred to as an IDLE state.

  Step S 802 is a step in which the register A 407 is supplied with test data from the test data generation unit 409 and holds it. The data held in the register A 407 is data A. Steps S <b> 802 to S <b> 807 are processes for inspecting the write protection device, and are in a write-inhibited state and will be referred to as STATE <b> 1.

  In step S803, the CPU 402 designates the address number of the register A407 and reads the held data A.

  An example of the address data in this case is shown in FIG. D91 (hexadecimal data 5555) in FIG. 9 is a preset address number of the register A407. The CPU 402 notifies the register A407 via the address decoding unit 404 and the data determination unit 406, and the data A of the register A407 is stored. The data is read by the CPU 402.

  In step S804, in order for the CPU 402 to write the data B obtained by inverting the data A to the register B408, D93 (AAAA in hexadecimal data) of FIG. 9 which is the address of the register B408 is designated as the write destination address.

  For example, in the address bus that transmits this write destination address number from the CPU 402 to the address decoding unit 404, if an error occurs in which the 16th bit is fixed to 0, D95 (2AAA in hexadecimal) is obtained, and the register B408 It is different from the correct address number (AAAA in hexadecimal).

  In step S805, the address decoding unit 404 performs an address check, and determines whether or not the write destination address number commanded from the CPU 402 in STATE1 matches the address number set in the register B408 (eg, AAAA in hexadecimal). .

  If step S805 is No and not the register B408, it is determined that the data B is not written to the address of the register B408 (AAAA in hexadecimal), the process proceeds to step S808, the CPU 402 is notified of the abnormality, and the write protector IDLE Reset to. In the case of Yes and the register B408, the process proceeds to step S806.

  In step S806, the CPU 402 writes the data B obtained by inverting the data A to the register B408.

  In step S807, the data determination unit 406 compares the data obtained by inverting the bit of the data A stored in the register A407 with the inverting buffer 414 and the data B stored in the register B408 in hardware. In this data comparison, the CPU 402 does not perform writing and reading processing, and the direct data determination unit 406 directly compares the data.

  In the case of No in step S807, the data determination unit 406 determines that correct reading and writing have not been performed, proceeds to step S808, notifies the CPU 402 of the abnormality, and the write protection device is reset to IDLE.

  In the case of No in step S807, the reason why the inverted data of the data A of the register A407 and the data B of the register B408 do not coincide is the error of the data itself in the data reading, inversion processing, and writing, and the register A407 or the address B408. There is an error in the address number.

  An error in the write destination address number is checked up to the address decoding unit 404 in step S805, but a failure from the address decoding unit 404 to the data determination unit 406 and the register B 408 is detected in step S807.

  In the case of Yes in step S807, the data determination unit 406 permits writing in step S809, assuming that the test data is correctly read and written correctly.

  At this time, the write protection device is in a write permission state and is referred to as a STATE 2 state.

  In step S810, the CPU 402 instructs the address decoding unit 404 to write data.

  In step S 811, the address decoding unit 404 determines whether the write destination address instructed by the CPU 402 is in the protection register 410.

  When the steps up to this point in FIG. 8 are passed, it is for the protection register 410, and other address numbers are determined to be incorrect write destination addresses.

If the designated address is not in the protection register 410 in the case of No in step S811, the process proceeds to step S808 to notify the CPU 402 of the abnormality and the write protection device is reset to IDLE.
If YES in step S811, if the designated address is in the protection register 410, the process proceeds to step S812, and the data sent from the CPU 402 is written to the designated destination address in the protection register 410.

  When the data writing is completed, the write protection device 401 is reset to an IDLE (write-inhibited) state, returns to step S502 in FIG. 5, and corresponds to the write data generated by the CPU 402 next.

  Therefore, the writing of data from the CPU 402 to the protection register 410 is executed only when the process starting from S801 in FIG.

  Therefore, permission to write to the protection register 410 according to the flow of FIG. 8 indicates that the CPU 402, the address decoding unit 404, the register A407, the register B408, and the address bus, data bus, and bus control signal system that connect them operate normally. If done.

Further, since the address number obtained by inverting the address number of the register A407 is set for the register B408, the address designation of the CPU 402 in STATE1 is simple and can be performed in a short time.
(Appendix 1)
In a write protection device for controlling data writing by a processor,
First storage means for storing test data;
A second storage means for writing the read data, wherein the processor that has read the test data from the first storage means;
Determining means for determining whether the test data stored in the first storage means and the data stored in the second storage means match;
A control means for permitting data writing to the third storage means of the processor when it is judged by the judging means that they match,
A write protection device comprising:
(Appendix 2)
The write protection device according to appendix 1, wherein each of the first storage unit and the second storage unit has one storage address.
(Appendix 3)
The determination unit compares the test data stored in the two storage units via a line directly connected to the first storage unit and the second storage unit. The write protector described.
(Appendix 4)
The processor data written in the third storage means is the test data stored in the first storage means, and the processor reads from the first storage means and writes it in the second storage means. The write protection device according to appendix 1, wherein reading is permitted by the control means when the test data matches.
(Appendix 5)
Of the data of the processor, the data judged as important by the processor is written in the storage means 3 based on the write permission by the control means, and the data judged not important is written without the write permission by the control means. 4. The write protection device according to appendix 1, further comprising four storage means.
(Appendix 6)
In a write protection device for controlling data writing by a processor,
First storage means for storing test data;
A second storage means for writing the data obtained by inverting each bit of the read data, wherein the processor that has read the test data from the first storage means;
Determination means for determining whether data obtained by inverting each bit of the test data stored in the first storage means matches data stored in the second storage means;
A control means for permitting data writing to the third storage means of the processor when it is judged by the judging means that they match,
A write protection device comprising:
(Appendix 7)
The first storage means and the second storage means each have one storage address, and the address number of the second storage means is each bit of the address number of the first storage means. The write protection device according to appendix 6, wherein the address number is obtained by inverting the address number.
(Appendix 8)
The determination means compares the test data stored in the two storage means through the polarity inverting circuit and the second storage means through a directly connected line. The write protector according to appendix 6, wherein:
(Appendix 9)
Of the data of the processor, the data judged as important by the processor is written in the storage means 3 based on the write permission by the control means, and the data judged not important is written without the write permission by the control means. 4. The write protection device according to appendix 6, further comprising four storage means.

It is a figure which shows the structure (Example 1) of a write-protection apparatus. FIG. 6 is a diagram illustrating a flow of write control (Example 1). FIG. 6 is a diagram illustrating a flow of read control (Example 1). It is a figure which shows the structure (Example 2) of a write-protection apparatus. FIG. 10 is a diagram illustrating a flow of write control (Example 2). It is a figure which shows the example (Example 2) of inversion of hexadecimal data. It is a figure which shows the example (Example 2) in which hexadecimal data were mistaken. FIG. 10 is a diagram illustrating a detailed flow of write control (second embodiment). It is a figure which shows the example (Example 2) of the hexadecimal data for address numbers.

Explanation of symbols

101 Write protector 102 CPU
103 Storage Device 104 Address Decoding Unit 105 OR Unit 106 Register A
108 Register B
109 Test Data Generation Unit 110 Protection Register 111 No Protection Register 112 Buffer 113 Buffer 114 Buffer 115 Gate 116 Gate 117 Gate 118 Gate 401 Write Protection Device 402 CPU
403 Storage device 404 Address decoding unit 405 Logical sum unit 406 Data determination unit 407 Register A
408 Register B
409 Test data generation unit 410 Protection register 411 No protection register 412 Buffer 113 Buffer 414 Inversion buffer 415 Gate 416 Gate 417 Gate 418 Gate

Claims (4)

In a write protection device for controlling data writing by a processor,
First storage means for storing test data;
A second storage means for writing the read data, wherein the processor that has read the test data from the first storage means;
Determining means for determining whether the test data stored in the first storage means and the data stored in the second storage means match;
A control means for permitting data writing to the third storage means of the processor when it is judged by the judging means that they match,
A write protection device comprising:   2. The data storage device according to claim 1, further comprising: a fourth storage unit in which important data among the data of the processor is written to the storage unit 3 based on the write permission, and unimportant data is written without the write permission. The write protector described. In a write protection device for controlling data writing by a processor,
First storage means for storing test data;
A second storage means for writing the data obtained by inverting each bit of the read data, wherein the processor that has read the test data from the first storage means;
Determination means for determining whether data obtained by inverting each bit of the test data stored in the first storage means matches data stored in the second storage means;
A control means for permitting data writing to the third storage means of the processor when it is judged by the judging means that they match,
A write protection device comprising: The first storage means and the second storage means each have one storage address, and the address number of the second storage means is each bit of the address number of the first storage means. 4. The write protection apparatus according to claim 3, wherein the address number is obtained by inverting the address number.

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