JPS6366798A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten a checking time at the time of starting an operation by detecting the input of an external prescribed signal by a start control means, activating a self-diagnosing control means and outputting a writing and reading error by a data reading and writing control means after the activation if it is generated. CONSTITUTION:To the start control circuit 21, a column address strobe signal, the inverse of CAS used in an ordinary operation as a D-RAM, a row address strobe signal, the inverse of RAS, a write enable signal, the inverse of WE and an external address Add are supplied through an external terminal. Then, the start control circuit 21, when the input sequence and the level or the like of various types of inputted control signals are made a fixed condition, outputs a start signal to the self-diagnosing control circuit 18. The self-diagnosing control circuit 18 starts a self-diagnosing operation and supplies a control signal to an address counter 17, a writing data generating circuit 19, an address buffer/ multiplexer 16, a data multiplexer 15 and a trouble diagnosing/trouble signal generating circuit 20. If the number of memories used in a system is defined as N, it can be reduced to 1/N as much as the convention.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention relates to a large-capacity semiconductor memory device, and particularly to a method for automatically determining whether or not a defective cell exists in a memory cell array. The present invention relates to a semiconductor memory device that has a self-diagnosis function that performs self-diagnosis.

(Prior Art) Conventionally, semiconductor memory devices (hereinafter referred to as semiconductor memories)
When configuring a system using , you can check whether there are any defective cells in these semiconductor memories by operating each memory chip, selecting memory cells one by one from outside the chip, and checking the selected cells. This is done by writing data and checking whether it can be read correctly.

However, as semiconductor memory becomes larger in capacity and lower in price, the number of systems using semiconductor memory has increased dramatically, and at the same time, the capacity of semiconductor memory per system has also become enormous. There is. For this reason, for example, the amount of time required to check whether each semiconductor memory is defective at the start of system operation has become enormous. As a result, the startup of the system may be delayed, making it difficult to use. Moreover, wasted time during system startup not only reduces system availability;
Whenever you try to operate the system, you will always have to wait for a certain period of time.

Further, the higher the frequency of maintenance and inspection, the more noticeable these adverse effects become.

(Problems to be Solved by the Invention) As described above, conventional semiconductor storage devices have the drawback that the check time required at the start of operation of a system using the storage device is enormous, resulting in slow system startup. .

This invention was made in consideration of the above circumstances, and its purpose is to automatically determine whether or not a defect has occurred in each internal cell. It is an object of the present invention to provide a semiconductor memory device which can significantly shorten the check time at the start of operation of a system using a semiconductor memory device and can speed up the startup of the system.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device of the present invention includes a memory cell array having a plurality of memory cells, and one memory cell array in the memory cell array.
memory cell selection means for selecting one or more memory cells;
data read/write control means for controlling data writing to or reading data from the memory cell selected by the memory cell selection means; A self-diagnosis control means that performs self-diagnosis by sequentially writing predetermined data into each memory cell, reading it after it is old, and detecting whether or not an error has occurred in the read data. ,
It is composed of a start control means that detects that a predetermined signal is inputted in a predetermined order and level to a plurality of external terminals used in normal operation and starts the new control means described in 11.Self-diagnosis 1. .

(Operation) In the semiconductor memory device of the present invention, the self-diagnosis control means is activated when the activation control means detects that a predetermined signal is input from the outside in a predetermined order and at a predetermined level.

After the self-diagnosis control means is activated, predetermined data is sequentially written into each memory cell in the memory cell array by the data read/write control means, and after writing, the data is read out. Then, it is detected whether or not an error has occurred in the read data, and if an error has occurred, that fact is output to the outside.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor memory device of the present invention as a dynamic random access memory (one word consists of one bit).
FIG. 3 is a block diagram showing the (I+4 configuration) of all cases when implemented in D-RAM.

In the figure, reference numeral 10 denotes a memory cell array in which a plurality of dynamic memory cells (not shown) are arranged in rows and columns. In this memory cell array 10, n memory cells for one column are simultaneously selected according to the decoded output of the row decoder 11, and the stored data of these n memory cells is supplied to the sense amplifier 12. This sense amplifier I2 is provided with n sense amplifiers (not shown) corresponding to one row of memory cells of the memory cell array 10, and one cell data sensed by these n sense amplifiers is The selection is made according to the decoded output of the column decoder 13. Further, L4 is a data output buffer. This data person output buffer! 4, in the data read operation, the selected one cell data is transferred to D.
It is outputted to the outside as out, and during a data write operation, data from a data multiplexer 15, which will be described later, is supplied to a corresponding sense amplifier of the sense amplifier 12. In the data write operation, data is then written to the corresponding cell in O in the memory cell array.

That is, any one memory cell in the memory cell array IO is selected based on each decode output of the row decoder 11 and column decoder 13, and one bit of data is read out via the data output buffer 14; Or writing is performed.

The row decoder 11 and column decoder 13 are supplied with an address output from the address buffer/multiplexer 1B. This address buffer/multiplexer 1B receives an external address Add (not shown) consisting of a multi-bit row address and column address input in a time-division manner via several external terminals, and an external address Add generated by an address counter 17. The address buffer/multiplexer 1B selects one of the external address Add and the internal address based on a control signal from a self-diagnosis control circuit 18, which will be described later, and outputs the selected address. An address of a complementary level is generated from and supplied to the row decoder 11 and column decoder 13.

The data multiplexer 15 is supplied with external data Din and internal data for self-diagnosis generated by a write data generating circuit 19, which will be described later, in parallel via an external terminal (not shown). The data multiplexer 15 selects either the external data Din or the internal data based on a control signal from a self-diagnosis control circuit 18, which will be described later, and supplies the selected data to the data output buffer 14.

During the self-diagnosis operation, the address counter 17 sequentially generates the internal address consisting of a plurality of bits of row address and column address based on a control signal from a self-diagnosis control circuit 18, which will be described later. Further, during the self-diagnosis operation, the write data generation circuit 19 sequentially generates the internal data to be written to the bipedal memory cell array IO based on a control signal from the self-diagnosis control circuit 18, which will be described later.

20 is a fault diagnosis/failure signal generation circuit. This circuit 2
0, the above data output cover rough 7 is displayed during self-diagnosis operation.
Read data read from the memory cell array IO and internal data from the write data generation circuit 19 selectively output from the data multiplexer 15 are supplied via the memory cell array 14. The fault diagnosis/failure signal generation circuit 20 then compares both data, and when the two data do not match, it is assumed that a defective cell exists in the memory cell array 10, and a fault signal generation circuit 20 detects a fault to notify the outside of the memory cell array 10. Generates a signal Fail and outputs it to the outside.

The self-diagnosis control circuit 18 starts a self-diagnosis operation upon receiving a start signal from a start-up control circuit 21 to be described later, and after starting the self-diagnosis operation, the address counter 17, write data generation circuit 19, and address buffer/multiplexer 1
B. A control signal is supplied to the data multiplexer 15 and the fault diagnosis/failure signal generation circuit 20 to control the operation of each circuit.

The startup control circuit 21 includes a column address strobe signal CA used in normal operation as a D-RAM.
S, row address strobe signal RAS.

Write enable signal W E and the above external address Ad
d are each supplied via an external terminal.

The activation control circuit 21 outputs an activation signal to the self-diagnosis control circuit 18 when the input order, level, etc. of the various input control signals meet certain conditions.

Next, the operation of the storage device configured as above will be explained.

First, normal operations such as writing and reading data as a RAM are performed using RASSCAS,
This is performed based on various control signals such as WE.

Next, when performing a self-diagnosis operation, various control signals such as "bilateral RAS, CAS, WE, etc." supplied from the outside and an external address signal Add are inputted under predetermined conditions. For example, as shown in the timing chart of Figure 2, during normal operation, RAS is first lowered to the "0" level,
After this, CAS is lowered to the "0" level. First, CAS is lowered to the "0" level, and then RAS is lowered to the mO" level. Then, when RAS is at the "0" level, WE is set to "0". In addition, RAS and WE
When both are at “0” level, external address signal Add
An arbitrary 2-bit signal (Ai.

By setting Aj) to (0, 1), the startup control circuit 21 senses that the self-diagnosis operation is to be performed and generates a startup signal.

When this activation signal is input, the self-diagnosis control circuit 18 starts a self-diagnosis operation, and the self-diagnosis control circuit 18 starts a self-diagnosis operation for the address counter 17, write data generation circuit 19, address buffer/multiplexer 1B, data multiplexer 15, and fault diagnosis/fault signal generation circuit 20. and supply control signals. By being supplied with this control signal, the address counter 17 sequentially generates an internal address consisting of a row address and a column address for selecting all the memory cells in the memory cell array 10, and the write data generation circuit 19 For example, "0" level data is generated continuously at the beginning. During this self-diagnosis operation, the 2-bit external address (At, Aj) is set to (1, 1).

On the other hand, by supplying a control signal from the self-diagnosis control circuit 18, the address buffer/multiplexer te
selects the internal address generated by the address counter 17 and supplies it to the row decoder 11 and column decoder 13. Further, the data multiplexer 15 selects the internal data generated by the write data generation circuit 19 and supplies it to the data output buffer 14. Here, in the first cycle, the data output buffer 14 is set to data write mode. Therefore, "0" level data is sequentially written into each memory cell selected by the row decoder 11 and column decoder 13.

Then, in the next cycle after writing of "0" level data to all memory cells in the memory cell array 10 is completed, the data output buffer 14 is set to the data read mode, and the address counter 17 is set to the data read mode. Internal addresses consisting of row addresses and column addresses for selecting all memory cells in the memory cell array 10 are generated sequentially from the beginning again. In this cycle, the cell data sequentially read from each memory cell via the data output buffer 14 and the write data generation circuit 19 selected by the data multiplexer I5 are processed.
The failure diagnosis/failure signal generation circuit 20 sequentially detects coincidence or mismatch with the "0" level data from the fault diagnosis/fault signal generation circuit 20. Here, the failure diagnosis/failure signal generation circuit 20 does not output the failure signal Fail when the read data from the memory cell and the data from the write data generation circuit 9 match. On the other hand, if the read data from the memory cell and the data from the write data generation circuit 9 do not match, a failure signal Fail is output at a predetermined timing.

In the next cycle, the write data generation circuit I9 continuously generates "1" level data, and the "1" level data is written to and read from all memory cells in the same manner as above, and the data is Depending on the detection results,
A failure signal Fail is output at a predetermined timing.

When the detection of all cells is completed, as shown in the timing chart of Fig. 2, CAS is lowered to "0 level", RAS is lowered to "0# level", and both RAS and WE are set to "0" level. At this time, by setting the 2-bit external address signal (Ai, Aj) to (0, 0), the startup control circuit 21 senses that the self-diagnosis has been completed, and thereby the self-diagnosis control circuit 18 stop the operation.

Here, MOS dynamic RAM and static R
In actual use when multiple semiconductor memories such as AM are incorporated in a system, when each memory becomes defective, it has been mostly due to a single bit defect in the memory cell array IO,
It is known that failures such as single row failures and single column failures are caused by deterioration of the cell oxide film or disconnection. That is, the characteristics of the transistor deteriorate with the passage of time, and defects such as those that operate as a RAM but eventually no longer meet specifications rarely occur. Therefore, for failure checking under actual use conditions, complicated tests such as those used during chip selection are no longer necessary. Therefore, as in the above example, it is possible to simply write 1" level data or "0" level data to all memory cells under standard conditions, and check whether this can be read out correctly. Even something as simple as doing so is both necessary and sufficient.

Therefore, when configuring a system using a plurality of storage devices of the above embodiments, the signals RAS, CAS, WE, and external address signal Add must be supplied in parallel to all semiconductor memories under predetermined conditions. This allows all memories to perform self-diagnosis operations at the same time. Therefore, compared to the case where each memory is tested one by one in series as in conventional equipment, the time required for fault diagnosis of the memories in the system is reduced, where N is the number of memories used in the system. For example, it can be shortened to 1/H of the conventional one. This not only shortens the time required for system testing, but is also particularly effective for initial inspections at the start of operation of systems using this memory, allowing initial inspections to be performed without having to wait an extremely long time. This greatly improves the work efficiency of the user, and also allows frequent inspections, ensuring high reliability of the system at all times.

FIGS. 4 to 6 are circuit diagrams showing specific configurations of each part of the device of the above embodiment.

FIG. 4 shows a specific configuration of the address counter 17 and write data generation circuit 19.

Here, both of the above circuits are composed of set-reset type flip-flops or frequency divider circuits connected in series so that the Q and Φ output signals of the previous stage are supplied as inputs of the latter stage.
The first stage counter 30□ is configured with 0 counters 301 to 302o, and the first stage counter 30□ receives, for example, a signal CA as an input signal during the self-diagnosis operation in the self-diagnosis control circuit 18.
Clock signals CK and CK generated based on S are supplied.

The counters 30 at each stage use this clock signal CK.

The frequency of CK is divided into 1/2 sequentially. The 9-bit output signals of the counters 301 to 309 from the first stage to the ninth stage are the row addresses aOR and aOR of the internal addresses.
or a3R, a8R as the previous address buffer/
The 9-bit output signals of the counters 30□0 to 30□8 in the 10th to 18th stages, which are supplied to the multiplexer 16, are the column addresses aOc,
It is supplied to the address buffer/multiplexer 16 as arc to a8C, a8C. Further, the output signal of the 19th stage counter 3019 is used as a write/read signal W/R for setting the data write mode and read mode in the data output buffer 14. Furthermore, the 20th stage counter 302o corresponds to the write data generation circuit 19, and its output signal is supplied to the data multiplexer 15 as the internal data D.

In a circuit with such a configuration, before the self-diagnosis control circuit 18 is activated, the Q output signals of all the flip-flops 30 are at the "0" level, and the Φ output signals are at the "1" level. All bits of the 9-bit internal row address and internal column address are both at the "0" level, the write/read signal W/R is also at the "0" level, and the data output buffer 14 is placed in the data write mode. Furthermore, the internal data generated by the write data generation circuit 19 is at the "0" level.

When the self-diagnosis control circuit 18 is activated in this state and generates clock signals CK and CK, the internal row addresses first change sequentially. This internal address is sent to the row decoder 1 via the address buffer/multiplexer 16.
1 and the column decoder 13, the memory cells in the memory cell array 10 select the current data from among the n cells in one row corresponding to all the bits of the column address or the "0" level. Those corresponding to the row addresses are selected one by one. At this time, the data D written to each memory cell is at the "0# level. Then, when the row address and column address complete one cycle, the write/read signal W/R becomes the "1" level, and the data The human output buffer 14 is put into the data read mode. Since the self-diagnosis control circuit 18 generates the clock signals CK and CK also in this data read mode, the internal row addresses are first changed sequentially in the same manner as above. By supplying this internal address to the row decoder 11 and column decoder 13, data is sequentially read from the memory cells in the memory cell array 10 to which "0° level data has been written in advance," and fault diagnosis/fault is performed. The signal is supplied to the signal generation circuit 20. At this time, the 20th stage counter 302o corresponding to the write data generation circuit 19
The internal data generated by
The signal is supplied to the fault diagnosis/failure signal generation circuit 20 via.

Therefore, this circuit 20 detects coincidence or mismatch between both data, and when detecting mismatch, outputs a failure signal Fail at a subsequent predetermined timing.

When the row address and column address cycle again in this state, the write/read signal W/R goes back to the "07 level" and this time, the 20th stage counter 302o
The output data D changes from the "0#" level to the "1" level. That is, this puts the data output buffer 14 into the data write mode again, and the internal data written at this time becomes the "1" level. .Similarly to the above, the °l° level data is applied to all memory cells in the memory cell array 10, and when the row address and column address complete one cycle, the write/read signal W/R becomes the "0" level. , the fault diagnosis is performed again on the "1" level data in the fault diagnosis/fault signal generation circuit 2.
It is done with 0.

In this way, in this circuit, writing and reading of 10'' level data and writing and reading of 1@level data are performed for all cells in the memory cell array 10 during the period in which the row address and column address circulate four times.
Defective cells are checked when reading data. Normally, a dynamic RAM is provided with a refresh counter to refresh memory cells, and this refresh counter selects all memory cells in the 11th column in the memory cell array IO, and
This is performed by supplying cell data for columns to the sense amplifier 12 in parallel. Therefore, this refresh counter only needs to generate a row address, so
A part of the address counter 17, that is, the outputs of the flip-flops 30 to 309, can be used for refreshing without providing an independent refresh counter.

FIG. 5 shows the multiplexer portion of the address buffer/multiplexer 16 or the data multiplexer 15.
This shows the specific lj~ composition for each 1 bit. This circuit has one end of the external address Add.
MO to which bits or external data D1n is supplied
S switch 4L and one bit of internal address a generated by the address counter 17 or internal data D generated by the write data generation circuit 19 at one end.
a MOS switch 42 which is supplied with a NOR gate circuit 43 to which is supplied a signal T generated at step 18 indicating whether or not the self-diagnosis operation period is in progress, the clock signal φ and the signal T;
A NOR gate circuit 44 is supplied with a signal T having an opposite phase. And one NOR gate circuit 43
The output of the other NOR gate circuit 44 is supplied to the gate of the MOS switch 41, and the output of the other NOR gate circuit 44 is supplied to the gate of the MOS switch 42.

In this circuit, during the self-diagnosis operation period, the signal T or “
The signal T is set to 1" level and the signal T is set to 10" level. Therefore, the output of one NOR gate circuit 43 is always kept at the "0" level regardless of the clock signal φ, and the hi o s switch 41 remains closed. The output of the other NOR gate circuit 44 is set to "1" level every time the clock signal φ is set to "0" level, and in synchronization with this, the MOS
Switch 42 is opened. Therefore, during the self-diagnosis operation period when the signal T is at the "0" level, the address buffer/multiplexer 1B selects the internal address a, and the data multiplexer 15 selects the internal data D. Also, the signal T is at the "0" level. during the normal operating period,
That is, during the period of writing external data Din or reading cell data and outputting it as DouL, the 7-address buffer/multiplexer 16 outputs the external address Ad.
d and the data multiplexer 15 selects the external data Din.

FIG. 6 shows a specific configuration of the fault diagnosis section of the fault diagnosis/failure signal generation circuit 20. As shown in FIG.

This circuit is an exclusive OR gate circuit to which read data RD from a memory cell is supplied as one input data, and data D from the write data generation circuit 19 is supplied as the other input data. The circuit is made up of 50 and 14 circuits, i.e.
In this circuit, if the levels of the data RD and D of both people are the same, the output E of the exclusive OR gate circuit 50 is "0".
If the levels of the data RD and D are different, the output E of the exclusive OR gate circuit 50 becomes the "1" level.

If the output E of the gate circuit 50 reaches the "1" level even once, the fault diagnosis/failure signal generation circuit 2o detects the presence of a defective cell in the memory cell array IO after detecting all the cells. The fault signal Fall is generated assuming that the fault signal is

Although this embodiment device can achieve the above-mentioned great effects, only a small amount of circuitry is required compared to the conventional device, and therefore, circuit design is relatively easy. Moreover, the increase in chip area when integrated into a circuit can be relatively small.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the device of the above embodiment, the memory cell array 1 is
First write predetermined data to all cells in 0, then
Although data is read out, data may be written in one memory cell and read out immediately after that.

In this case as well, first write “0” level data,
Next, read this out for all cells, then write 12-level data, and then read it out for all cells, or write 0-level data, read it, and then It is possible to use a method in which the operation of writing and reading data at the "1" level is sequentially performed for each cell, and this operation is performed for all cells.

In addition, although the write data generation circuit 19 has explained the case where it continuously generates "0" level data and "1# level data," this means that all the data to be written at the time of self-diagnosis is "0" level and "1" level data. Instead of a uniform pattern of levels, a checkerboard pattern in which "0" level data and "1" level data appear alternately, a so-called checkerboard pattern, etc. can also be used.

FIG. 7 is a circuit diagram showing a specific configuration of the write data generation circuit 19 when generating the checkerboard pattern as described above. This circuit is an exclusive logic circuit to which an internal column address aOc of the least significant bit generated by the address counter 17 shown in FIG. 4 and an internal row address aOR of the least significant bit also generated by the address counter 17 are supplied. Sum gate circuit 61 and this circuit 6
1 and the data D generated at the final stage flip-flop 302o of the address counter 17 shown in FIG.
and an exclusive OR gate circuit 62 to which is supplied.

In this circuit, in the initial state, the data D generated by the counter 302o is "0 level" and the column address aOc
and the row address aOR are both at the "0" level. Therefore, the data initially output from the gate circuit 62 is “
0” level.

Next, when the row address aOR reaches the "1" level, the output of the gate circuit 61 is inverted to the "1 degree" level, and following this, the output data of the gate circuit 62 is inverted to the "1" level.Hereinafter, the address Each time the clock signal CK is supplied to the counter 17, the row address aOR is alternately inverted, so that the internal data D is also inverted bit by bit.

Then, when the row address goes around and the row address changes again from the beginning, the lowest bit aOC of the column address is inverted to the "1" level, so the gate circuit in this column (row) The data initially output from 62 is "1m level data. Next, when the row address aOR becomes "1# level", the gate circuit 62
The output data of is inverted to "0" level. Thereafter, each time the clock signal CK is supplied to the address counter 17, the row address aOR is alternately inverted, so that the internal data D is also inverted bit by bit.

Then, data is written in the first column and the next column with the data alternated.

As a result, by using the output data from this write data generation circuit, self-diagnosis can be performed using a checkerboard pattern.

Further, in the above embodiment, the case where the failure signal Fail is outputted after all the cells are detected has been described, but it may be outputted at the time when a data mismatch is detected. Further, in that case, the subsequent self-diagnosis operation may be canceled.

Furthermore, in the above embodiment, the data to be written into the memory cell during self-diagnosis is generated in the write data generation circuit 19 provided inside the storage device, but this may be supplied as data Din from outside the storage device. You may also do so. Similarly, although the case has been described in which the address used to address the memory cells during self-diagnosis is generated by the address counter 17 arranged inside the storage device, this address is supplied from outside the storage device as the address Add. You may also do so. By using external addresses in this manner, it is possible to obtain the effect that defective addresses can be immediately recognized.

Furthermore, in the above embodiment device, the case of a 1-bit write/read dynamic RAM has been explained, but this is not limited to a 1-bit configuration, but can also be implemented later with a 4-bit or 8-bit configuration. Needless to say. In addition to dynamic RAM, static RAM
Great effects can be obtained even when applied to AM.

Furthermore, the input conditions for sensing the start and end of the self-diagnosis operation in the startup control circuit 21 may not necessarily be based on the timing chart shown in FIG. As such, the write enable signal W is only used at the start and end of the self-diagnosis operation.
E is lowered to the "0" level, and at this time the 2-bit external address signals (Ai, Aj) are set to (0, 1) or (1).
By setting ゜1), it is possible to do this.

[Effects of the Invention] As explained above, according to the present invention, it is possible to automatically determine whether or not a defect has occurred in each internal cell, thereby improving the system using this memory 'ji IXj. Accordingly, it is possible to provide a semiconductor memory device in which the check time at the start of operation can be significantly shortened, and the system can be started up quickly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
2 and 3 are timing charts showing different operations of the above embodiment device, respectively. FIGS. 4 to 6 are four-way diagrams showing the specific configuration of a part of the above embodiment device, respectively. FIG. 7 is a circuit diagram according to a modified example of the invention. IO...Memory cell array, 11...Row decoder, 12...Sense amplifier, 13...Column decoder, 14...Data output buffer, 15...Data multiplexer, 16...Address buffer /Multiplexer, 17...Address counter, 18...Self-diagnosis control circuit, 19...Write data generation circuit, 2
0...Fault diagnosis/fault signal generation circuit, 21...Start control circuit, 30...Counter, 41°42...M
OS switch, 43.44...Nor gate circuit, 50
, 61.62... exclusive OR gate circuit.

Claims (1)

[Claims] 1. A memory cell array having a plurality of memory cells;
memory cell selection means for selecting one or more memory cells in the memory cell array; and data for controlling writing of data to the memory cell selected by the memory cell selection means or controlling reading of data from the selected memory cell. read/write control means; and after activation, the data read/write control means sequentially writes predetermined data to each memory cell in the memory cell array, and reads the same after writing, so that an error occurs in the read data. self-diagnosis control means that performs self-diagnosis by detecting whether the A semiconductor memory device comprising activation control means for activating the self-diagnosis control means. 2. The self-diagnosis control means includes an address counter that sequentially generates addresses for addressing memory cells in the memory cell array, a write data generation circuit that generates data to be written to the memory cells, and a write data generation circuit that generates data to be written to the memory cells. a data comparison circuit that compares data written to the memory cell with data read from the memory cell to which the data has been written, and a control circuit that controls the operations of the address counter, write data generation circuit, and data comparison circuit after startup. A semiconductor memory device according to claim 1, comprising: 3. Each memory cell in the memory cell array is composed of a dynamic type cell, and a part of the address counter is configured to generate a refresh address used when performing a refresh operation of each of these memory cells. A semiconductor memory device according to claim 2. 4. The self-diagnosis control means according to claim 1, wherein the self-diagnosis control means is provided with a failure signal output means for outputting a message to the outside when an error has occurred in the data. Semiconductor storage device. 5. The semiconductor memory device according to claim 1, wherein the predetermined signal detected by the activation control means includes some or all of the external address signals. 6. Claim 2, wherein the lower digits of the address counter are used as a row address for addressing the memory cell, and the upper digits are used as a column address for addressing the memory cell. 2. The semiconductor storage device described in . 7. The semiconductor memory device according to claim 6, wherein the write data generation circuit is configured to be supplied with the most significant digit output of the address counter. 8. The semiconductor memory device according to claim 2, wherein the address counter is composed of a plurality of set/reset type flip-flops connected in series. 9. The semiconductor memory device according to claim 2, wherein the address counter is constituted by a plurality of frequency dividing circuits connected in series. 10 The activation control means detects a column address strobe signal and a row address strobe signal input via the external terminal, detects that the column address strobe signal is input before the row address strobe signal, and The semiconductor memory device according to claim 1, which activates a self-diagnosis control means. 11 The activation control means detects a column address strobe signal, a row address strobe signal, and a write enable signal inputted via the external terminal, and when the column address strobe signal is inputted before the row address strobe signal, 2. The semiconductor memory device according to claim 1, wherein said self-diagnosis control means is activated based on the level of a write enable signal. 12 The activation control means detects a column address strobe signal, a row address strobe signal, a write enable signal, and an external address signal input via the external terminal, and detects that the column address strobe signal is input before the row address strobe signal. 2. The semiconductor memory device according to claim 1, wherein the self-diagnosis control means is activated when external address signals are set to a predetermined combination of levels during a period when a write enable signal is at a predetermined level. .