JP2006268919A - Built-in self test circuit of memory and self test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable test contents to be changed even after production without restricting test contents in a built-in self test of a memory. <P>SOLUTION: A register circuit 106 provided in the built-in self test circuit of the memory changes test contents by performing setting change of an address generating circuit 101, an input data generating circuit 102, a control signal generating circuit 103, and an expected value data generating circuit 104 based on test setting data td received from the outside. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to the field of semiconductor integrated circuit device testing, and more particularly to a memory built-in self-test circuit and self-test method.

  In recent years, as the system integration into semiconductor integrated circuits progresses, the number of memories mounted on one semiconductor integrated circuit has increased. The test for these memories uses a direct memory access method in which a signal connected to a port of a conventional memory is extracted to an external terminal, a signal is input from the external terminal to the memory, and a signal from the memory is output to the external terminal to perform the test. Has been. However, with this method, the number of external terminals is insufficient to test multiple memories at the same time, and it is difficult to test at actual speed due to signal delay from the external terminals to the memory. A built-in self test circuit (BIST) of a memory has been put in an integrated circuit.

  In the memory built-in self-test circuit, an address, data, and a control signal are generated inside the semiconductor integrated circuit and input to the memory, and a determination result obtained by comparing the output result of the memory with the expected value data is output to the external terminal.

  A conventional memory built-in self-test circuit and self-test method will be described below.

  FIG. 9 shows a built-in self-test circuit of a conventional memory, where 10 is a memory, 11 is a column address and a row address, and an address generation for outputting the generated column address and row address to the memory 10 is shown. The circuit 12 generates input data and outputs the generated input data to the memory 10, and 13 generates write and read control signals and outputs the generated control signals to the memory 10. A control signal generation circuit 14 that generates and outputs expected value data for comparison with output data output from the memory 10 during the test, and 15 is output from the memory 10. The output data and the expected value data output from the expected value data generation circuit 14 are input, and the output data and the expected value data are compared. A data comparator for outputting a test result obtained by.

  The operation of the built-in self-test circuit of the memory configured as described above will be described below.

  First, a memory test is automatically started by receiving a test start signal from an external terminal of the semiconductor integrated circuit. When a write test to the memory 10 is performed, a signal for performing the write test is automatically generated from the address generation circuit 11, the input data generation circuit 12, and the control signal generation circuit 13, and is input to the input port of the memory. . When a read test from the memory 10 is performed, a signal for performing the read test is automatically generated from the address generation circuit 11 and the control signal generation circuit 13 and is input to the input port of the memory and expected value data. The generation circuit 14 also automatically generates an expected value data signal, and the generated expected value data is output to the comparator 15. The output data output from the memory 10 by the write or read test and the expected value data output from the expected value data generation circuit 14 are compared by the comparator 15, and the test result is output to the external terminal of the built-in self test circuit of the memory. Is output. A series of these operations is automatically performed when a test start signal is input.

  Since testing is performed automatically in this way, the necessary memory test algorithm is determined at the time of circuit design, and the address signal, input data signal, control signal and expected value data signal input to the memory are combined circuits. As long as the test start signal is input, the necessary tests are performed and only the result is returned.

  The built-in self-test of the memory shown here is a valuable configuration and method in terms of testability, but there is a problem that the algorithm cannot be changed after commercialization. With the conventional direct memory access method, the memory core port is connected to the external terminal, and the test contents can be freely set, such as the test of only a part of the address area and the test algorithm can be changed arbitrarily. When a memory test is performed using a self test, all addresses can be tested with a predetermined algorithm, and the result can only be seen, and a detailed analysis is performed with an algorithm other than the predetermined one. Inappropriate for

  In response to this problem, efforts are being made to perform high-quality tests while being built-in tests. For example, in the technique described in Patent Document 1, although an algorithm is determined in advance, a mechanism that can execute various memory tests with a predetermined test pattern within a range of the algorithm determined with a simple circuit configuration is realized. ing.

Patent Document 2 describes a microinstruction control method as means for changing the test contents. In this technique, a predetermined number of test algorithm instructions are stored in advance in a built-in read-only memory, and by changing the test algorithm instructions within the predetermined number range, an address signal input to the memory, an input The signal generated as the data signal and the control signal is changed.
JP 2000-76894 A Japanese Patent Laid-Open No. 10-69799

  However, since the method of increasing the memory test pattern with the simple circuit configuration of Patent Document 1 described above cannot be changed to other than a test pattern that can be implemented with a simple circuit configuration prepared in advance after commercialization, It is impossible to test for defects after commercialization.

  In the microinstruction control method, a read-only memory for storing test algorithm instructions is required separately, and a microinstruction to be written in the read-only memory needs to be created in advance. In this microinstruction control system, the number of test algorithm instructions stored in the read-only memory is inevitably limited to specific types of tests with high importance in order to reduce the circuit scale and cost. Therefore, easy debugging with relatively low importance is not possible. If it is desired to change the test contents other than those stored in the read-only memory prepared separately, it is necessary to re-create the semiconductor integrated circuit again in order to re-create the read-only memory.

  As described above, the memory mounted on one semiconductor integrated circuit is large-scale and tends to increase in number, and since all the memories do not operate correctly from the beginning of the design, the necessity for the debug function is increased. In spite of this, the test content has been limited in the past, and the test content could not be changed after commercialization.

  In order to solve the above-described problems, an object of the present invention is to make it possible to change test contents even after commercialization without limiting the test contents and without recreating a semiconductor integrated circuit.

  In order to achieve the above object, according to the present invention, a built-in self-test circuit includes a register circuit that changes test settings based on test setting data input from the outside.

  In other words, the built-in self-test circuit for a memory according to the first aspect of the present invention is incorporated in a semiconductor integrated circuit having a memory and tests the function of the memory in the built-in self-test circuit for testing the function of the memory. Receiving test setting data input from outside the built-in self-test circuit of the memory, and inputting an output value of the test setting data to the test signal generating means And a register circuit for changing the content of the test by changing the test signal generated by the test signal generating means.

  According to a second aspect of the present invention, in the built-in self-test circuit of the memory according to the first aspect, the test signal generating means receives an output value from the register circuit and controls an address on the memory. An address generation circuit for generating a signal, an output value from the register circuit, an input data generation circuit for generating test input data to be written to the memory, an output value from the register circuit, A control signal generation circuit for generating a control signal for controlling writing and reading to the memory; and an output value from the register circuit, and the memory by the test using the address control signal, the input data, and the control signal An expected value data generation circuit for generating expected value data for comparison with output data output from And wherein the door.

  According to a third aspect of the present invention, in the built-in self-test circuit for a memory according to the first or second aspect, the register circuit includes an address register for address setting, an input data register for input data setting, and a control A control signal register for signal setting and an expected value data register for setting expected value data are provided.

  According to a fourth aspect of the present invention, in the built-in self-test circuit of the memory according to the second aspect, the address generation circuit and the input are based on a reference clock signal input from the outside of the built-in self-test circuit of the memory. A clock generator that generates at least one clock signal to be input to each of the data generation circuit, the control signal generation circuit, and the expected value data generation circuit is provided.

  According to a fifth aspect of the present invention, in the built-in self test circuit for a memory according to the third aspect, the register circuit includes the address register, the input data register, the control signal register, and the expected value data. A shift register that receives the test setting data from the outside, comprising register data to be set in a register and a register identifier for identifying one of the four setting registers to set the register data And, based on the register identifier included in the test setting data received by the shift register, identifies one register from the four setting registers for setting the register data, and is paired with the register identifier. The register setting data included in the test setting data Register identification processing for registering each of the four setting registers, register setting data output from the register identification means, and temporarily storing the register setting data And a plurality of predetermined buffers for outputting the temporarily stored register setting data to each of the four setting registers at the end of one test being executed. .

  According to a sixth aspect of the present invention, there is provided a memory built-in self test method for testing a function of a memory of a semiconductor integrated circuit having a memory, wherein a plurality of paired register identifiers and register setting data are provided. A test setting data receiving step for receiving test setting data included from the outside, an address register for address setting based on the register identifier included in the test setting data received in the test setting data receiving step, and input data 1 for setting the register setting data among four setting registers including a setting input data register, a control signal register for setting a control signal, and an expected value data register for setting expected value data Identifying one register and out of the four setting registers A register identifying step for outputting the register setting data, the register setting data output in the register identifying step being temporarily stored, and the register setting data being temporarily stored for the one separate register A buffer step of outputting the register setting data temporarily stored to each of the four setting registers at the end of one test executed in the meantime.

  As described above, in the first to sixth aspects of the invention, the test signal output from the test signal generating means is changed by the register circuit inside the built-in self-test circuit of the memory based on the test setting data received from the outside. The test contents can be changed from the outside after commercialization without re-creating the semiconductor integrated circuit.

  In the inventions of claims 5 and 6, the register setting data extracted from the test setting data is temporarily stored in the buffer. Therefore, after one test is completed, it is only necessary to load the register setting data stored in the buffer. The next test can be started immediately.

  As described above, according to the first to sixth aspects of the invention, the test signal output from the test signal generating means can be changed by the internal register circuit based on the test setting data input from the outside. Detailed debugging can be performed without any restrictions on the contents of the test according to a defect that has occurred after conversion, and there is no need to recreate the built-in self-test circuit.

  In particular, according to the fifth and sixth aspects of the invention, the register setting data obtained from the test setting data is temporarily stored in the buffer, so that the register setting data stored in the buffer is loaded after one test is completed. By doing this, the next test can be started immediately, and the time for register setting can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration example of a built-in self-test circuit according to an embodiment of the present invention. The built-in self-test circuit for the memory 100 in FIG. 1 generates an address control signal for controlling writing and reading of data, outputs the generated address control signal to the memory 100, and test input data. The input data generation circuit 102 that outputs the generated input data to the memory 100, a control signal that controls the writing and reading of the input data to the memory 100, and the generated control signal to the memory 100 Expected value to be compared for verifying whether the data read from the memory 100 is correct by the control based on the control signal generation circuit 103 to be output to the memory and the test based on the input address control signal, input data and control signal An expected value data generation circuit 104 for generating data, and the memory 10 Comparing the read data with the expected value data from, a data comparator 15 to output the comparison result as a result of the built-in self test of the memory.

  In order to change the contents of the test, in addition to the above configuration, the register circuit 106 that receives the test setting data td input from the outside at the external terminal 200, and the reference clock signal ck input from the outside are connected to the external terminal. And a clock generator 107 received at 201.

  The register circuit 106 inputs an output value to be output based on the test setting data td input to change the test content from the outside, to the test signal generating means 300. Here, the test signal generation means 300 includes an address generation circuit 101, an input data generation circuit 102, a control signal generation circuit 103, and an expected value data generation circuit, and the output values output from the register circuit 106 are generated by these. Input to circuits 101-104. Thereby, a setting for generating an address control signal in the address generation circuit 101, a setting for generating input data in the input data generation circuit 102, a setting for generating a control signal in the control signal generation circuit 103, and Settings for generating expected value data in the expected value data generation circuit 104 are changed. Then, by changing the setting of each of the generation circuits 101 to 104, the test signal including the address control signal, input data, control signal, and expected value data input to the memory is changed, and the test contents are changed. .

  The clock generator 107 generates at least one clock signal based on a reference clock signal ck input from the outside. The generated clock signal is generated by an address generation circuit 101, an input data generation circuit 102, and a control signal generation. It is input to each of the circuit 103 and the expected value data generation circuit 104.

  Here, the configurations of the address generation circuit 101, the input data generation circuit 102, the control signal generation circuit 103, and the expected value data generation circuit 104 will be described in detail.

  First, the address generation circuit 101 and the address setting register 202 will be described with reference to FIG. Here, the address setting register 202 is a register provided for address setting in the configuration of the register circuit 106 of FIG.

  FIG. 2 shows an address generation circuit 101, an address setting register 202, and a clock signal generator 107. In the present embodiment, the clock signal generator 107 generates three clock signals based on a reference clock signal ck input from the outside, and these three clock signals are input to the address generation circuit 101.

  The address generation circuit 101 includes a column address counter 110 that outputs a column address for writing and reading input data for self-test to and from the memory 100, and a row address counter 111 that outputs a row address.

  Of these counters 110 and 111, a clock signal or a carry signal output from the counter 111 is input to the counter 110, and a clock signal or a carry signal output from the counter 110 is input to the counter 111. Is done. Here, selectors 113 and 114 are provided to select one from the clock signal and the carry signal. That is, the column address counter 110 includes a selector 113 that outputs a clock signal or carry signal selected from a plurality of clock signals output from the clock signal generator 107 and a carry signal output from the row address counter 111. The row address counter 111 includes a selector 114 that outputs a clock signal or carry signal selected from a plurality of clock signals output from the clock signal generator 107 and a carry signal output from the column address counter 110. It is done.

  In this manner, based on the clock signal or carry signal output from the selectors 113 and 114, the column address is output from the column address counter 110, and the row address is output from the row address counter 111.

  On the other hand, the address setting register 202 sets an initial value of the row address, and inputs the set initial value to the row address counter 111 of the address generation circuit 101, and an initial value of the column address. And a column address initial value setting register 116 for inputting the set initial value to the column address counter 110, and an address setting register 117 for setting a column address and a row address. The address setting register 117 controls the signal selection operation of the selectors 113 and 114 in the address generation circuit 101 by a select signal, and controls the column address counter 110 and the row address counter 111 by an UP / DOWN signal. A column address and a row address are output from the address generation circuit 101.

  With such a configuration, the column address and the row address are individually controlled, and it is possible to give a degree of freedom in address setting.

  The clock signal generator 107 outputs a frequency-divided clock signal, an L fixed signal, an H fixed signal, or the like as necessary. For example, when data is written to and read from the same address, a clock signal divided by two from the clock signal output from the clock signal generator 107 is selected by the selectors 113 and 114, and the column address counter 110 and the row address counter are selected. 111 is input.

  The column address counter 110 and the row address counter 111 load the values of the column address initial value setting register 116 and the row address initial value setting register 115, respectively, at the start of the test, and specify a memory array to start the test execution. Here, FIG. 3A shows the memory of the column 8 array and the row 16 array. For example, as shown in FIG. 3A, the column addresses 0 to 7 and the row addresses 5 to 6 are used. To test a part of the test area TA, the column address initial value setting register 116 is set to 0 (default value), the row address initial value setting register 115 is set to 5, and the column address counter 110 is set to The address setting register 117 is set so that the reference clock signal ck is input and the row address counter 111 is input with the carry signal of the column address counter 110. Output signals of the column address counter 110 and the row address counter 111 are input to the column address port and the row address port of the memory 100, respectively. Access to the memory is performed in the direction of the arrow in FIG. 3A. These operations stop the input of the clock signal or turn off the test signal when the address advances to the array where the test is to be finished. End the test.

  Next, the input data generation circuit 102 and the input data register 203 will be described with reference to FIG. Here, the input data register 203 is a register provided for setting input data in the configuration of the register circuit 106 shown in FIG.

  4 shows an input data generation circuit 102, an input data register 203, a clock signal generator 107, a column address counter 110, and a row address counter 111 of the address generation circuit 101. In the present embodiment, the clock signal generator 107 generates three clock signals based on a reference clock signal ck input from the outside, and these three clock signals are input to the input data generation circuit 102. Further, in order to set the input data generation circuit 102, the input data register 203 includes an input data setting register 124 and three data registers 125 to 127.

  The input data generation circuit 102 includes a selector 128 that selects one of a plurality of clock signals output from the clock signal generator 107 under the control of the input data setting register 124, and three data registers 125 to 127 of the register circuit 106. And a selector 120 that selects one of the three pieces of data that are input from the control data by control of the clock signal selected by the selector 128.

  The input data generation circuit 102 is further provided with two operators 122 and 123 and a selector 121. Here, the two operators 122 and 123 are both two-input EXOR operators, and constitute a three-input EXOR in which the output of the operator 123 is one input of the operator 122. The LSB values of the values output from the column address counter 110 and the row address counter 111 of the address generation circuit 101 are input to the two input terminals of the operator 123. The remaining one input terminal of the operator 122, that is, the remaining one input terminal of the three-input EXOR operator including the operators 122 and 123 is selected from the three data registers 125 to 127 by the selector 120. One data signal is input. In the 3-input EXOR operator, if the value “1” is an even number among the input values, the output value is “0”, and among the input values, the value “1” is If it is an odd number, the output value is “1”. Therefore, if the LSB of the column address and the row address is the same value, the output value of the 3-input EXOR operator consisting of the operators 122 and 123 is Depending on the output value of the selector 120, the operator 122 outputs the output value of the selector 120 as it is. On the other hand, if the column address and the row address have different LSB values, the output value of the operator 122 is a value obtained by inverting the output of the selector 120.

  The selector 121 selects one of the output value of the operator 122 and the output value of the selector 120 under the control of the input data setting register 124 of the input data register 203, and uses the selected value as input data for the memory 100. Output.

  Therefore, with this configuration, when it is desired to write a checker pattern as shown in FIG. 3B to the memory 100, for example, data 00 (all 8 bits are all 0) for at least one of the data registers 125-127. ), The selector 128 selects the reference clock signal ck, the selector 120 selects one of the data registers in which the data 00 is set, and the input data so as to select the output value of the operator 122. The selector 121 may be controlled by the setting register 124.

  Subsequently, the control signal generation circuit 103 and the control signal register 204 will be described with reference to FIG. Here, the control signal register 204 is a register provided for setting a control signal in the configuration of the register circuit 106 shown in FIG.

  FIG. 5 shows the control signal generation circuit 103, the control signal register 204, and the clock signal generator 107. In the present embodiment, the clock signal generator 107 generates four clock signals based on a reference clock signal ck input from the outside, and these four clock signals are input to the control signal generation circuit 103.

  The control signal generation circuit 103 includes a selector 130 that selects one of a plurality (four in this case) of clock signals output from the clock signal generator 107.

  Then, the control signal register 204 outputs a control signal for performing selection control of the selector 130 from the control signal setting register 131.

  One clock signal selected in this way is output from the control signal generation circuit 103 as a control signal for writing and reading test data to and from the memory 100.

  The access timing to the memory is described in the memory specification, and since only that timing needs to be realized, the necessary signal waveform is limited. At the time of writing and reading, the clock signal generator 107 generates an L signal (fixed to a value “0”), an H signal (fixed to a value “1”), a clock signal, and the like as necessary. Is selected by the control signal setting register 131. By using such a configuration, it is possible to generate various clock signals internally and diversify the contents written into the memory.

  Next, the expected value data generation circuit 104 and the expected value data register 205 will be described with reference to FIG. Here, the expected value data register 205 is a register provided for setting expected value data in the configuration of the register circuit 106 shown in FIG.

  FIG. 6 shows the expected value data generation circuit 104, the expected value data register 205 and the clock signal generator 107, and the column address counter 110 and the row address counter 111 of the address generation circuit 101. In the present embodiment, the clock signal generation circuit 107 generates three clock signals based on a reference clock signal ck input from the outside, and these three clock signals are input to the expected value data generation circuit 104.

  Here, the expected value data generation circuit 104 has substantially the same configuration as the input data generation circuit 102 shown in FIG. 4, and the function of the expected value data register 205 with respect to the expected value data generation circuit 104 is also the input of FIG. The input data setting register 124 in the data register 203 is replaced with the expected value data setting register 144 in FIG. 6, and the configuration in the expected value data generation circuit 104 is the same as that of the input data generation circuit 102 in FIG. Similarly, it is assumed that the selector 120 is replaced with the selector 140, the selector 121 is replaced with the selector 141, the selector 128 is replaced with the selector 148, the operator 122 is replaced with the operator 142, and the operator 123 is replaced with the operator 143. Therefore, description of these configurations is omitted.

  Expected value data, which is an output signal of the expected value data generation circuit 104, is input to the data comparator 15 shown in FIG. 1, and this expected value data is compared with the output data read from the memory 100 by the test, The comparison result is output outside the built-in self-test circuit of the memory.

  Here, the expected value data register 205 includes an expected value data setting register 144, and the data registers 125, 126, and 127 are used to store the expected value data, but the data written to the memory is read from the memory. Since there are many tests for reading, if the input data generation circuit 102 and the expected value data generation circuit 104 share the same data register, the number of necessary registers can be reduced. The register circuit 106 is set before or during the execution of the automatic memory test in which the memory 100 outputs the output data based on the address control signal, the input data, and the control signal.

  With the above-described configuration, the address generation circuit 101, the input data generation circuit 102, the control signal generation circuit 103, and the expected value data generation circuit 104 from the external terminal 200 of the memory built-in self-test circuit through the register circuit 106 in the test mode. Therefore, it is possible to set the test data in each of the generation circuits 101 to 104 and change the test contents before starting the test or during the test.

  When this embodiment is used, it is not necessary to individually input an address signal, an input data signal, and a control signal from the outside, so it is not necessary to consider the limitation on the number of terminals for these external signals, and a plurality of memories can be simultaneously stored. The built-in self-test that combines the advantages of built-in self-test that can be tested at high speed and the advantage of direct memory access that allows the test contents to be freely changed after commercialization can be easily realized with several registers and combinational circuits.

  Here, a further configuration of the register circuit 106 in the built-in self-test circuit of the memory will be described with reference to FIG. 7A and 7B are both provided in the register circuit 106. FIG.

  In the built-in self test of this memory, the row address initial value setting register 115, the column address initial value setting register 116, the address setting register 117, the input data setting register 124, the data registers 125 to 127, the control signal setting register 131, the expected value Since a plurality of registers such as the data setting register 141 are required, the test setting data td is set by the configuration of FIG.

  FIG. 7A illustrates a configuration including a shift register 150 and a buffer 151 included in the register circuit 106 illustrated in FIG. The shift register 150 receives the test setting data td from the outside, and loads the test setting data td received from the outside into the buffer 151. This loading is performed based on a load signal input from the outside. Here, each of the plurality of test setting data td stored in the buffer 151 includes register setting data for setting in a register and a register identifier for identifying a register for setting the register setting data. . As described above, the test setting data td input from the outside has a pair of the register setting data and the register identifier as one unit.

  Further, reference numeral 152 in FIG. 7B denotes a register identifier decoder (register identification means). The register identifier decoder 152 receives buffer data obtained from the buffer 151 in FIG. 7A, that is, test setting data td. Thus, the register to be set is identified by the register identifier included in the test setting data td, and the register setting data is output to the identified register. Here, the identification by the register identifier is performed by identifying the address setting register 202, the input data register 203, the control signal register 204, and the expected value data register 205, which are four setting registers, and these four setting registers. Are the input data setting register 124, the data registers 125 to 127, the row address initial value setting register 115, the column address initial value setting register 116, the control signal setting register 131, and the expected value data setting register 144. Here, as an example, an address setting register 117 is shown as a setting target register, and the register setting data output from the register identifier decoder 152 is an address setting buffer 153 provided for the setting target address setting register 117. Temporarily stored.

  Also, a plurality of other buffers such as the address setting buffer 153 shown as an example are provided for each of the registers constituting the four setting registers.

  Therefore, the register setting data obtained from the register identifier decoder 152 is stored in an address setting buffer 153 (predetermined buffer) provided for the address setting register 117. This register setting data is stored in the address setting buffer 153 until the previous test is completed. When the previous test is completed, a load signal (predetermined signal) is transmitted to the address setting buffer 153, and the register setting data is immediately loaded into the address setting register 117.

  With such a configuration, the time during which the memory test is interrupted for register setting is significantly reduced.

  Next, a memory built-in self test method according to the present embodiment will be described. When a memory test is performed using the built-in self-test circuit of the present invention, it is necessary to set register setting data in the register circuit 106 each time a test is performed with one test pattern. This will be described with reference to the flowchart of FIG.

  First, a test mode signal for testing the memory 100 is activated in step S8101, and then the register circuit 106 is set in step S8102, and then the reference clock signal ck is input and set to the test pattern A in step S8103. Test A is started. When the test A using the test pattern A is completed, the process proceeds to step S8104, and the input of the reference clock signal ck is stopped. If it is desired to continue the test using another test pattern B, the register circuit 106 is set again in order to perform the test using the test pattern B in step S8105. After the register circuit 106 is set, the reference clock signal ck is input in step S8106, and the test B set to the test pattern B is started. When the test B using the test pattern B ends, the process proceeds to step S8107, the input of the reference clock signal ck is stopped, and the test B of the test pattern B ends. Furthermore, when it is desired to perform the test C for the test pattern C, step S8109 is similarly performed. This flow is repeated as many times as there are test patterns that need to be tested.

  When debugging with a small number of test patterns, there is no problem even if testing is performed with this flow, but when many tests such as testing at the time of product shipment must be performed, it takes time to set registers, The extension cannot be ignored, leading to an increase in product cost.

  In testing at the time of product shipment, it is common to test the entire area of the memory, and a certain amount of time is required to perform the test using one test pattern. This processing time is used for other processing in the flowchart shown in FIG. 8B, which uses the configuration shown in FIG. The register circuit 106 will be described by taking the address setting register 117 as an example, and the buffer will be described by taking the address setting buffer 152 as an example.

  In the flow of FIG. 8B, preparation for setting the address setting register 117 for the next test is performed while the test is being performed. First, after the test is started, in step S8201, a test mode signal for testing the memory is activated. In next step S8202, register setting data is set in the address setting register 117. In the processing flow shown in FIG. 8B, a buffer process is provided for temporarily storing register setting data included in test setting data input from the outside. Then, register setting data for the next test is stored in the address setting buffer 153 during a certain test, and the test is started immediately by loading from the address setting buffer 153 to the address setting register 117 during the next test. To be able to. This is shown in steps S8203 to S8204 in FIG.

  After receiving the test setting data td input from the outside in step S8202 (test setting data receiving step), the register to be set is identified by the register identifier decoder shown in FIG. 7B (register identifying step). The register is set by sending register setting data to the identified register to be set. In step S8203, the reference clock signal ck is input and the test A is performed based on the register setting data set in step S8202, while the test setting data td transmitted from the outside is received (test setting). (Data receiving step), the register to be set is identified from the register identifier included in the received test setting data td (register identifying step). Then, register setting data for the test B is stored in the address setting buffer 153 provided for the identified setting target address setting register 117 (buffer process). In this way, the register setting data for the next test B is temporarily stored and prepared in the address setting buffer 153 immediately before the register. In the next step S8204, the reference clock signal ck is stopped by the end of the test A, and the register setting data for the next test B is loaded from the address setting buffer 153 to the address setting register 117. Subsequently, when it is desired to perform the test C, similarly, steps S8205 to S8207 are repeated, and the time for preparing the register setting data for the test C is reduced.

  The built-in self-test in this embodiment requires four registers, an address setting register 202, an input data register 203, a control signal register 204, and an expected value data register 205, so that time can be reduced. The method shown in FIG. 8B is used.

  In addition, with the method of FIG. 8B using this configuration, the terminal connection from the external terminal to the buffer is sufficient in one system, so that it is possible to reduce the circuit and the test time.

  The built-in self-test circuit of the memory according to the present invention can input test setting data from the outside, change the test contents by an internal register circuit, and reduce the number of connections from the external terminal to the internal circuit. An increase in circuit scale can be suppressed. In addition, by providing a buffer for the register for changing the test contents and preparing the setting data of the next test in the buffer during one test, the time required for the entire setting can be shortened. . Therefore, it is useful as a built-in self-test circuit for a semiconductor integrated circuit whose memory has been increased in scale and number.

It is a block diagram of the built-in self-test circuit in embodiment of this invention. FIG. 3 is a configuration diagram of an address setting register and an address generation circuit in the embodiment of the present invention. 4A and 4B are diagrams showing a test area of a memory according to an embodiment of the present invention, where FIG. 5A is a diagram showing an access movement, and FIG. It is a block diagram of the register for input data and the input data generation circuit in the embodiment of the present invention. It is a block diagram of the register for control signals and the control signal generation circuit in the embodiment of the present invention. It is a block diagram of the register for expected value data and the expected value data generation circuit in the embodiment of the present invention. 2A and 2B are diagrams illustrating a configuration of a register circuit according to an embodiment of the present invention, in which FIG. 1A is a configuration diagram of a data receiving portion, and FIG. 2B is a register for address setting register setting data in received test setting data. It is a block diagram of the part set to. FIG. 2 is a flowchart for explaining a built-in self-test using a register circuit in an embodiment of the present invention, where (a) is a flowchart for setting a register for each test, and (b) is an execution time of one test. FIG. 10 is a flowchart for register setting for the next test. It is a figure explaining the example of a circuit of the conventional built-in self test.

Explanation of symbols

100 Memory 101 Address Generation Circuit 102 Input Data Generation Circuit 103 Control Signal Generation Circuit 104 Expected Value Data Generation Circuit 105 Data Comparator 106 Register Circuit 107 Clock Generator 115 Row Address Initial Value Setting Register
(One of the address setting registers)
116 Column address initial value setting register
(One of the address setting registers)
117 Address setting register
(One of the address setting registers)
124 Input data setting register
(One of the input data registers)
125, 126, 127 Data register
(Input data register, expected value data register)
131 Control signal setting register
(One of the control signal registers)
144 Expected value data setting register
(One of the expected value data registers)
150 Shift register 151 Buffer 152 Register identifier decoder (register identification means)
153 Address setting buffer (predetermined buffer)
200, 201 External terminal 202 Address setting register 203 Input data register 204 Control signal register 205 Expected value data register 300 Test signal generating means td Test setting data ck Reference clock

Claims (6)

In a built-in self-test circuit of a memory that is incorporated in a semiconductor integrated circuit having a memory and tests the function of the memory,
Test signal generation means for generating a test signal for testing the function of the memory;
The test signal generated by the test signal generating means by receiving test setting data input from outside the built-in self-test circuit of the memory and inputting the output value of the test setting data to the test signal generating means A built-in self-test circuit for memory, comprising: a register circuit for changing the contents of the test by changing A built-in self-test circuit for a memory according to claim 1,
The test signal generating means includes
An address generation circuit for receiving an output value from the register circuit and generating an address control signal for controlling an address on the memory;
An input data generation circuit that receives an output value from the register circuit and generates test input data to be written to the memory;
A control signal generation circuit which receives an output value from the register circuit and generates a control signal for controlling writing and reading to the memory;
Expected value data that receives the output value from the register circuit and generates expected value data to be compared with the output data output from the memory by the test using the address control signal, the input data, and the control signal A built-in self-test circuit for a memory characterized by comprising a generation circuit. The built-in self-test circuit of the memory according to claim 1 or 2,
The register circuit includes:
An address register for address setting, an input data register for setting input data, a control signal register for setting control signals, and an expected value data register for setting expected value data Built-in self-test circuit for memory. A built-in self-test circuit for a memory according to claim 2,
Each of the address generation circuit, the input data generation circuit, the control signal generation circuit, and the expected value data generation circuit based on a reference clock signal input from the outside of the built-in self test circuit of the memory A built-in self-test circuit for a memory, comprising: a clock generator for generating at least one input clock signal. The built-in self-test circuit for a memory according to claim 3,
The register circuit includes:
The register data set in the address register, the input data register, the control signal register, and the expected value data register, and the register data among these four setting registers are set. A shift register for receiving the test setting data from the outside, comprising a register identifier for identifying one register;
Based on the register identifier included in the test setting data received by the shift register, one register is identified from the four setting registers for setting the register data, and is paired with the register identifier. Register identifying means for performing register identification processing for outputting the register setting data included in the test setting data for each of the four setting registers;
The register setting data output from the register identifying means is temporarily stored, and the register setting data temporarily stored at the end of one test that was executed while temporarily storing the register setting data is stored in the register setting data. A built-in self-test circuit for a memory, comprising: a plurality of predetermined buffers for outputting to each of the four setting registers. In a memory built-in self-test method for testing a function of the memory of a semiconductor integrated circuit having a memory,
A test setting data receiving step for receiving test setting data including a plurality of pairs of register identifiers and register setting data in pairs;
Based on the register identifier included in the test setting data received in the test setting data receiving step, an address register for setting addresses, an input data register for setting input data, and a control signal for setting control signals One register for setting the register setting data is identified from among four setting registers including a register and an expected value data register for setting expected value data, and is identified among the four setting registers. A register identifying step for outputting the register setting data to the one register;
The register setting data output in the register identification step is temporarily stored, and the register setting data temporarily stored at the end of one test executed while temporarily storing the register setting data, And a buffer process for outputting to each of the four setting registers.

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