JP3972416B2 - Memory test pattern generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test of a semiconductor integrated circuit, and more particularly to a test circuit for a memory circuit.
[0002]
[Prior art]
Due to advances in semiconductor circuit technology, it is common to mount memory and logic on the same chip. In order to inspect the memory circuit on such a chip, a means for activating the path between the primary pin of the chip and the pin of the internal memory is prepared, and the tester is configured by associating the pin of the internal memory with the primary pin of the chip at the time of inspection. There is an external test method for testing using an algorithmic pattern, but when the number of pins of the internal memory is large or when the logic from the internal memory to the external pin is deep, the circuit and wiring for the activation are not There are problems such as an increase in area and delay overhead, a long access path and high-speed testing is difficult, and an expensive tester is required to generate a test externally.
[0003]
As a technique for solving the above problems, a technique of embedding a circuit for inspection on the same chip as a non-inspection circuit called built-in self-test or BIST (Built-In Self-Test) is known.
[0004]
As a known example of this technique, Japanese Patent Application Laid-Open No. 6-325600 expresses an operation of accessing all memory cells once as a step, and a memory having means for processing the output of a binary counter for each step. A test pattern generation circuit is shown.
[0005]
As another example, Japanese Patent Application Laid-Open No. 6-342040 discloses a deterministic data pattern generator which is arranged on a VLSI chip and can select a data pattern via an instruction code even after the chip is manufactured. Yes.
[0006]
As another example, a method of embedding a general-purpose MPU and a test program as an inspection circuit on a chip is also conceivable.
[0007]
[Problems to be solved by the invention]
The BIST method reduces the problem of the external test method as described above. However, since the test circuit is incorporated as hardware, there is a problem that a specific test algorithm cannot be added or changed due to the cause of memory failure after manufacturing. It was.
[0008]
In Japanese Patent Laid-Open No. 6-325600, a complicated test such as galloping or walking in which there are two or more address changes cannot be executed. Further, since the test generation algorithm is realized as hardware in advance, there is a problem that the algorithm cannot be changed after the chip is manufactured.
[0009]
In Japanese Patent Laid-Open No. 6-342040, there is still a problem that the algorithm is fixed or the procedure is fixed because it is a deterministic pattern generator, and the degree of freedom in changing the algorithm is small.
[0010]
In the method of embedding a general-purpose MPU and a test program on a chip as an inspection circuit, even if the above-described complicated test can be performed, the cost and hardware overhead are increased, and access and control of the memory are increased. Therefore, there are problems such that it is difficult to perform a high-speed test because an instruction for the above operation takes a plurality of clock cycles in a plurality of steps.
[0011]
The present invention provides a compact and programmable high-speed memory test pattern generation circuit suitable for BIST, which solves the problems of the prior art in memory testing.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, in one means of the present invention, a single or a plurality of memory access address counters, a single or a plurality of memory access data registers, a program counter for execution step management, A test pattern generation circuit having a plurality of instruction registers for storing instruction words and a single or a plurality of control registers operated by the instructions is provided. In the instruction register, one access to the memory is regarded as one step, and an instruction to access the memory, a write or read address to the memory, an operation of write or read expected data, Stores a program that implements a memory test algorithm configured by instructions that simultaneously represent operations of execution control variables.
[0013]
According to another aspect of the present invention, the test pattern generation circuit is configured such that the instruction register portion is replaced with another storage element such as a RAM or a ROM.
[0014]
Furthermore, in another means of the present invention, the test pattern generation circuit is embedded in the same semiconductor integrated circuit as the memory under test, and a semiconductor circuit is provided in each FF including an instruction register inside the test pattern generation circuit. The value can be set directly or indirectly from the primary input.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
For simplicity, FIG. 1 shows a first embodiment of the present invention in which the memory to be inspected is a 4-word × 2-bit SRAM.
[0016]
<Description of FIG. 1>
The test pattern generation circuit 100 includes two address counters (hereinafter referred to as AC) 116, one data register (hereinafter referred to as DR) 117, a program counter (hereinafter referred to as PC) 112, and eight instruction registers (hereinafter referred to as IR) 111. As the control registers operated by the instruction, a loop counter (hereinafter referred to as LC) 115, two work counters (hereinafter referred to as WC) 118, and a maximum word address storage register (hereinafter referred to as MAR) 113 are provided. Further, all flip-flops (hereinafter referred to as FF) constituting each register and counter are clocked by a test clock (hereinafter referred to as TC) 101, and scan-in data (by a shift operation synchronized with the scan clock (hereinafter referred to as SC) 102) ( Scan-in from SI) and scan-out to scan-out data (hereinafter SO) are possible. Since the PC 112 has 8 IRs 111, 3 bits from the logarithm of 2 and AC 119, WC 118, and MAR 113 all have 2 bits from the logarithm of 2 so that the maximum word address 3 (address number 4) can be expressed. The LC 115 is 2 bits on the premise of a maximum of 2 loops.
[0017]
<Description of FIG. 2>
FIG. 2 is an example implementation of the more detailed circuit of FIG.
[0018]
The selector 114a selects and outputs one of eight IR111s 0 to 7 according to the value of the PC 112.
[0019]
Each of the eight IRs 111 has a width of 12 bits, and each of the bits 111a to 111i has the meaning shown in FIG.
[0020]
In order to facilitate the understanding of the test generation algorithm described later, this machine language expression instruction is represented by a mnemonic expression as shown in FIG.
[0021]
The selected instruction bit INS0 and INS1 bit 111a of the selected IR 111 are decoded by the instruction decoder 114b for the type of the instruction. The write indicator W106 for the write instruction, the read mode indicator R105 for the read instruction, and the mask for the NOP and LOOP instructions The mode indicator M107 is 1 each.
[0022]
The LC 115 performs a decrement process in synchronization with TC when the DEC terminal is 1, and the ZERO terminal becomes 1 when the content becomes 0.
[0023]
Therefore, in the LOOP instruction, the DEC terminal of the LC 115 becomes 1, and the LC value is decremented in synchronization with the application of TC.
[0024]
The selector in the address processor 114c selects the designated AC0 or AC1 with the value of the AC selection bit 111b of the selected IR 111. Further, this result is output to the terminal A 108 by changing the complement address indicator bit 111e of the selected IR 111 to 0 or 1 and changing the complement in 114c to a non-complement or a complement value, respectively.
[0025]
The AC 116 performs an increment process in synchronization with TC when the INC terminal is 1, and returns to 0 when it overflows in the increment process.
[0026]
Therefore, depending on whether the value of the AC0 addition bit 111c of the selected IR111 is 0 or 1, AC0 holds or increments the current value in synchronization with the application of TC.
[0027]
Further, depending on whether the value of the AC1 addition bit 111d of the selected IR111 is 0 or 1, AC1 holds or increments the current value in synchronization with the application of TC.
[0028]
Depending on whether the DR inversion instruction bit 111f of the selected IR 111 is 0 or 1, the selector in 114d selects a non-inverted or inverted value of the current DR value, and the result is synchronized with the application of TC. Stored in DR.
[0029]
The WC 118 performs decrement processing in synchronization with the application of TC when the DEC terminal is 1, and the ZERO terminal becomes 1 when the content becomes 0.
[0030]
Therefore, when the value of the WC0 subtraction instruction bit 111g of the selected IR 111 is 1, the DEC terminal of WC0 becomes 1, and the value of WC0 is decremented in synchronization with the application of TC.
[0031]
When the value of the WC1 subtraction instruction bit 111h of the selected IR 111 is 1, the DEC terminal of the WC 1 becomes 1, and the value of the WC 1 is decremented in synchronization with the application of TC.
[0032]
When the L terminal is 1, the PC 112 loads the value of the D terminal in synchronization with the application of TC, and when the INC terminal is 1, the PC 112 performs an incremental process in synchronization with the application of TC.
[0033]
The ZERO output terminal of WC0 indicating that the value of the WC0 subtraction instruction bit 111g of the selected IR111 is 1 and the current WC0 is 0, or the value of the WC1 subtraction instruction bit 111h of the selected IR111 is 1 When at least one of the ZERO output terminals of WC1 indicating that the current WC1 is 0 holds, the non-inverted output of the OR gate in the work counter processor 114e is 1, and the INC terminal of the PC is Since it becomes 1, the value of PC is incremented in synchronization with the application of TC.
[0034]
The value of the WC0 subtraction instruction bit 111g of the selected IR111 is 0 or the ZERO output terminal of the current WC0 is 0, and the value of the WC1 subtraction instruction bit 111h of the selected IR111 is 0 or the ZERO output terminal of the current WC1 is When 0 holds simultaneously, the inverted output of the OR gate in the work counter processor 114e becomes 1, and the L terminal of the PC becomes 1. Therefore, the next execution step no. Of the IR 111 selected in synchronization with the application of TC. The 3-bit value of bit 111i is loaded into the PC.
[0035]
In this figure, the illustration of the connection is omitted, but all the FFs in the test pattern generation circuit 100 have a well-known shift scan structure, and from the SI 103 in synchronization with the SC 102. Scan-in and scan-out to SO110 are possible.
[0036]
Such a circuit can be realized with about several hundred gates, and the circuit scale is significantly smaller than that in the case of using a general-purpose MPU or the like.
[0037]
<Figure 4 Explanation of parameters>
Of the symbol parameters used in the instruction specification of FIG. 4, P0 is a step number from 0 attached to each instruction. P1 indicates an address counter (AC). However, when an inversion symbol (˜) is attached, it indicates an AC complement value. This complementary value means that when the value indicated by AC takes an ascending value, the address actually given to the memory takes a descending value. P2 indicates whether data is edited (inverted in this embodiment). P3 indicates the AC to be incremented. P4 indicates the work counter (WC) to be decremented. P5 indicates the step number to be processed next.
[0038]
<Figure 4 Instruction explanation>
In the WT instruction, the current DR data is written to the test target memory at the address indicated by the current AC indicated by P1, and the instruction common processing described later is performed. The RD instruction reads the data of the address indicated by the current AC indicated by P1 from the test target memory, compares the data of the current DR as an expected value, and performs an instruction common process described later. The NP instruction does not access the test target memory and performs only the instruction common processing described later. The LP instruction performs an instruction common process similar to the NO instruction, and further performs a decrement process of the loop counter (LC). As a result, if the LC is 0, the E signal indicating the end of the process is set to true (1). As processing common to all commands, data editing according to the P2 instruction, AC incrementing according to P3, and WC decrementing according to P4 are performed. If there is a WC decrement instruction, if the WC is 0 at the time of execution of this instruction, the program counter (hereinafter referred to as PC) becomes the contents of the current PC + 1, and if not, P5 is substituted into the PC.
[0039]
<Processing procedure>
As a processing procedure of circuit operation in the present embodiment, first, as preparation for test generation, all FFs of the test pattern generator are initialized by a scan operation. At this time, the address register is set to 0, the work counter is set to 3 which is the maximum word address, and the program counter is set to 0. The loop counter is set to 2 this time. Thereafter, when an actual test clock is transmitted, a test generation operation is performed. Finally, when 1 is sent to the E signal from the test generation circuit, it is a test end.
[0040]
<FIGS. 5 and 6 Description of March Program>
More specifically, the circuit operation will be described by taking the March program of FIG. 5 as an example.
[0041]
The machine language of the March program in FIG.
Step 0 is INC <0-1> = '00', SAC = '0',
INC0 = '1', INC1 = '0', CA = '0', INVD = '1',
DW0 = '1', DW1 = '0', NS <0-2> = '000',
Step 1 is INC <0-1> = '01', SAC = '0',
INC0 = '1', INC1 = '0', CA = '0', INVD = '1',
DW0 = '1', DW1 = '0', NS <0-2> = '001',
Step 2 is INC <0-1> = '11', SAC = '0',
INC0 = '0', INC1 = '0', CA = '0', INVD = '1',
DW0 = '0', DW1 = '0', NS <0-2> = '000',
It becomes.
[0042]
In the circuit operation, first, AC0 = AC1 = PC = 0, WC0 = WC1 = 3, LC = 2, and DR = “00” are set as initial values. It can be easily understood as a known technique that the initial value can be set by sequentially setting data taking into consideration the shift order of the FFs in the circuit 100 to the SI103 terminal in a state where TC is 0 and applying SC102. I will. Thereafter, processing is executed as shown in FIG. 6 in synchronization with TC in the order of FIG. FIG. 6 shows an AC that determines the type of access to the memory under test, the address to be accessed, and the address in the processing order for each cycle synchronized with the TC 101 in the second and subsequent rows. Hereinafter, the values of AC0, AC1, DR, WC0, WC1, PC, and LC are described. For AC0 to LC, the upper part of each row shows values before TC application, and the lower part shows values after TC application.
[0043]
In this example, data is inverted in each cycle while performing simple repetition using AC0 and WC0. Thus, by using the counter, the data editing and the loop skillfully, the generation of the march test can be described with only three steps of instructions.
[0044]
<Fig. 7 and Fig. 8 Explanation of galloping program>
As a more complicated example, the operation in the case of the galloping program of FIG. 7 will be described with reference to FIG. As initial values, AC0 = AC1 = PC = 0, WC0 = WC1 = 3, LC = 2, and DR = '00 'are set as in the case of the march. FIG. 8 is almost the same as FIG. 6, but with regard to the DR and LC fields, values corresponding to the processing orders 1 to 38 are described in the A column and values corresponding to 39 to 76 are described in the B column. Since the values corresponding to the processing orders 1 to 38 and the values corresponding to 39 to 76 are the same, the other columns are represented by one side. In the processing order 1 to 4 in FIG. 8, all addresses are cleared to 0 using AC0 and WC0 as in the case of the march. After reversing DR in processing procedure 5, in procedures 6 to 38, AC0, AC1, WC0, and WC1 are devised and used to change the main address (X) from 0 to 3, Thus, a complicated flow is realized in which the slave address (Y) is changed from X + 1 to X−1 for each X. Here, it is assumed that the address increment is cyclic, such as 0, 1, 2, 3, 0, 1. According to the present embodiment, such a complicated flow can be described with an instruction of only 7 steps. In addition, the test pattern to be generated can be changed only by the initial setting including the change of the instruction word without changing the hardware of the test generator. In addition, walking patterns can be generated by writing a program using a similar method. This indicates that a fairly complicated pattern generation algorithm can be programmed after chip creation without changing hardware, and is an important feature of the present invention.
[0045]
Furthermore, if the bit width and value of the loop counter (LC) are further increased, burn-in can be performed by rotating the loop as many times as necessary.
[0046]
Alternatively, for the purpose of the burn-in test, it is possible to add a circuit change such as not decrementing the LC until a specific signal is received.
[0047]
Furthermore, the present embodiment is an example in which the number of word addresses is a power of 2, but if this is not the case, a circuit for comparing the contents of the counter with the word address is added or the maximum address is stored in advance. Then, a measure such as determining that the decrement result is 0 may be taken.
[0048]
In this embodiment, an inverting circuit is taken up as a data editing method. However, a pattern that shifts every cycle may be required depending on a request from the memory test side. In such a case, it is possible to add a bit representing the type of data editing in the instruction word.
[0049]
As a second embodiment of the present invention, FIG. 9 shows an example of circuit connection when used as a memory test pattern generator in a BIST environment. The test pattern generator 100 is embedded in the same chip 200 as the memory 208 to be tested, and is placed under the management of the chip test control circuit 201. The memory under test includes a READ signal 202 and a READ signal during a normal logic operation, a WRITE signal 203 and a WRITE signal during a normal logic operation, an address signal 204 and a test address signal during a normal logic operation, and a normal logic operation. The data signal 205 at the time and the data signal at the time of the test are connected via the multiplexer 207 that selects the test side signal at the time of the test. Further, the memory output result is connected so that the fan-out signal is compared with the data signal output from the test generator by the comparator 210. Further, the mask signal output from the test generator serves to make the output result of the comparator 210 unconditional match. The operation of the test control circuit 201 is controlled from the outside by the test input pin group 211 of the chip 200, and the result is output to the test output pin group 212. In a typical example, the input pin group 211 is directly connected to the selection signals 206 of the test pattern generation circuit 100, 101, 102, 103, and 104, and the MUX 207, and the output pin group 212 is connected to the test pattern generation circuit 100. The test end indicator E104 and the output 211 of the comparator 210 may be directly connected. In the case of this connection, the operation of the test pattern generation circuit 100 is the same as that of the first embodiment. In this embodiment, after setting the initial state, 206 is set to the test logic selection side, and the comparator The only change is to monitor at 212 whether it reports a mismatch at 211.
[0050]
It is possible to store the output result of the comparator in the control circuit and observe it after the test is completed.
[0051]
In the present embodiment, a typical example is shown. However, within the scope of the present invention, for example, the circuit is used as a test pattern generation circuit of a tester, or on a connection jig with the tester. By using this circuit, it is possible to test the memory on another chip by mounting this circuit on a chip different from the memory to be tested.
[0052]
【The invention's effect】
As described above, by using the present invention, it is possible to solve the problems of the prior art in the memory test and obtain a compact and programmable high-speed memory test pattern generation circuit suitable for BIST.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a test pattern generation circuit for SRAM of 4 words × 2 bits.
FIG. 2 is a block diagram showing a more detailed circuit configuration of a test pattern generation circuit for SRAM of 4 words × 2 bits.
FIG. 3 is a specification of constituent bits of a machine instruction word for operating the circuits of FIGS. 1 and 2;
FIG. 4 shows specifications when machine instructions are expressed as mnemonic instructions.
5 is a description example of a march pattern generation program expressed by a mnemonic instruction in FIG. 4;
6 is an operation example in which the execution of the program of FIG. 5 is traced including the internal state for each step.
7 is a description example of a galloping pattern generation program expressed by a mnemonic instruction in FIG. 4;
8 is an operation example in which the execution of the program in FIG. 7 is traced including the internal state for each step.
FIG. 9 is an example of circuit connection when used as a test pattern generator for a memory under a BIST environment as an embodiment.
[Explanation of symbols]
100 ... Test pattern generation circuit, 101 ... Test clock (TC),
102: Scan clock (SC), 103: Scan-in data (SI),
104 ... Test end indicator (E),
105 ... Read mode indicator (R),
106 ... write indicator (W),
107 ... mask mode indicator (M),
108 ... Address output (A) 109 ... Data output (D)
110 ... scan-out data (SO),
111: Instruction register (IR), 111a: Instruction (INS <0-1>),
111b ... AC selection (SAC), 111c ... AC0 addition (INC0),
111d ... AC1 addition (INC1), 111e ... complement address instruction (CA),
111f ... DR inversion instruction (INVD), 111g ... WR0 subtraction (DW0),
111h ... WR1 subtraction (DW1),
111i: Next execution step number (NS <0-2>),
112 ... Program counter (PC),
113 ... Maximum word address storage register,
114 ... Control circuit (CL), 114a ... Selector,
114b: instruction decoder, 114c: address processor,
114d: Data processor 114e: Work counter processor
115: Loop counter (LC), 116: Address counter (AC),
117: Data register (DR) 118: Work counter (WC)
118a ... Work counter (WC0), 118b ... Work counter (WC1),
200 ... chip,
201: Chip test control circuit,
202 ... READ signal during normal logic operation,
203 ... WRITE signal during normal logic operation,
204: Address signal during normal logic operation,
205 ... Data signal in normal logic operation, 206 ... Test mode signal,
207 ... multiplexer, 208 ... memory under test,
209 ... Memory output, 210 ... Comparator,
211: Comparison result, 212: Test input pin group,
213: Test output pin group.

Claims (2)

Multiple instruction registers;
An instruction selector;
An instruction decoder;
A program counter,
A work counter,
An address counter that outputs the address to be stored to the memory as an address signal;
A data register that outputs data to be stored to the memory as a data signal;
Each instruction register stores one of a WT instruction, an RD instruction, a NO instruction, and an LP instruction,
The selector selectively outputs the instruction of the instruction register to the decoder according to the value of the program counter,
The instruction decoder is for decoding the instruction,
When the instruction decoder decodes the WT instruction, data in the data register is written to an address indicated by the address counter, data in the data register is edited, the address counter is incremented, and the work counter is decremented. And
When the instruction decoder decodes the RD instruction, it reads data from the address indicated by the address counter, compares it with an expected value, edits data in the data register, increments the address of the address counter, and the work counter Is decremented, and
When the instruction decoder decodes the NO instruction, the data in the data register is edited, the address counter is incremented, and the work counter is decremented.
When the instruction decoder decodes the LP instruction, the loop counter is decremented,
Upon decrementing the workpiece counter, when the value of the work counter is 0, the instruction register increments the value of the program counter, otherwise 0 for storing instructions for processing the next the instruction a step number to specify those substituted into the program counter,
When the value of the loop counter is 0, the test is terminated,
A test pattern generation circuit, wherein an instruction in the instruction register is set directly or indirectly from outside. The pattern generation circuit according to claim 1 ,
It has a de Tasereku data,
A test pattern generation circuit, wherein, when editing data in the data register, the data selector selectively outputs the value of the data register or its inverted value to the data register.

Images