KR100683436B1 - Generator of memory BIST circuit - Google Patents

Abstract

The present invention relates to a memory self test circuit generator, and more particularly, to a CAD tool for automatically generating a BIST IP by receiving information of a memory structure and a memory test algorithm.

The memory self test circuit generator may include receiving memory model configuration information for memory self test and describing a memory model; A memory configuration step of registering a generated memory model for testing in the memory model description step; Algorithm configuration step for selecting an algorithm to be applied to the memory test by fault or a conventional algorithm, and BIST IP generation step for generating and outputting a BIST Verilog file embedded in a system on chip by applying the selected memory model and test algorithm. There is a technical feature made to include.

Therefore, the memory self test circuit generator according to the present invention has an effect of efficiently testing regardless of the model and the number of semiconductor integrated memories by automatically generating a BIST IP by receiving information of a memory structure and a memory test algorithm from a user. .

Memory Test, BIST, Circuit Generators

Description

Generator of memory BIST circuit             

1 illustrates a functional model of a memory for a test.

2 is a diagram illustrating an internal structure of a dual port memory.

3 is a diagram illustrating an operation sequence of a memory self test circuit generator.

4 is a diagram illustrating a test algorithm optimization flowchart.

5 is a diagram illustrating a dual port memory cell failure classification.

6 is a diagram illustrating an algorithm for detecting a dual port memory failure.

7 is a diagram illustrating the structure of a dual port memory when both input and output signals are defined.

FIG. 8 is an embodiment of a dual port memory structure diagram created by selecting only a signal desired by a user.

FIG. 9 is a diagram illustrating functions of signals represented in FIG. 7.

10 is a diagram illustrating a multi-port memory structure.

11 is a diagram illustrating a BIST IP structure of a single port memory.

12 illustrates a BIST IP structure of a multi-port memory.

13 illustrates a BIST structure for testing a flash memory.

14 is a test mode state diagram of a flash memory BIST controller.

15 is an analysis mode state diagram of a flash memory BIST controller.

16 is a state diagram of a flash memory BIST test pattern generator.

17 is a diagram illustrating a tool for selecting a failure model and generating a March algorithm.

18 is a view showing the entire user interface of GenMBC.

19 illustrates a memory model generation user interface.

20 is a diagram illustrating an embodiment of a read / write operation waveform of a memory model.

21 is a diagram illustrating a memory model registration user interface.

22 is a diagram illustrating a test algorithm application user interface.

           <Description of the symbols for the main parts of the drawings>

     100: GenMBC setting information 110: GenMBC

     120: Memory BIST IP 200: Memory Model Menu

     210: Memory Config Menu 220: Algorithm Config Menu

     230: MBIST Gen menu

The present invention relates to a memory self-test circuit generator, and more particularly, to a CAD tool that generates a BIST (Built-In Self Test) intellectual property by receiving information of a memory structure and a memory test algorithm from a user. It is about.

Testing of a large number of embedded memories due to the increased integration of semiconductor integrated circuits becomes increasingly complex and difficult to implement because they cannot be accessed directly from the input and output pins of the integrated circuit. In order to solve the above problems, a chip design technique using the design for testability technique has been introduced. Testability design techniques are designed to improve the observability and controllability of in-chip nodes. Scanning, BIST, and Ad-hoc techniques are used. In particular, the BIST technique takes less time because the test can be performed at the operating frequency of the chip, and has the advantage that no additional test equipment is required to compare the test response. Because of these advantages, many chips apply the BIST technique.

Substrate-level testing is also required when constructing a system using these chips. Substrate-level testing has increased the difficulty of testing as the surface-to-chip technology has increased the number of interconnects between chips. Therefore, a design technique to solve this problem is required, and a lot of researches on a testability design technique that can support testing at the substrate level have been studied.

Failures in real memory can take many forms. Therefore, it is practically impossible to perform a test for all cases of failure that may affect the normal operation of the memory. However, the purpose of the memory test is to determine whether a failure has occurred, rather than identifying the type or location of the failure, except in special cases. Therefore, memory test in general memory test first simplifies the structure of memory into functional model.

1 illustrates a functional model of a memory for a test. In this case, the memory is composed of a memory cell array, an address decoder, and read / write logic. The faults that can occur in each module can be divided according to where they occur. The faults that can occur in this functional model can be classified into address decoder faults, stuck-at faults, transition faults, and coupling faults. Fixing failure and transition failure are failure models considering one memory cell, and combined failure is a failure model considering two cells together.

An address decoder failure is divided into a failure in which no cell in memory can access a specific address, a failure in which one address accesses two memory cells, and a failure in accessing one memory cell at different addresses.

A fixation fault is a fault in which the value of a memory cell is fixed at a logic value of 0 or 1 and the logic value does not change. A fix-at-0 fault at which a logic value is fixed at 0 and a fixation at 1 is fixed. 1 (stuck-at-1) failure. Tests to detect stuck failures should be able to read and write 0 and 1 to each and every cell.

A transition failure is a failure in which the logic value of a memory cell does not transition from 0 to 1 (upward transition) or 1 to 0 (downward transition). Tests to detect transition failures should be able to cause upward and downward transitions in each and every cell, and be able to read the value of the cell before another transition occurs anymore. Coupling failures are failures in which the value of another memory cell associated with that cell changes when a logical value transition occurs in a particular memory cell.

Coupling faults include an inversion coupling fault where the transition of one cell changes the contents of another cell, and an intimate coupling fault where the transition of one cell fixes the contents of the other cell to a logical value of zero or one. There is this. Coupling failure <↑; 1> is a failure where the value of the coupled cell is fixed to 1 when an uplink transition occurs in the combined cell, and a <↑; 0> fault is the value of the combined cell when an upshift occurs in the combined cell. This is a fault that is stuck to zero. <↓; 0> faults and <↓; 1> faults are faults in which the value of the coupled cell is fixed to 0 and 1, respectively, when a downward transition occurs in the combined cell. In order to detect a coupling failure, it is necessary to activate the coupling failure in all possible cases and read it before writing any value to the combined cell.

The memory can be divided into stand-alone memory and embedded memory according to where it is located. Built-in memory is more difficult to test than stand-alone memory because the input and output signals must be controlled or observed outside the chip. In addition, as described above, due to the structural characteristics of the memory itself, a large number of test patterns are needed to detect a memory failure since complex fault forms occur that cannot be detected by a commonly used stuck-at fault model. It is generally acceptable to test using the memory BIST technique.

Various memory test algorithms based on March that can detect the above memory failures have been developed so far. The March C-test algorithm, which is currently widely used, can detect all of the above address decoder failures, stuck failures, transition failures, coupling failures, and the like.

 ↓ (w0); ↓ (r0, w1); ↓ (r1, w0); ↑ (r0, w1); ↑ (r1, w0); ↑ (r0)

    M0 M1 M2 M3 M4 M5

The definitions of the symbols ↓, ↑, w0, w1, r0, and r1 used in the algorithm are as follows.

↓: Reduce the memory address from high address to low address

↑: Increase memory address from low to high

w0: Write logical value 0 to memory cell

w1: Write logical value 1 to memory cell

r0: read logical value 0 from memory cell

r1: read logical value 1 from a memory cell

For example, M1 operation decreases the memory address and reads logical value 0 and writes logical value 1 to the cell corresponding to the current address.

Memory can be divided into memory in bit unit and memory in word unit according to the unit of reading and writing. In contrast to the unit of memory, the unit of memory reads and writes in units of words. Since a word consists of two or more bits, word-by-word memory tests must take into account the problem of fault masking that can occur within one word. In this word-based memory test, only one bit pattern does not solve the problem of fault masking that may occur between bits in a word. Therefore, bit patterns called background data are required to detect these faults. Bit patterns that can be used as background data must be able to solve the above-mentioned fault masking problem, and the number of required bit patterns is determined by the number of bits in one word. If the number of bits in one word is m, then [log2m] + one or more background data should be used.

FIG. 2 is a diagram illustrating the internal structure of a dual-port memory capable of 2-read / 2-write, which is a type of multi-port memory. The multi-port memory consists of one common memory cell array and a plurality of input / output circuits that can access it. Most multi-port memory test algorithms consider multi-port memory as multiple single-port memory and perform tests using the algorithm for existing single-port memory test independently for each port. Therefore, it takes P * T time to test the multi-port memory with P ports using the single-port memory test algorithm with a time complexity of T using the existing multi-port memory test algorithm. Existing multi-port memory test algorithms consider the multi-port memory as a combination of several single-port memories, and thus, test execution time is proportional to the number of ports.

Most commercially available tools have a disadvantage in that it is difficult to add BIST-related instructions that can be selectively used by a user because the generated circuit is provided as a gate level circuit.

The conventional semiconductor memory test apparatus of the Republic of Korea Patent Publication No. 10-2000-0051283 relates to a test device of the semiconductor memory to simplify the test process and facilitate the manufacture of the package so that the memory test can be efficiently performed, the test circuit at the gate level Because of this, there is no room for BIST-related setting that can be selectively used by the user, and it was limited to testing DRAM memory.

In addition, the automatic generation method of a user-defined memory embedded self test circuit of the Republic of Korea Patent Publication No. 10-2000-7014772 of the prior art provides a tool for automatically generating a circuit for the memory self test, but detailed BIST operation for each embedded memory type There is no detailed description of, and in particular, it does not consider the test of the flash memory, there is a problem such as not outputting the BIST IP described in Verilog-HDL code.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, it is possible to efficiently test the semiconductor integrated memory by automatically generating the BIST IP by receiving the information of the memory structure and the memory test algorithm to the user It is an object of the present invention to provide a memory self-test circuit generator.

According to an aspect of the present invention, there is provided a method for automatically generating a board-level memory self test circuit, the method comprising: describing a memory model by receiving memory model setting information for memory self test; A memory configuration step of registering a generated memory model for testing in the memory model description step; BIST that generates and outputs a BIST Verilog file that can be embedded in a system on chip (SoC) by applying the selected memory model and test algorithm to the algorithm configuration step of selecting an algorithm to be applied to a memory test by fault or from among conventional algorithms. This is accomplished by a memory self test circuit generator comprising an IP generation step.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

FIG. 3 is a diagram illustrating an operation procedure of a generator of memory BIST cuicuit (GenMBC, hereinafter referred to as GenMBC). GenMBC selects the type of memory to test and the algorithm to apply, and GenMBC generates BIST IP in Verilog-HDL code form through strategic application of information received from the user. In the configuration file part of GenMBC, there are three main categories. The first part of memory model classification is to select memory to test among single-port memory, multi-port memory, and flash memory, define input and output pin names and pin size in selected memory, and read and write memory. Describe the timing of the Second, since GenMBC supports multiple memory BIST IPs of the same size, enter the number of memory models to test. Finally, when the algorithm, background data, control signal, etc. to be applied are input, all settings are applied strategically to generate BIST IP described in Verilog-HDL.

4 is a diagram illustrating a test algorithm optimization flowchart. In order to generate algorithms for detecting faults desired by the user rather than the conventional March algorithm, the present invention improves the disadvantage that a large amount of time is consumed in terms of time and complexity, and thus the present invention provides a typical fault model, a stuck-at fault. Memory failures such as transition faults, coupling faults between two cells, and address decoder faults can be detected. In addition to the conventional March algorithm, the optimization of the failure algorithm desired by the user and the desired algorithm can be directly described and applied.

5 shows a dual port memory cell failure classification. As shown in FIG. 5, a dual port related failure occurs when two ports access one cell at the same time (2PF1), and a failure occurs when two ports simultaneously access another cell while one cell has a certain value. 2PF2a), failure when two cells fail simultaneously when accessing one cell at the same time (2PF2v), write operation to one cell through each port, and another port When a read operation is performed to another cell, there is a failure (2PF2av) that causes the cell of the read operation to be changed.

FIG. 6 illustrates an algorithm for detecting a dual port memory failure as shown in FIG. 5. GenMBC provides this algorithm as well as a user-defined algorithm part that allows you to put your own algorithm.

The dual port memory structure modeled through GenMBC can define the input and output signals according to the characteristics of the desired memory model without specifying the port input and output signals. 7 is a dual port memory structure diagram when both input and output signals are defined. In this structure, a dual port memory can be designed by selecting a dual port memory input and output signal desired by a user. FIG. 8 is an exemplary embodiment of a dual port memory structure in which only a signal desired by a user is selected. 9 illustrates the function of the signals represented in FIG. In the dual port according to the user signal definition of FIG. 8, not only a control signal, an input and an output signal but also a bit width, read and write operation technique of the signals may be defined. As such, you can define the dual-port memory model you want to test and provide BIST IP to facilitate testing of the defined model.

The failure of a multi-port memory can be divided into a failure for one cell due to multiple ports and a failure in which two cells are associated. GenMBC basically provides March sp PF algorithm to detect multi-port memory failures and provides BIST IP to apply the algorithm that user wants.

FIG. 10 is a diagram illustrating a multi-port memory structure, in which input and output signals can be adjusted by user definition like a dual port memory.

11 is a diagram illustrating a BIST IP structure of a single port memory. The memory BIST IP generated by GenMBC is a control module that controls the entire IP, an address generation module (AGL Module) that generates an address for applying a test pattern, and a data generation module (DGL Module) that produces a test pattern. Finally, it is divided into data comparison module (DCL module) which receives data from memory and compares it to determine the failure after applying test pattern.

The control module is a circuit that controls the operation of each module of the memory BIST IP during the test process. This module determines the overall start and end of the test, and plays an overall role in ensuring that the test runs smoothly by applying the appropriate signal to each module. In the control module, the algorithm and background data inputted to the configuration file exist for each state machine, and the algorithm and background data are analyzed with the state machine, and the algorithm is repeated step by step until the address of the memory is completed. The DGLEnable signal is sent to the DGL Module to apply the background data, and the AGLEnable signal is sent to the AGL Module that generates the address so that the test data can read and write to the correct address in memory. Make it. Lastly, DCLEnable signal is applied to the data comparison module (DCL Module) to determine whether there is a failure.

The address generation module creates a counter that can sequentially increase and decrease from address 0 to the last address in order to receive the signal generated from the control module in test mode and read and write the test data value in the correct location. When changing from incremental state to decrement state, or from decrement state to incremental state, it is possible to generate the desired address by taking address's complement. In addition, when multiple memories are used, the last memory address can be adjusted to match the size of the address of the memory currently being tested.

The data generation module generates a test pattern by the DGLEnable signal generated from the control module. It generates data or background data for the memory currently being tested and delivers it to the memory.

The data comparison module reads and compares the values read from the memory with the data values generated by the data comparison module. The value read from the memory and the value generated by the data comparison module output the final test result value to the outside through IEEE 1149.1 or IEEE P1500 by shifting the result through various operations.

FIG. 12 is a diagram illustrating a BIST IP structure of a multi-port memory, in which a multi-memory model having one bit data input, multiple address access inputs, and multiple data signals output from the memory is tested through GenMBC. Control module that takes care of all signals, AlgoGL module for proper algorithm processing to detect faults occurring in multiple ports, and data generation module that delivers appropriate data values to memory according to algorithm. Module, a data comparison module (DCL module) that reads the value of the memory and compares it to the test pattern, and a total of five modules of the AGL module to apply the test pattern to the desired address of the memory BIST IP is configured to detect

The control module is a module that controls all modules during the BIST operation, and determines the start and end points of the entire test. Each module is implemented to perform a test operation suitable for the sub-module to operate as shown in FIG. 12. There is a performance state machine for the algorithm described in the configuration file and a background data state machine for the background data defined for each memory. When AGLEnable, DCLEnable, DGLEnable, and AlgorithmEnable are applied in the control module, an address generation module (AGL Module), a data comparison module (DCL Module), a data generation module (DGL Module), and an algorithm generation module (AlgoGL Module) are performed.

The address generation module receives the address generation signal from the control circuit in the test mode and generates a counter circuit so that it can be easily increased or decreased from address 0 to the last address of the memory, and the test pattern is read and written to the correct address. It was made possible. When the memory address is changed from the incremented state to the decreased state, or when the memory address is changed from the reduced state to the increased state, the address can be repaired to generate the desired address.When multiple memories are used, the size of the address of the memory currently being tested is determined. The last memory address can be adjusted to fit.

The data comparison module compares the value read from the memory with the value written to the memory to determine whether there is a failure. The presence of a fault is sent to the final test result value through IEEE 1149.1 or IEEE P1500 by shift operation after calculation in the data comparison module.

The data generation module is a module that generates background data according to the algorithm level in the AlgoGL module and delivers it to the memory under test.

The algorithm generating module analyzes the test algorithm described by the user and applies a data signal for each algorithm step.

13 illustrates a BIST structure for testing a flash memory. The BIST structure can be broadly divided into a control unit (CTR), a test pattern generator (TPG), and a test collar (MUX). The controller handles the test commands sent to the test pattern generator using input values input through the serial interface. CTR generates two modes, test and analysis, depending on the BMS signal.

In the test mode, the state of FIG. 14 sends a set of built-in instructions from the CTR to the TPG.

In the analysis mode, the test algorithm may be programmed while passing through the states as shown in FIG. 15, and the test command input through the BSI of FIG. 13 may be shifted.

16 illustrates a state of the test pattern generation unit TPG. The TPG serves to generate an address order by user description. When it is reset for the first time, it enters Idle state. When the ENA signal comes in, it goes to the Ifetch state to get the test command and analyze it. In the Exec state, the timing sequence required for the read, write, and erase commands is generated. The data is read from flash memory in the Dfetch state, and compared to the data without defects in the Compare section, and if a fault is found, the defect is notified through the serial output in the Wait state.

The memory self test circuit generator of the present invention generates an optimized test algorithm by selecting and selecting each failure model generated in the memory. The program generating the optimized test algorithm was implemented in a Windows OS environment, and the software development tool used the Visual C ++ compiler to prepare a graphical user interface.

FIG. 17 is a diagram illustrating a tool for generating a March algorithm by selecting a failure model address decoder fault (ADF), transition fault (TF), and stuck-at fault (SAF). As described above, an optimized test algorithm is generated by selecting a failure model.

18 is a view showing the entire user interface of GenMBC. GenMBC, a memory BIST Generator, generates a memory test RTL module embedded in the system on a chip. The operation process to generate is performed in the following four steps.

1. Memory Model Create a memory model at the technical stage.

1.1 Define the read, write and read / write port types.

1.2 Defines the bandwidth of the input and output pins and the active value of the enable signal.

1.3 Describes how memory works in the Cycle Editor.

2. Register the memory model for testing in the Memory Config step.

2.1 Load the memory model to test.

2.2 Register the model type to be tested and the number of each model.

2.3 Enter background data information.

3. In the algorithm configuration (MBIST Configuration) step, select the applied algorithm by fault or select from the existing March algorithm.

3.1 User Define Mode selects test algorithm by fault type.

3.2 Select March In Algorithm Mode, the existing March algorithm can be selected and applied.

3.3 Define the names of the clock and reset signals.

4. Create BIST Verilog file that can be embedded in system on chip at MBIST Gen stage.

4.1 Create one BIST Verilog file for one type of memory model.

4.2 For more than one type of memory model, BIST Verilog files generate as many memory models.

19 illustrates a memory model generation user interface. Register a read port, write port, or read / write port when you edition a memory model. Registering one acts as a single port, and registering two or more ports acts as a multi-port memory model.

First we define the memory model name. The keyword is model, which requires model_name. Next, we define the memory pins. The pin type definition keywords for the pin information of the memory are address, data_in, data_out, write_en, ram_en, and reset. The address keyword defines the name and size of the memory address. data_in is the input data bus of the memory and data_out is the output data bus of the memory. <name> and <bit_width> define the pin names and sizes of address, data_in, and data_out, respectively. write_en, read_en, and ram_en define the control signals in memory. <pin> defines the name of each control signal. The <assert_state> defines the active state of the control signal, which is marked high or low.

Next, we define the read / write ports and their behavior. The port type is one of read_port, write_port, and read_write_port. Within the type of port you define the cycle type. The cycle type consists of read_cycle and write_cycle. Within each cycle type, read / write operations are described.

20 is a diagram illustrating an embodiment of a read / write operation waveform of a memory model. The definition of the memory model operating with the above operating waveform is as follows.

model RAM1 (// Memory model name RAM1 Start model definition

address ADDR 4 // address port name ADDR, bandwidth 4bit

data_in DIN 8 // data_in port name DIN, bandwidth 8bit

data_out DOUT 8 // data_out port name DOUT, bandwidth 8bit

write_en WEN high // write_en portname WEN, active high

read_en REN high // read_en portname REN, active high

read_write_port (// read_write_port porttype definition

read_cycle (// read_cycle read operation description

change ADDR // change of address value

wait // advance one clock time

assert REN // read_en control signal active change

expect DOUT // specify when to output data_out

wait // advance one clock time

wait // advance one clock time

)

write_cycle (// write_cycle write operation description

change ADDR // change of address value

change DIN // Display data_in value change

wait // advance one clock time

assert WEN // write_en control signal active

wait // proceed one clock cycle

wait // proceed one clock cycle

)

)

 )

After defining the read / write port and operation, the next step is to register the created memory model. 21 is a diagram illustrating a memory model registration user interface. In the above process, the generated memory models may be registered regardless of the type and number. If the types of memory models are the same, one BIST IP is generated regardless of the number. On the other hand, if there are other types of models regardless of the number of memories, BIST IPs are generated as many as the number of memory models.

FIG. 22 is a diagram illustrating a test algorithm application (MBIST configuration) user interface which is a final configuration step. FIG. The test algorithm application can be selected single or combination AF, SAF, TF, CFin, CFid, Flash Memory by fault in User Define Mode. Selecting by fault causes the optimized March sequence to be generated and executed inside the implemented program. Select March Algorithm selects the existing March Algorithm and applies it as it is. In addition, the dual-port algorithm and the multi-port algorithm can apply the algorithm proposed by Hamdioui (Journal of Memory Technology, Design and Testing). Algorithm that user wants, not algorithm provided by GenMBC, can be applied regardless of memory model. In this step, names of a clock signal and a reset signal are defined.

Finally, if the "MBIST Gen" button on the left menu bar shown in Figure 22 is selected, the BIST IP according to the structure set up to now is generated in the Verilog file format.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

Therefore, the memory self test circuit generator according to the present invention has an effect of efficiently testing regardless of the model and the number of semiconductor integrated memories by automatically generating a BIST IP by receiving information of a memory structure and a memory test algorithm from a user. .

Claims (14)

delete delete delete delete delete delete delete delete delete delete A test circuit generator for automatically generating board-level memory self test circuits, A memory model unit configured to receive memory model setting information for memory self test; A memory component to receive test information of a memory model generated for testing in the memory model unit; An algorithm component for receiving a type of algorithm to be applied to a memory test; And MBIST Gen execution unit generating and outputting a BIST Verilog file that can be embedded in a system on a chip (SoC) by applying the selected memory model and test algorithm Memory self-test circuit generator that is configured to include. delete The method of claim 11, And the test circuit generator is capable of testing any one of a single port memory, a dual port memory, a multi-port memory, and a flash memory. delete

Images