KR100959055B1 - System and embedded circuit for built-in self repair and built-in self test and method thereof - Google Patents

Abstract

The present invention can detect not only the existing defect model but also newly modeled defects using a finite state machine (FSM) and an algorithm that can be relocated to the rows and columns of the spare memory. It provides a built-in self-test circuit that can select and apply algorithms and a built-in recovery circuit to efficiently recover from detected defects. The memory device according to the present invention includes a data storage unit for storing data and outputting the stored data, an algorithm generator for selecting and outputting one of a plurality of algorithms in response to a selection signal input from the outside, and an output from the algorithm generator. And a test control unit for detecting a defective area by testing the data storage unit using an algorithm. According to the present invention, in the case of an SOC including various memories, the SOC can be normally operated by detecting a defect even when various defects occur, and the memory device in the SOC can be repaired and used by using a spare row and column memory. The yield of memory can be increased.

Embedded memory, self test, self repair, like element, finite state machine

Description

Built-in memory device and system with programmable self-test and its self-healing method {SYSTEM AND EMBEDDED CIRCUIT FOR BUILT-IN SELF REPAIR AND BUILT-IN SELF TEST AND METHOD THEREOF}

The present invention relates to a self-healing circuit of a memory, and in particular, to test a variety of internal memory contained in a System On Chip (SOC) through a programmable self-test algorithm to replace the detected defective memory portion with a spare memory The present invention relates to a self-healing circuit and a method thereof that can be recovered.

As the size of each component of the memory decreases, the probability of occurrence of a defect increases and the recovery of the generated defect becomes more complicated. In particular, in conjunction with the development of portable devices, circuits for performing various functions are integrated and produced on one chip. One such SOC contains multiple circuits, and the size of the embedded memory included to support such a variety of functions is increasing, resulting in increased post-production testing time. As a result, the increased time for testing a memory device has resulted in a higher cost of testing the memory device than the cost of producing one transistor.

The internal memory included in the SOC is growing, and according to the SIA (Semiconductor Industry Association) technical report, the area of the internal memory in 2014 will be 94% of the total system-on-chip (SOC). have. Thus, to reduce the time and cost of testing SOC, improving the process of testing internal memory has the greatest impact.

As the amount of internal memory continues to grow, while the size of the SOC decreases, the testing process becomes more complex, requiring complex algorithms and a lot of time. Therefore, the method of accessing and testing the internal memory from the outside using a semiconductor automatic test equipment (ATE) requires a very long test time, and at-speed testing cannot be performed. In addition, as the proportion of internal memory increases, not only the efficiency of the test but also the yield of the SOC containing the internal memory is an important problem.

In order to efficiently test the internal memory, it is proposed that the memory device includes a built-in self-test (BIST) circuit therein, and the test method is not merely included in the memory device. The excellence and efficiency of implementation should also be considered. Furthermore, in order to increase the yield of SOC, it is proposed that the memory device include a built-in self-repair (BISR) circuit to repair the defects detected by the test and its use is widely confirmed. It is being treated. Here, the built-in self-repair (BISR) of the memory device is not only built-in self test (BIST) for defect detection, but also built-in self-diagnostics (BISD), self-redundancy analysis (BIRA). It is accompanied by several mechanisms.

Built-in Self Test has presented a method for solving test problems using existing semiconductor automatic test equipment (ATE). Built-in self-test can implement the appropriate memory test algorithm for the chip under test. The built-in memory test is built into the memory device, which eliminates the need for a large number of ports for channels to be connected to external test equipment, and allows for testing at the operating speed of the memory device, enabling at-speed testing. It is possible. However, such a test structure could apply only one test algorithm that was already determined at the time of manufacturing a memory device.

The test using only one algorithm has the following problems. For the first reason, memory devices are difficult to cope with when the necessary test algorithms are changed during the memory production process. In the early stages of production, algorithms are needed to find various defects, even if they are complex and time consuming.However, as the production is repeated repeatedly, the production process is stabilized and yield is increased. Therefore, a simpler and faster algorithm can be used to test a memory device. For example, if a problem arises in the repetitive production of a memory device and can be stably produced, testing may be omitted.

Secondly, an SOC can contain various types of memory blocks. Different memory types have different test algorithms. As a result, in order to support both the yield of the memory production process and the appropriate algorithms according to the memory blocks, the overhead of the SOC is increased because the test circuit implementing all the algorithms must be embedded.

To improve this, a Programmable Memory Built-in Self Test has been proposed that supports various test algorithms, which increases efficiency by allowing you to select the test algorithm that is appropriate for the environment at which the test is needed. It became possible. Various programmable in-memory self tests have been developed so far, which can be largely divided into microcode and finite state machine (FSM) approaches.

In general, the method using microcode is frequently used because it is easy to apply to various algorithms. In microcode testing, instructions are defined for each step of the algorithm. Each step of the algorithm is constituted by predefined instructions. In other words, each step of the algorithm is required for the test, and the command must be sent from the outside to the built-in self test each time. This method has the advantage of freely choosing the algorithm to use for testing. However, the complexity of embedded self-test circuits increases and the overhead increases. When testing the internal memory present in the SOC, the semiconductor automated test equipment (ATE) needs to send a large number of commands to perform the test. Therefore, a connection pin is required to receive external commands and the test time is increased. do.

Built-in programmable self-test using the finite state machine (FSM) allows each step of the algorithm to operate according to a predesigned finite state machine (FSM). Most of the built-in self-tests that support a single algorithm used this method. Minimal external connection pins are required to convert the built-in self-test based on the finite state machine (FSM) into a programmable structure. The reason is that the algorithm to be used for the test must be selected externally. In addition, embedded self-tests based on finite state machines (FSMs) must determine in advance the algorithms they can support. That is, the finite state machine (FSM) -based structure can support only a few predetermined algorithms, not all algorithms. However, the minimum external connection pins are required, which reduces the overhead compared to the micro code method, and allows for at-speed testing at the speed of memory operation, thus providing an efficient test speed. .

The relocation algorithm is applied to recover the memory device after the test, which detects defect information in the memory through the in-memory self test. Redundant row and column memory relocation algorithms are used to replace defective parts of memory with extra row and column memory so that the user can use them as if they were faultless.

If a row or column of internal memory is defective, relocating the defective part to rows and columns using both rows and columns in redundant memory is more difficult than relocating the defective part to extra memory rows or columns using only extra memory rows or columns. More efficient. However, the algorithm for relocating extra row and column memory using defective rows and columns is a non-deterministic polynomial-time hard (NP-hard) that is difficult to get an accurate answer other than checking all the cases. That's a problem.

To check whether the memory cells operate normally, read and write operations must be performed in a specific order. The number and order of read and write operations can vary depending on the type of fault you are trying to find. Recently, the most commonly used algorithm for detecting defects in internal memory is March test-based algorithm. March test algorithms consist of March elements.

March elements are composed of values applied to memory cells and read and write operations. When the memory size is N, the March elements perform multiple read and write operations allocated to each memory cell, increasing the address from 0 to N-1, or decreasing from N-1 to 0. To detect faults. For example, as if the element ((March Element) '(w0, r0)' performs the operation of writing '0' to the memory cell (w0) and confirms that the read value is '0' (r0), the address is This means repeating the same read and write operations to the next address in increasing direction. Another like element '(r1)' means to read the read value with '1' and perform the read operation in a certain direction regardless of the address increase / decrease direction, and '(w1)' means '1' in the memory cell. 'Means to perform a write operation in the direction of memory reduction.

1 shows various test algorithms based on March Elements. Since each algorithm is composed of different March elements, the types of defects that can be detected vary depending on the algorithm.

Figure 2 shows the defect detection rate for the types of defects possessed by March test-based algorithms. In the table, 'O' means all detectable, '△' means partially detectable, and 'X' means no detection at all. As can be seen from the table, only the 'March SS' algorithm can detect all types of defects.

The existing programmable built-in self test supported six algorithms: MATS +, March X, March C-, March A, March B, and Zero-One. As shown in FIG. 2, the algorithms supported by the existing built-in programmable self-testing structure include data destructive faults (Read Destructive Faults (RDF)) in read operations, disturb disturbances (WDF) in write operations, and data transfer. There is no guarantee that new modeled faults, such as coupling transition faults (CF), can be detected perfectly. In the early stages of SOC's internal memory production, various defects can occur in the memory, so testing with existing algorithms that do not detect newly defined defects reduces the reliability of the test and the finished product.

Programmable Memory To recover from faults found after the built-in self-test, the detected fault information is used to relocate the faulty location in the built-in memory to the spare spare row and column memory without defects, thereby eliminating any faults in the built-in memory. It can be used without impact. Spare memory analysis algorithms using semiconductor automated test equipment (ATE) have been proposed for relocating spare row and column memories. Although the built-in self-healing (BISR) structure of the memory device must be embedded in the circuit, the proposed algorithms are expensive to implement in the embedded circuit and cannot be implemented. Therefore, conventionally, a structure of a built-in self recovery (BISR) of a memory device using a spare memory word has been proposed. This method does not require spare memory analysis because it uses only spare row memory compared to other algorithms proposed in the present invention, which takes too long to find the optimal solution and requires complicated calculations. there was.

However, as described above, the test and recovery techniques used in the prior art do not completely detect various defects that may occur in the internal memory production process, and are not highly efficient in recovering from the detected defects.

The present invention can detect not only existing defect models but also newly modeled defects that can overcome the above-mentioned problems and provide transparency to the user, and can selectively apply more diverse algorithms according to stabilization of the memory production process. The present invention provides a built-in memory device and system and a self-healing method thereof.

The present invention uses a data storage unit for storing data and outputting the stored data, an algorithm generator for selecting and outputting one of a plurality of algorithms corresponding to a selection signal input from the outside, and an algorithm output from the algorithm generator. An internal memory device including a test controller for testing a data storage unit to detect a defective area is provided.

In addition, the present invention implements a built-in memory circuit including a memory for storing data and outputting the stored data and an extra spare memory, and a test algorithm corresponding to a selection signal input from an external device to correct defects in the memory in the internal memory circuit. A system includes a programmable memory self-test circuit for detecting and notifying a defect result, and a self-healing circuit for receiving a defect result and relocating the defective area of the memory to a spare memory to repair the defect.

Also, the present invention selects and executes one of the test algorithms embedded by an externally selected selection signal, and then tests a defect in the internal memory, and uses the address and data included in the defect information as a result of the test. Executing a relocation algorithm for determining whether to relocate a defective location of the memory to a spare row memory or a spare column memory, and to replace a defective portion of the internal memory according to a signal generated in the relocation algorithm step. The present invention provides a self-healing method of an internal memory device, which includes recovering a defect.

In the structure of the present invention, by using a finite state machine (FSM) and an algorithm that can be relocated to the rows and columns of the spare memory, not only the existing defect model but also newly modeled defects can be detected. We propose a built-in self test structure that can select and apply a wider variety of algorithms. In particular, in addition to verifying the presence of memory defects through programmable self-testing of the built-in memory, the faulty information can be used to relocate the defective portion of memory to spare row and column memory using efficient algorithms, thereby allowing the user to It is to solve the conventional problem by providing a memory self-defect recovery apparatus and a method for using the memory as a normal memory.

According to the present invention, in the case of an SOC including various memories, the SOC can be normally operated by detecting a defect even when various defects occur, and the memory devices in the SOC can be repaired and used by using a spare row and column memory. This has the advantage of increasing memory yield.

In addition, the present invention relates to an internal memory self-healing design incorporating programmable self-test, which can increase test efficiency by selectively executing a suitable test algorithm corresponding to the kind of defects that may occur in a memory device during manufacturing. .

Furthermore, a feature of the present invention is that it is possible to apply test algorithms corresponding to defects that may occur in each memory device when several types of memory devices are included in the SOC, and to use each memory by using independent spare row / column memory. The advantage is that all the faults of the device can be rearranged.

The foregoing and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which: There will be. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a table for explaining an algorithm set in an embedded self test circuit according to an embodiment of the present invention and a selection number for selecting an algorithm.

As shown, the programmable self-test method according to an embodiment of the present invention consists of a total of seven algorithms. A total of seven algorithms include the March SS algorithm, which can detect all the defects modeled to date to detect many defects at the beginning of the memory production process. Algorithms such as MATS + are as simple and fast as possible.

The algorithm selection number in FIG. 3 is a selection number of an algorithm to be selected for executing a built-in self test in an external semiconductor automatic inspection equipment (ATE). The selection number consists of 3 bits to select a total of seven algorithms. Each algorithm indicated by the selection number includes a number of March elements, each of which consists of a 5-bit signal. The most significant bit of the code for each element represents the increment of the address pointing to the memory to which the element is applied and tested. In this case, '1' is assigned to the most significant bit for elements that increase or decrease the address freely, and '0' is assigned to the most significant bit for elements that test while decreasing the address. In addition, the remaining 4-bit code indicating the element indicates a read / write operation except whether the address is increased or decreased, and the 4-bit code arranges the elements used in the entire algorithm and gives the same numbers to the same operations. For example, all algorithms are supposed to start with the element '(w0)'. Since '(w0)' is a free movement of the address, the most significant bit is assigned to '1' and the '(w0)' The 4-bit code of '0001', which means the operation of writing '0' to the memory cell, was assigned to complete the code of the entire 5-bit gut element.

FIG. 4 is a table for explaining algorithm codes indicating elements as if included in the algorithm shown in FIG.

The self test according to the present invention includes a total of seven algorithms. The total number of March elements included in the seven algorithms is 35, but since the same code is assigned to the same March element, the code from 1 to 14 is assigned to the March Elements. All seven algorithms can be represented. March elements arranged through such a collecting process may be represented by 14 four-bit codes [3: 0] as described in FIG. 4.

5 is a block diagram illustrating a test circuit 100 embedded in an SOC for self test according to an exemplary embodiment of the present invention.

As shown, the test circuit 100 selects an algorithm by a control signal input from the outside and the algorithm generator 10 and the delivered march for delivering the elements of the selected algorithm in order. The test controller 50 applies a test element by applying the elements to the internal memory 20. Here, the test control unit 50 includes an address generator 80 for generating an address, a signal generator 70 for generating a signal for executing a read / write operation in the internal memory 20, and an internal memory 20. It includes a comparator 60 for comparing the read value with the value in the normal operation.

First, when a control signal (BIST_EN, AL_Select) for selecting an algorithm is input from the semiconductor automatic inspection equipment (ATE) at the beginning of the test, the algorithm generator 10 selects one of all algorithms included and fits the selected algorithm. Prepare the Elements. The prepared elements are converted into codes MM_code and transferred to the test controller 50 after the activation of the start signal Start_ME and before the activation of the test end signal End_of_BIST. In response to the input code (MM_code), the test control unit 50 includes an internal command (Ctrl) for a read / write operation to execute an element, input data (InData) required for read / write, and a read / write operation. Create an address Addr in the internal memory 20 to be executed.

When the test is in progress, the test controller 50 has no address corresponding to the input code MM_code or cannot be accessed with the corresponding address, or when the data OutData output from the internal memory 20 is incorrect. It outputs fault detection signals (Fault_Detection, Fault_Address, Fault_Data) corresponding to.

FIG. 6 is a block diagram for describing in detail the algorithm generator 10 illustrated in FIG. 5.

As shown, the algorithm generating unit 10 receives a minimum control signal required for a test from an external semiconductor automatic inspection equipment (ATE), the control signal and code corresponding to various test algorithms included in itself And so on.

The control signals input from the external semiconductor automatic inspection equipment (ATE) include a test enable signal (BIST_EN) for executing a built-in self test, a 3-bit algorithm selection signal (AL_Select) for selecting one of a plurality of included algorithms, There is a clock signal Clk and a reset signal Rst for resetting the test. In addition, the algorithm generator 10 receives the end signal End_MM for requesting the element as if the test control unit 50 is the next step after the test proceeds according to the input code of the element.

Corresponding to the above-described signals, the algorithm generating unit 10 is a code (MM_code) consisting of an element (March Element) for testing and whether to increase or decrease the address (MM_code), the element according to the start of the selected test algorithm The start signal Start_ME for notifying the transmission of the signal, the test end signal End_of_BIST for notifying that all the tests have been completed, and the back data signal BG_CNT for changing the background data are output to the test controller 50.

FIG. 7 is a conceptual diagram illustrating a finite state machine (FSM) constituting an operation of the algorithm generator 10 illustrated in FIG. 6.

As shown, the operation of the algorithm generator 10 can be described as a finite state machine (FSM). When there is no input from the outside, the algorithm generator 10 waits for an external input in an idle state (Idle, S12). When the test enable signal BIST_EN is applied, the algorithm generator 10 switches to the testable state (BIST Enable, S14). When the algorithm select signal AL_Select is input from the outside, the algorithm is prepared and the algorithm is prepared. Accordingly, the start signal Start_ME is applied to the test controller 50 indicating that the element is generated. Thereafter, the algorithm generating unit 10 is switched from the test control unit 50 to the request waiting state (Wait Request ME, S16) which waits until the next request for the element is completed. At this time, when the end signal End_MM is input from the test control unit 50, the algorithm generating unit 10 switches to the element transmission state Send March Element S18. In the element transmission state S18, the algorithm generator 10 determines whether the element corresponding to the selected algorithm remains and what data are required accordingly to notify the end of the selected test is switched to the idle state S12. If it is necessary to proceed with the test, it is switched to the testable state (S14) and the request waiting state (S16).

Specifically, when the algorithm generator 10 receives the end signal End_MM, which is a signal for requesting the element of the next step, from the test controller 50, the algorithm generator 10 switches to the element transmission state S18. Then, the elements (March Elements) of the selected algorithm are converted into the code (MM_code), and the state is returned to the request waiting state (S16). After passing the element, that is, the code (MM_code), it is converted to the element transfer state (S18) again and repeatedly executed this process, so that all the March elements included in the corresponding algorithm are included in the test control unit ( 50). In addition, the algorithm generating unit 10 increases the back data signal BG_CNT that changes the background data after sending the last element, and becomes a testable state S14 and applies the changed background data to the start signal Start_ME. ) Is transferred to the test control unit 50 and the state is switched to the request waiting state S16 to execute the new algorithm again. After all the tests that apply all the background data by repeating the above process are executed, the algorithm generator 10 notifies the end of the built-in self test by applying the test end signal End_of_BIST.

FIG. 8 is a conceptual diagram illustrating a finite state machine (FSM) constituting an operation of the test controller 50 illustrated in FIG. 5.

As illustrated, the test controller 50 directly tests the internal memory 20 in response to the signals input from the algorithm generator 10. In detail, the test control unit 50 includes three modules for directly testing the internal memory 20, namely, an address generator 80 for generating an address and a read / write operation for the internal memory 20. A read / write signal generator 70 for generating a signal and a comparator 60 for comparing the value read from the memory with the value in the normal operation.

Hereinafter, the operation of the test controller 50 will be described with reference to the finite state machine FSM shown in FIG. 8.

The test controller 50 sends the most significant bit of the code MM_code received from the algorithm generator 10 to the address generator 80 and the rest to the signal generator 70. When the most significant bit (Adr_direc, MM_code [4]) of the input code (MM_code) is '1', the address generator 80 increases the address to generate a new address, and if it is '0', decreases the address. The new address is generated and then transferred to the internal memory 20. In addition, when the operation end signal End_OP is input from the signal generator 70 to indicate the end of each detailed operation of the element, the address generator 80 generates a new address and delivers it to the signal generator 70 again.

The signal generator 70 has the remainder (MM_code [3: 0]) of the code (MM_code) except for the most significant bits (Adr_direc, MM_code [4]) and performs the read / write operation of the corresponding March element. Raise accordingly. For example, referring to FIG. 4, in the case of an M3 March Element meaning an operation of (r1, w0), an input code is '0011'. First, when the code '0011' is input in the idle state (Idle, [000]), the signal generator 70 is switched to the first state [100]. Here, the first state [100] is a state of performing a process of comparing the read '1' value (r1). After the operation is completed, the signal generator 70 moves to the second state [001]. The second state [001] refers to a state in which a process of writing a value '0' into the memory (w0) is performed. Upon completion, the signal generator 70 returns to the idle state [000] again and sends an operation end signal End_OP to the address generator 80 to increase or decrease the address.

The signal generator 70 generates a control signal Ctrl for controlling the internal memory 20 in each operation state (for example, r0 / r1 / w0 / w1) defined in the element. The generated control signal Ctrl may include a Lars signal _RAS for informing a row address, a Cass signal _CAS for informing a column address, and storing data in the internal memory 20. A write enable signal _WE and an output enable signal _OE for reading data of a corresponding address from the internal memory 20. In addition, the signal generator 70 transfers the row and column addresses Addr received from the address generator 80. As a result, when testing a write operation, the signal generator 70 outputs input data InData for writing to the internal memory 20. In contrast, in the case of testing a read operation, output data OutData read in the internal memory 20 is output to the comparator 60 included in the test controller 50.

The comparator 60 compares the output data (OutData) output from the internal memory 20 with a value expected by the selected algorithm, and determines that a fault has occurred when it is different, and indicates fault data (Fault_Data), which means defective data, and It will send a fault detection signal (Fault_detection) indicating that it has detected a fault. In addition, the comparator 60 outputs a fault detection signal (Fault_detection) signal to the address generator 80 so that the address generator 80 can output a fault address (Fault_Address) to the outside.

If defects are found in the internal memory to increase production yields, a recovery action is needed to relocate the defects to redundant memory so that they appear to work normally regardless of the defects from the outside. At this time, if the relocation processing space for replacing all the defective parts of the internal memory is small, even if it is possible to recover through the relocation to the defective location, the information of the defective location cannot be contained, and as a result, the entire operation of the internal memory is error. Occurs. However, if the storage space is enlarged to increase in size, there are limitations in increasing the amount of redundant memory due to various problems caused by overhead in the SOC (degradation, power consumption, etc.).

FIG. 9 is a pseudo code for describing a method of recovering a memory device, according to an exemplary embodiment. Referring to FIG.

In the memory device according to an embodiment of the present invention, the space for storing the defective location and the address information is the sum of the number of spare row memories and the number of spare column memories. If the defect of the internal memory exceeds the sum of the spare row memory count and the spare column memory count, the relocation space is insufficient and the relocation fails.

To compensate for this, select the one with the most defective rows based on the defective locations in the internal memory and the locations where the defective addresses are stored. The result of the algorithm is the same even on a column basis. In the present invention, the most defective row is rearranged into a spare row memory. If two or more rows with the highest number of defective cells appear, the first row is selected as a spare row memory. Next, in the first defective cell of the defective address, compare the number of defective cells in the row of that address with the number of defective cells in the column. If the number of defects is in a row, the corresponding row of the internal memory is relocated to the spare row memory. If the number of defects is a large number, the corresponding column of the internal memory is relocated to the spare column memory.

Before comparing the number of defective cells in a row and the number of defective defects in a column, two things are largely calculated first. First, make sure that the faulty cell of the most defective row is located in the most defective column. Because the most defective rows are unconditionally relocated to spare row memory, if you relocate defects at both the rows relocated to spare row memory and the location of the most defective columns (that is, the defects at the overlapping locations) to spare column memory. The defect will be relocated to two parts: spare row memory and spare column memory. This makes the operation much more complicated when data is updated in either the spare row memory or the spare column memory, so that the rest must be updated as well to prevent errors. Therefore, when the defective position of the most defective row and the defective cell overlap, the information is unconditionally relocated to the spare row memory.

Second, if there are more than one defective cell at the same address, if one cell defect is relocated to spare column memory, all cells at the same address must be relocated to spare column memory to prevent sharing of the defective cell. Also, if the column location of a defective cell is relocated to spare column memory by another address, it must also be relocated to spare column memory to prevent sharing of the defect.

Referring to Fig. 9, the relocation algorithm of the above description is explained. After the built-in self test (BIST) stores the defective and defective locations in the internal memory, an algorithm is started to relocate the information to the spare row and column memory at the defective location. First, a row of the number of cells having the most defective cell is selected through defective information according to a relocation algorithm (Search_TheMostFaultyRowCell ()). Thereafter, the cells included in the address (row) containing the most defective cell are rearranged (Reallocation_RowSpareMemory ()) to the spare row memory. If it finds defective information and it is not the address containing the most defective cell, it is determined whether the cell defect location of the row and column with the highest number of defective cells overlaps (TheMostFaultyRowCell_Overlap). Relocate to spare row memory (Reallocation_RowSpareMemory ()).

If after finding faulty information, it does not overlap the most defective row, and another defective cell at the same address has already been relocated to spare column memory (Already_ReallocationColumnSpareMemory_atLocation) or has already been relocated to spare column memory by a different address (Already_ReallocationColumnSpareMemory_atFaultyAddress). If so, relocate the defective cell to spare row memory.

If the location of the defective cell is not the above three cases, and the number of defective cells in the row (TheNumberOfRowFaultyCell) and the number of columns (TheNumberOfColumnFaultyCell) are compared and the number of defective cells in the column is large, the location of the cells is relocated to spare column memory. Otherwise, it is relocated to spare row memory.

FIG. 10 is a conceptual diagram illustrating that a defective cell is rearranged into a spare row memory and a spare column memory according to the relocation algorithm described in FIG. 9. Specifically, this example illustrates the relocation process when there are four 5-bit addresses, four row spare memories, and four column spare memories.

First, as soon as a defect is confirmed through an internal self-test on the internal memory, the defective address and the defective location information of the internal memory are stored in the storage circuit 210 in the relocation algorithm circuit, and then the defective location is stored in the spare column memory 440. ) And spare row memory 460.

As shown, the address (defective address) of the row containing the most defective cell among the defective information is found and all information of the corresponding address is rearranged in the row spare memory 460. In FIG. 10, the defective address '10100' is first relocated to the address '1000' in the spare row memory 460. In the storage circuit 210, at the address '11101' with the next defective information, the number of defective cells in the column 02 of the first defective cell is compared with the number of defects in the row. However, cell positions 05, 06, 07 and 21 in the address '11101' are defective. This position is the position of the defect that overlaps with the column position of the most defective address '10100'. Thus, the address '11101' is relocated to the address '0100' in the spare row memory 460.

In the column position '09' of the row address '00010' of the next storage circuit 210, there is no overlapping with the position of the column defective cell of the most defective row, and it has been previously relocated to the spare column memory at the same address. None compare three defective cells in a column position with two defective cells in a row. Due to the large number of defective cells in the column, the '09' in the storage circuit 210 column is relocated to the '1000' portion of the spare column memory 440. Column position '25' of the next defective cell of the same row address' 00010 'has been relocated to column spare memory 440 from the previous column position' 09 ', so column position' 25 'is also an address within column spare memory 440' Relocated to 0100 '.

Next defective location The defective cell location at row addresses '00011' and '01101' is '09' in the column. Since column '09' has been completely relocated to the spare column memory from the previous row address '00010', column '09' of the row addresses '00011' and '01101' has also been relocated to the address '1000' in the spare column memory 440. The defective cell location column '25' of the defective row address '00011' is also relocated to the address '0100' in the spare column memory 440.

The defective row addresses '00100' and '00101' in the storage circuit 210 are also rearranged at the row address '00010' with the column defective cell position '25' to the address '0100' in the spare column memory and the row address '00100'. The defective cell location column '25' of '00101' is relocated to the address '0100' in the spare column memory 460. The defective cell location columns '11' through '14' of the next row address '01010' have four and one defective cells, respectively, in terms of the row and column address, so the address '0010' in the spare row memory 460 Relocate to

FIG. 11 is a conceptual diagram illustrating a result output through the relocation algorithm described with reference to FIG. 10.

As shown, the final information output through the relocation algorithm is faulty data at faulty locations in the internal memory, faulty fault addresses in the internal memory, spare row and column memories 460 and 440. A total of four spare memory addresses, a row memory address and a row / column flag for relocation to the spare row memory 460 and the spare column memory 440.

If the row / column flag information is '0', the row / column flag information is rearranged to the spare row memory 460, and if '1', the row / column flag information is rearranged to the spare column memory 440. The spare memory address has a number of bits that can be rearranged into the spare row and column memories 460 and 440. When the spare row memory 460 is relocated, the entire spare row memory is relocated, so it is not necessary to check the defective location and is represented by '.'. Because of the relocation, you need to locate the faulty internal memory. Thus, the location of a defective cell is represented by a '1' and the location of a defective cell is represented by a '0'. Finally, the location of the defective address in the internal memory is represented by the defective address.

The address representation of the spare row and column memories 460 and 440 is not represented as a binary code, but as an address having the number of bits as many as the number of rows and columns of the spare row and column memories 460 and 440. For example, if the number of rows of the spare column memory 460 is four, it is generally represented by four binary addresses (00, 01, 10, 11). However, in the present invention, four addresses are designated as '1000', '0100'. ',' 0010 'and' 0001 '. That is, although it can be represented by 2 bits of address in a general manner, the structure of the present invention requires 4 bits of address. The reason for this expression is that if two defective locations are located at the same time (00, 01), the general method requires two transmissions of two bits each, but the method of the present invention uses four bits (1100) after an OR operation. This is because you only need to send it once. In addition, if the 8-bit address is consumed in the addresses of the spare row and column memories 460 and 440 as in a general manner, duplicate data values for accessing the spare row and column memories may be stored. If you set the address as a 4-bit address, you can avoid the redundant storage of data.

This relocation algorithm processes the cell location and address of the defective memory into information that can be relocated into spare row and column memory. That is, the final processed information includes four pieces of information: a defective location in internal memory, a defective address in internal memory, an address to be relocated to spare row and column memory, and a flag to be relocated to spare row memory or spare column memory. This information is output from the control circuit containing the relocation algorithm. With the output relocation information, you can use spare row and column memory without inputting or outputting data to or from the defective location in the internal memory so that the user can use it as if the data were entered or output to the internal memory at the defective address. It can be used like a faultless internal memory.

12 is a block diagram illustrating a built-in self-recoverable memory device according to an embodiment of the present invention.

As shown, the memory device includes a programmable memory self-test circuit 100, a relocation algorithm circuit 200, a data input / output relocation circuit 300, and an internal memory circuit 400 that can change the test algorithm according to circumstances. ). The programmable memory self test circuit 100 may be implemented by applying the algorithm generator 10 and the test controller 50 included in the built-in test circuit 100 described with reference to FIG. 5, and the reposition algorithm 200 ) And the data input / output relocation circuit 300 may employ the relocation algorithm described in FIGS. 9-11. In addition, the internal memory circuit 400 may include an internal memory 420 for storing data and an extra memory for replacing defective cells detected in the internal memory (that is, the spare row memory 460 and the spare column memory 440). ) Is included.

The number of bits of the control signal and data shown in FIG. 12 has 5 bits of the address of the internal memory, 4 rows / columns of the spare row memory 460 and the spare column memory 440, and data has 32 bits. For example is shown. However, these can be changed as many as the size of the memory device required by the SOC or system. The operation of the internal self-healing memory device is as follows.

Programmable memory self-test circuit 100 allows faulty address and faulty data to be sent to relocation algorithm circuit 200 along with fault detection signals in the internal memory. do. The relocation algorithm circuit 200 sends the final information shown in FIG. 11 to the data input / output relocation circuit 300 to relocate the defective cell using the information. The data input / output relocation circuit 300 that receives the relocation information through the relocation algorithm circuit 200 replaces the data accessing the defective location of the internal memory with the normal data.

FIG. 13 is a block diagram illustrating the configuration of the data input / output relocation circuit 300 shown in FIG. 12.

As shown, the data input / output relocation circuit 300 connected to the relocation algorithm circuit 200 and the internal memory circuit 400 includes a defect address comparison unit 320, a spare memory address relocation circuit 340, and data. A relocation circuit 360. Hereinafter, the operation of the data input / output relocation circuit 300 will be described by applying the relocation algorithm described with reference to FIG. 11.

The relocation algorithm circuit 200 outputs a row / column flag to distinguish between the data to be relocated to the spare row memory 460 and the spare column memory 440. When the defective data is relocated to the spare row memory 460, since the entire 32-bit data is relocated to the spare row memory 460, the defective data is relocated to the spare row memory 460 through the data relocator 360 or the spare row. The memory 460 is replaced and output.

If the data is relocated to the spare column memory 440, the inputted data approaches a defective location of the internal memory 420 by using faulty data (Faulty Address) output from the relocation algorithm circuit 200. In this case, the relocation algorithm circuit 200 extracts data that approaches a defective location of the internal memory 420 and sends the data to the spare memory address relocation circuit 340.

The spare memory address relocation circuit 340 in the data input / output relocation circuit 300 selects an address in the spare row memory 460 or the spare column memory 440 to relocate the data transferred through the data relocation unit 360. Relocate data to spare row or column memories 460 and 440.

The write operation will be described with an example. The case in which the 5-bit address '11101' is written in the internal memory 420 to write 32-bit data 'FF000000h' will be described. First, the defect address comparator 320 compares the address '11101' of the internal memory 420 with the spare row and column memories 460 and 440 due to internal defect cells.

When it is confirmed that the relocated address, the relocation notification signal Hit is activated from the defective address comparator and input to the data relocating unit 360. At this time, when the row / column flag signal is '0', 32-bit data input from the relocation algorithm circuit 200 is input to the data relocation circuit 200, and the address '0100' of the spare row memory 460 is a spare memory. The address relocator 340 is input. The 32-bit data value 'FF000000h' stored in the '0100' position of the spare row memory 460 is stored according to the value '0100' inputted to the spare memory address relocator 340 when the row / column flag signal is '0'. do.

The following describes the read operation. For example, a case in which the data value at the 5-bit address '11101' is read in the internal memory 420 will be described. First, the address '11101' of the internal memory 420 is compared and checked by the defective address comparator 320 to be rearranged to the spare row and column memories 460 and 440. When it is confirmed that the address is relocated, the relocation notification signal Hit is activated from the defective address comparator 320 and the row / column flag signal is output as '0' from the relocation algorithm circuit 200 to the internal memory 420. The stored value is input to the data relocator 360. In addition, the address '0100' of the spare row memory 460 is input to the spare memory address relocator 340. The data value 'FF000000h' stored at the position '0100' of the spare row memory 460 is output according to the row / column flag signal '0' and the value '0100' input to the spare memory address relocator 340.

Let's look at another case. The 32-bit data 'FF407000h' is written to the 5-bit address '00011' of the internal memory 420. Similarly, in this case, the address '00011' of the internal memory is compared and confirmed by the defective address comparator 320 to be relocated to the spare row and column memories 460 and 440.

When it is confirmed that the relocated address, the relocation notification signal Hit is activated from the defective address comparator 320 and input to the data relocator 360. At that time, the row / column flag signal '1' and defective data are input from the relocation algorithm circuit 200 to the data relocation unit 360, and the address value '1100' of the spare memory is transferred to the spare memory address relocation unit 340. Is entered. If the row / column flag signal '1', '1100' refers to the address of the spare column memory 440, and it may be determined that the defective cell has been relocated to the spare column memory 440.

The defective cell location value is transmitted to the spare memory address relocation circuit 340 as an input value based on the faulty data value (Faulty Data: 00000000010000000000000001000000) input from the relocation algorithm circuit 200 to the data relocation unit 360. That is, in the position of the defective cell, '0' and '1' corresponding to the seventh and twenty-third of the data input values corresponding to the seventh and twenty-thirds are transferred to the spare memory address relocation circuit 340 as an input value. The address '1100' of the spare column memory received from the relocation algorithm circuit 200 is divided into '1000' and '0100', and the data received from the data relocator 360 at the address '1000' of the spare column memory 440. The '1' corresponding to the 23rd and the '0' corresponding to the 7th are written in the address '0100'.

The 32-bit data received, including the cell in the defective location, performs a normal write operation to the '00011' address in the internal memory. The position value of the defective cell is rearranged to the spare column memory 440, so it is irrelevant to write to the internal memory 420.

In another case, an example of reading data from the 5-bit address '00011' into the internal memory 420 will be described. First, the address '00011' of the internal memory 420 is compared with the defective row comparator 320 to determine whether it is relocated to the spare row and column memories 460 and 440.

When it is confirmed that the relocated address, the relocation notification signal Hit is activated from the defective address comparator 320 and input to the data relocating unit 360. At that time, the row / column flag signal '1' and defective data are input from the relocation algorithm circuit 200 to the data relocation unit 360, and the address '1100' of the spare memory is input to the spare memory address relocation unit 3400. If the row / column flag signal is '1', it can be seen that the defective cell has been rearranged to the spare column memory 440.

The address '1100' of the spare column memory 440 received from the relocation algorithm circuit 200 is divided into '1000' and '0100'. The values '1' and '0' of the addresses '1000' and '0100' of the spare row memory 440 are input to the spare memory address relocator 340. At this time, the data value corresponding to the address '00011' of the internal memory 420 is input to the data relocator 360. The data repositioning unit 360 replaces the data values with '0' and '1' at the defective cell positions 7 and 23 based on the faulty data (Faulty Data: 00000000010000000000000001000000) value of the inputted defective cell position. Export to data output.

As described above, the memory device according to the present invention includes circuits for self-testing and self-healing, and the algorithm can be selected according to the situation, so that the efficiency of the test and recovery becomes very high. Therefore, it is possible to improve the yield and reduce the test time in the manufacture of the memory device. In addition, the memory device included in the SOC has also been able to recover from various defects that may occur by incorporating the above-described self-test and self-healing circuits.

As described above, the method of the present invention may be implemented as a program and stored in a recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.) in a computer-readable form. Since this process can be easily implemented by those skilled in the art will not be described in more detail. In addition, the present invention described above is capable of various substitutions, modifications and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains to the embodiments and It is not limited by the accompanying drawings.

1 is a table for explaining various test algorithms based on March elements.

FIG. 2 is a table showing defect detection rates for types of defects for each test based algorithm.

3 is a table for explaining an algorithm set in an embedded self test circuit according to an embodiment of the present invention and a selection number for selecting an algorithm.

FIG. 4 is a table for explaining algorithm codes indicating elements as if included in the algorithm shown in FIG.

5 is a block diagram illustrating a test circuit embedded in an SOC for a self test according to an embodiment of the present invention.

FIG. 6 is a block diagram for describing in detail the algorithm generator illustrated in FIG. 5.

FIG. 7 is a conceptual diagram illustrating a finite state machine (FSM) constituting an operation of the algorithm generator illustrated in FIG. 6.

FIG. 8 is a conceptual diagram illustrating a finite state machine (FSM) constituting an operation of the test controller illustrated in FIG. 5.

FIG. 9 is a pseudo code for describing a method of recovering a memory device, according to an exemplary embodiment. Referring to FIG.

FIG. 10 is a conceptual diagram illustrating that a defective cell is rearranged into a spare row memory and a spare column memory according to the relocation algorithm described with reference to FIG. 9.

FIG. 11 is a conceptual diagram illustrating a result output through the relocation algorithm described with reference to FIG. 10.

12 is a block diagram illustrating a built-in self-recoverable memory device according to an embodiment of the present invention.

FIG. 13 is a block diagram illustrating a configuration of a data input / output relocation circuit shown in FIG. 12.

Claims (20)

A data storage unit for storing data and outputting the stored data; Corresponding to the selection signal input from the outside, 14 kinds of elements included in the MATS +, March X, March C-, March B, March U, March LR, and March SS algorithms are classified into four bit codes. An algorithm generator for outputting a 4-bit code when selecting one of the algorithms; And And a test controller configured to test the data storage unit to detect a defective area by using the algorithm output from the algorithm generator. The method of claim 1, The selection signal is composed of 3 bits, and each of the MATS +, March X, March C-, March B, March U, March LR, and March SS algorithms have different March Elements in the data storage unit. An internal memory device, characterized in that detectable defect information is different. delete delete 3. The method of claim 2, And the algorithm generator has four operation modes: an idle state, a testable state, a request wait state, and an element transfer state. The method of claim 1, The test control unit An address generator for increasing or decreasing the address of the data storage unit to be tested by receiving the most significant bit of the code input from the algorithm generator; A signal generator for receiving a remainder of the codes and generating a control signal for testing a read / write operation of the data storage unit; And And a comparator for comparing the data output from the data storage with reference data to determine whether there is a defect. The method of claim 6, The code has a total of 5 bits, and the control signal includes a row access related signal, a column access related signal, a write operation related signal, and a read operation related signal. The method of claim 6, The test control unit outputs a defect detection signal indicating whether there is a defect in the data storage unit, a defect address signal indicating an address of a defective place in the data storage unit, and defect data indicating data to be stored in a defective place. . An internal memory circuit including a memory for storing data and outputting the stored data and an extra spare memory; A programmable memory self test circuit for executing a test algorithm corresponding to an externally selected selection signal to detect a defect in the memory in the internal memory circuit and to notify a result of the defect; And Take the defect result Based on the result of the defect, a relocation algorithm is executed to the fault data at the defective location in the internal memory, the defective address in the internal memory, the spare memory address to be relocated to the spare row and column memory, and the spare row memory and the spare column memory. A relocation algorithm circuit for determining a spare memory including a spare row memory and a spare column memory to relocate defective areas in the internal memory by outputting a row / column flag for relocation; A defect address comparison unit for comparing and confirming whether an input address is an address relocated to the spare row and column memories, and data for relocating data corresponding to a combined position of the internal memory to the spare row or column memory A relocation algorithm and a spare memory address arranging unit configured to select an address in the spare row memory or the spare column memory and relocate data to be relocated to the spare row or column memory by being transferred through the data relocation unit, wherein the relocation algorithm is configured. And a self-healing circuit comprising data input / output relocation circuitry for relocating the data according to the circuit's decision and for accessing the relocated spare memory when externally accessing a defective area of the internal memory. The method of claim 9, The programmable memory self test circuit is In response to the selection signal 14 kinds of elements included in the MATS +, March X, March C-, March B, March U, March LR, and March SS algorithms are converted into four bit codes, respectively, to respond when one of the algorithms is selected. An algorithm generator for outputting a 4-bit code; And And a test control unit which detects a defective area by testing the memory using an algorithm output from the algorithm generating unit. The method of claim 10, The selection signal is composed of 3 bits and the MATS +, March X, March C-, March B, March U, March LR, and March SS algorithms, each having different March Elements, so that the data storage unit System characterized in that the defect information that can be detected in the different. delete delete delete delete delete In response to the externally selected selection signal, 14 kinds of elements included in the MATS +, March X, March C-, March B, March U, March LR, and March SS algorithms are classified into four bit codes. When selecting one of the algorithms, output the corresponding 4-bit code, The internal memory is tested by executing a test algorithm corresponding to the output 4-bit code, and a defect detection signal indicating whether the internal memory is defective, a defect address signal indicating an address of a defect, and data to be stored in a defect location Outputting and testing a defect of the internal memory; The one with the most defects in terms of rows, in order to determine whether to replace the defective location of the internal memory with the spare row memory or the spare column memory using the address and data included in the defect information that is the result of the test. Select the row of, Verify that the fault cell position of the most defective row overlaps the position of the fault column to compare the position of the column, Verify that the column position of the defective cell has been relocated to spare column memory by another address, Executing a relocation algorithm by comparing the number of defective cells in the row of that address with the number of defective cell failures in the column in the first defective cell of the next defective address; And And recovering a defect by replacing a defective portion of the internal memory with the spare row and column memories according to a signal generated in the relocation algorithm step. delete delete The method of claim 17, The repairing of the fault may include reading and storing the internal memory by using the data of the faulty internal memory as a spare row and column memory instead of the setting value of the relocation algorithm circuit in executing the relocation algorithm. When the write operation is performed, the spare row and column memories also perform the same read and write operations as the internal memory.

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