JPH10209376A - System and method for testing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cut down the clock cycle during the testing time of a JTAG circuit. SOLUTION: The system is provided with a semiconductor chip forming a functional circuit for discharging the function in a specific mode and a test circuit for testing the correct operation of the functional circuit. The test circuit includes a decoding circuit (command decoding) decoding command data, a command holding register (command holding register) storing the decoded command and a command decoding test register (command decoding test register) outputting the decoded command data for comparing with the prospective data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to IEEE Standard 1149.1-1990 or IEEE Standard 114.
9.1-1990 (IEEE standard 1149.1a-19)
93, including systems and methods for testing compatible devices or similar scan configurations, but for application specific integrated circuits (ASICs).
ationSpecific Integrated
Circuits) is preferably not limited to such tests.

[0002]

2. Description of the Related Art IEEE Standard 1149.1 (Joint Test Operation Group Standard: JTAG-Joint Test A)
Ction Group Standard) is ASI
A boundary scan configuration for the C interconnection test is created. The JTAG standard states that scan input (receives serial data at input pins) and ASIC (output pins
With scan output)
It is a scan type configuration arranged on the ASIC under test as a part of the circuit. The ASIC also includes a mode pin, a clock pin, and a reset pin that indicate a desired operating mode at any time.

ASICs include packages (eg, dual in-line packages or DIPs, leadless chip carriers or LCCs, pin grid arrays,
Tested before and after assembling into a quad flat pack. Before assembling into a package, the ASIC can be examined by a special probe card and a special machine that uses test vectors composed of sets of input, output, and bidirectional signals. By providing information to the probe machine using these test vectors, the ASIC can be electrically stimulated and verified. Each vector includes a set of input signals (stimuli) and a set of output signals.
After applying an input stimulus to each test vector, the probe machine verifies the set of output signals.

[0004] Once the pre-assembled ASICs have been verified to function, they are assembled and packaged parts, this time of the same type with sockets instead of a set of probes. Retest using the device. Verify the post-assembly behavior using the same set of test vectors.

The JTAG standard is intended for use in both ASICs and board level interconnections after the ASIC is mounted on a circuit board. AS that does not use pins because of the density of the paths currently in use and that can be accessed while mounted on these circuit boards
Because of the use of ICs, it is becoming increasingly difficult to test a circuit board and an ASIC mounted thereon after assembly. The JTAG1149.1 standard is a normal ASI
This configuration includes a special circuit incorporated in an individual ASIC using a boundary scan register disposed between the C function circuit and the ASIC pins. JTAG circuit on ASIC is AS AS by special test function of JTAG standard
Takes over the interface of the IC and drives the output signal of the ASIC. Thus, an output signal of the ASIC can be captured by a JTAG boundary scan of the ASIC to which the ASIC is interconnected on the circuit board. ASI
The JTAG circuit can be used as well to test the internal operation of the ASIC while C is mounted on a circuit board. It is connected to an external standard via a five signal serial interface: clock (TCK), test mode select (TMS), test data in (TDI), test data out (TDO), and selective test reset signal (TRST_). It is performed under the control of the JTAG controller.

First, instructions are scanned via a scan input and placed in an instruction shift register. At the end of the scan, the instruction in the instruction shift register is immediately decoded (extended via combinational logic so that all control signals are set to the appropriate state to perform the function specified by the instruction). ), The decoded instruction or instruction decode is stored in a set of parallel latches. These instruction decodes are used to control the operation of the test logic.

Although the 1149.1 JTAG standard requires only three instructions, there is an unlimited number of optional instructions, each with its own decoding. Each decode is a combination of control logic used to specify the operation of the test logic. To fully test the JTAG standard circuit, each instruction must be shifted into an instruction shift register and measurements must be taken to determine the state of each bit of the decoding. Because of the difficulty in verifying the state of these decoded bits based on the response of the external pin of the ASIC, up to thousands of test vectors may be required for each bit of each instruction. , The number of vectors is huge, the test time is long,
Extra tester costs are incurred. Since each instruction must be fully tested, and testing each instruction requires a large number of test vectors, only a few JTs
ASICs using the AG instruction require an unacceptable number of test vectors. (The term "test vector" is a description of the state of the pins of the ASIC at any given time.) By reducing the number of test vectors required to test the JTAG circuit on the ASIC, the tester's time and Obviously, the costs can be greatly reduced.

[0008]

The problems addressed by the present invention are:
This is a test of the JTAG circuit itself. JTAG circuit is each AS
Since it is included in the IC, it must be verified before it can be confirmed that the ASIC is usable. In the prior art, this test is performed by shifting in a test instruction and observing what the chip did in response, and after the instruction was sent, the decoding was checked by observing the operation of the device. Was done. This test is performed on the probe and repeated after the ASIC is assembled as described above. Testing a JTAG circuit is complex and time consuming, as the only way to verify correct operation of the ASIC is to monitor the response of the ASIC output pin to a given input stimulus. IEEE
The standard 1149.1a-1990 only requires three specific instructions, but this allows for an infinite number of instructions as defined by ASIC designers and system engineers, making system testing easier. become. These tests are performed by manipulating the input of the ASIC after scanning and entering a JTAG instruction while monitoring the output to verify that a correct response is being made. Since each instruction is decoded into a number of bits (these bits are used to control the JTAG circuit and are updated immediately after a new instruction is entered by scanning), and Since each bit must be verified to be decoded, tens of thousands of vectors may be required for a complete verification.
As a result, the test time is lengthened, and the test cost is accordingly increased.

[0009]

SUMMARY OF THE INVENTION A system according to the present invention for a JTAG standard test circuit that is already present in an ASIC and greatly reduces the number of test vectors required to verify instruction decoding logic. Test means. One object of the present invention is to save clock cycles during testing of a JTAG circuit. The actual decoding of the test instruction can be observed according to the invention. Since multiple instructions are decoded using the same logic gate, a reduced set of test vectors can be used to verify that the decoding circuit operates correctly in the JTAG circuit. The present invention verifies the correct operation of the JTAG circuit itself.

This is done by capturing the decode from the instruction immediately before this special test. Whereas tens of thousands of clock cycles are required to verify that the decoding is being performed according to prior art procedures, the decoding can be sent in a few clock cycles. Since most of the decoding logic used by an instruction is common to other instructions, the effects of the logic need only be verified by a single instruction using that part of the decoding. If the instruction decode test register is included, following that single verification, the verification of the decode for subsequent instructions simply shifts in the instruction whose decode must be tested and shifts the test instruction. By shifting out the value held in the instruction decode test register and comparing it to the expected result. This comparison value is included in the test vector and is performed by the tester. The instruction decode test register is automatically loaded with the decode of the previous JTAG instruction. In this way, the redundancy required for verifying the decryption of an ASIC that does not include an instruction decode test register is significantly reduced.

In an embodiment of the present invention, an additional test register called an instruction decode test register is provided.
Using this instruction decode test register, the previous JTAG
Capture instruction decoding. The decoding of the previous JTAG instruction can be shifted out and verified. When a JTAG instruction is shifted into the ASIC, the instruction decode test register captures the decode of the previous instruction before that decode is replaced by the decode of the new instruction. Since most of the decoded bits are used by several different instructions, the correct response of the ASIC to the decoded bits need only be shown once, and then simply scanning out the decode through the instruction decode test register and reading the decoded bit Can be verified for the remaining instructions. This saves time and money for the tester because it requires fewer vectors than previously required thousands.

More specifically, according to the present invention, means are provided for reducing the number of test vectors required to verify that each instruction is correctly decoded.
This means that prior to being replaced by decoding of the current instruction, the previous JT (from the latch described in the prior art)
A shift register into which decoding of the AG instruction is loaded is included. The data held in this shift register can then be shifted out using the standard JTAG protocol and checked to make sure it is correct. "
Given a circuit consisting of n "bit instructions and" m "instructions, using the prior art JTAG protocol and system, test" m "times" n "bits of instruction decoding. However, due to the addition of another shift register stage (instruction decode test register) added by the present invention to check by capturing and shifting out the decode, the decoded bits are available. After that, you can verify each subsequent instruction by simply checking the state of the bit, not the response of the device pins.

Assuming that the ATSC uses only 10 JTAG instructions and only 10 bits for instruction decoding,
2000 to verify the correct operation of all 10 instruction decode bits for that particular instruction in the TAG instruction
If one test vector is required, 20,000 test vectors are required using prior art systems and protocols. However, using the present invention, only a few instructions are required to verify the decryption using the response at the system pin of the ASIC, and the remaining instructions are verified using a simple JTAG scan. can do. Assuming that three instructions are each 2,000 test vectors and the remaining seven instructions are each 50 test vectors, the test is performed for 6,350 tests instead of 20,000 test vectors. You just need a vector. This number depends on the type of instructions involved, the number of instructions used, and the number of bits of instruction decoding used, but this example gives a rough idea of the inventive concept.

In another example, a given ASIC uses several different instructions to select a boundary scan register for a shift. Prior art required shifting the data stream through the selected register (which was 183 bits long) to indicate that the boundary scan register was selected for each instruction. In this ASIC, the correct path is selected using 4 bits out of 20 instruction decoding bits, and the instruction length is 8 bits.
Therefore, if a conventional JTAG circuit is used for decoding verification, about 200 test vectors are required only to verify that the four decoded bits are correct. Assuming there are six instructions that selected that particular shift register, using the prior art systems and protocols would require 1200 test vectors to test 20% of the decoded bits. In contrast, using the present invention, only about 500 test vectors are required. In addition, these 500 test vectors also perform another 80% verification of the bits of the last 5 instructions.

[0015]

FIG. 1 shows a very simple prior art integrated circuit (IC) for simplicity of the following description of an embodiment.
t) is shown. This circuit uses its clock (CL
K) A register that latches data from the D input at the rising edge of the input and sends the value to the Q output.

The test of FIG. 1 is performed in two stages. In the first stage, the IC is tested while it is still on the wafer. This is done using a tester. The tester is I
It includes a probe placed on the pad of C and applies a signal to the pad coupled to inputs D and CLK and measures the response at the pad coupled to output Q. After passing these tests, the wafer is split into individual dies (individual ICs before the package) and then placed in a package. These packages are Dual Inline Package (DIP), Leadless Chip Carrier (LCC),
It can be a single in-line package (SIP), a pin grid array (PGA), or one of many other packaging methods. However, each package includes a mechanism for holding the die so that signals can enter and exit the IC through the package and connecting the die to the outside of the package. In the following description, these connections on the IC will be referred to as "pins".

The measurement of the output value at a given time continues.
The application of a single set of input stimuli is called one test vector. The test vector contains the input values to be applied and the expected output values resulting from the set of inputs at some point. The tester must apply inputs, measure output values, and compare these output values to the values contained in the test vectors. If the expected output does not match the measured output, an error is flagged. In the following description, “H” and “H” are used for the high input value and the low input value.
L ”is used, and“ 1 ”(high) for the output value
And "0" (low) are used.

In the case of the IC of FIG. 1, the test consists of only a few vectors, but the table of FIG. 2 shows 12 such vectors. Test vector # 1 is D
Set input and CLK input low. As a result, the Q output is indeterminate. This is because it is not possible to predict the value of the Q output without already clocking it into the IC. Test vector # 2 includes the low level of input D and the high level of the CLK input, and the Q output is low. This is because it is a value that is output when it is operating correctly. Test vector # 3 has input D
, And the low level of the CLK input, and the Q output is low. Test vector # 4 has input D
And the high level of the CLK input is included, and the Q output is high. For a complete test, check the output to see if the output transitions based on all combinations of current input and output values. The result is 10 to 12 vectors for a simple functional test. Twelve such vectors for testing the circuit of FIG. 1 are shown in prior art FIG. Because a typical IC includes much more complex circuitry than the simple circuit of FIG. 1, much more test vectors are required than shown here. In a typical IC,
The internal circuits (eg, registers,
Due to the number of latches, NAND gates, etc.), test vectors on the order of one million may easily be required.

IEEE Standard 1149.1a-1990
(JTAG) inserts test logic into an IC and uses the IC itself in a system that also includes a JTAG circuit as shown in FIG. You specify how you can test the connection. The JTAG circuit itself includes a JTAG test access port (TAP), a boundary scan register including a boundary scan cell for each input and output except for the JTAG interface pins TCK, TMS, TDI, and TDO, and a bypass register which is a shift register unique to JTAG. , An instruction shift register, instruction decoding logic, and an instruction holding register. In addition, additional circuitry can be used in this circuit, such as the ID code register shown in FIG.

The JTAG circuit of FIG. 3 is used to test the external interface to the IC, test internal circuits, and set the area of the IC for special tests. JTAG operation uses two types of scans called instruction scans and data scans.
Instruction scan selects the instruction shift register and sets the TDI
It consists of a JTAG TAP controller that shifts data into its shift register via pins. At the end of the shift, the data shifted into the instruction shift register is decoded by the instruction decoding logic (expanded into a set of control bits, hereinafter referred to as instruction decoding), and then latched into the instruction decoding holding register. Held there until updated at the end of the instruction shift. Using these instruction decodes, data scan, operation of the boundary scan register ("test" or "normal" mode), and I
A selection is made of which registers to select for any number of IC-specific tasks defined by the C designer. The exact use of these bits is well known and not relevant to the description of the present invention and will not be further described here.

In the data scan, the register specified by the instruction decode bit captures (1) data and (2)
After shifting out the data (while shifting in the new data), (3) it consists of a three-step process of updating the new data to the given position at the end of the shift. The details of this operation are well known and are not important to the present invention, and will not be described.

Since the JTAG circuit is to be used to test system level interconnects,
The TAG circuit is used in a "test" mode or a "normal" mode. In "normal" mode, the value from the input pin is sent directly to the core logic (the part of the IC that is different from the I / O buffer that exists without JTAG) through the input scan cell, and the value from the core logic is output to the output pin through the output scan cell. Sent to This mode allows the core logic of the IC to operate as if the JTAG were not present in the IC. When the IC is operating in "normal" mode,
Whenever indicated by an external JTAG controller (not part of the IC, but the circuitry used to control the JTAG interface pins TMS and TDI) to use the boundary scan registers,
A "early shot" of the value present on the C pin is taken.

When the IC is in the JTAG "test" mode, data applied to the core logic input is supplied from a holding latch included in the boundary scan input cell, and
The boundary scan cell is controlled such that the data supplied to the output buffer is supplied from a latch included in the boundary scan output cell. With this function, the boundary scan register isolates the core logic and
It can be prevented from being affected by an external I / O different from the AG controller.

The "test" mode is used while the IC is mounted on the system for interconnect testing (and can also be used to test the core logic of the IC). This is done by loading a value into the output cell of the boundary scan register for use in driving the output pin of the IC using a series of data scans, and either connected to that output cell. By capturing their values at the input cells of the boundary scan register of the IC. This captured data is shifted out and compared to expected data values to determine if system level IC interconnection is optional.

Since the JTAG circuit is included in the IC, the IC cannot be declared fully usable until the JTAG circuit has been verified to be fully usable. One of the more complex areas of this verification is the area of JTAG instruction decoding. Decoding is a mechanism through which the JTAG circuit controls the selection of the data scan path, the selection of test mode or normal mode, the initiation of special test features, control of IC specific test operations, and the like. Since these instruction decodes are not accessible at the pins of the IC, they cannot be tested simply or quickly. However, the IC cannot be declared functionally sound without testing each instruction decode bit of each instruction to verify correct operation.

The subset of verifications required without the present invention is as follows. a) the fact that multiple instructions select the same scan path, and the boundary scan path (s)
And the scan path, such as the internal scan path (s), for each instruction, regardless of the fact that it is a long chain of shift registers that requires multiple test vectors to complete a single scan. B) the instruction is in the correct mode ("test") by applying a series of vectors to the input and measuring the output to determine if the input value has propagated through the IC.
Test to ensure that it was in either "normal" mode or "normal"mode; c) any special instructions such as instruction decoding to initiate an internal test function for each such instruction. Determining whether each instruction initiates its corresponding internal test function by testing the instruction decode; d) Verification of special instruction decodes (such as instruction decode bits that turn off pull-ups on IC pins). Doing so ensures that such special instruction decoding is correct not only for the instructions that will activate them, but also for those instructions that will not activate them.

Note again that instruction decoding is
Since the value specified for each G instruction is provided,
Some method of verification per instruction decode bit must be performed for each TAG instruction. This has a mixed effect. This is because, for each instruction, for example, a simple 1000 vector test must be performed to verify a single instruction decoded bit. This results in tens of thousands of test vectors per bit for instruction decoding in the IC.

FIG. 4 shows the circuit of FIG. 3 with the features (instruction decoding test register) of the present invention added. An enlarged block diagram of the instruction decode test register is shown in FIG.

When the IC includes the circuit according to the invention,
The number of test vectors is greatly reduced. This reduces the vectors required to verify the instruction decode bits for a single instruction and, according to the invention, reduces all instruction decode bits for a given instruction for inspection in a single data scan. It depends on the combination with shifting out.

Since the value of the instruction decode can be accessed via the JTAG data scan path, for example, the instruction A is shifted into the instruction shift register of the IC via the scan input (TDI), and the instruction A is used as a path for the JTAG data scan. IN for selecting decoding test register
After the DEC instruction is shifted into the instruction shift register of the IC via the scan input, a data scan is performed to shift the entire instruction decode set for instruction A via the scan output (TDO). Using this technique and the instruction decoding test register, the conventional verification subset required without the present invention is reduced by the present invention as follows. a) Each data scan path is selected by specific instruction decoding. This requires data scanning per path, not data scanning per instruction, per path. b) Operate for both "test" mode and "normal" mode by verifying "test" / "normal" mode instruction decoding. This shifts all instructions one at a time into the instruction shift register via the scan input, correspondingly applies a series of vectors to the input, measures the output, and sets the input value to IC Instead of seeing if it has propagated, it is necessary to apply two instructions and a corresponding series of vectors to the input and measure the output to see if the input value has propagated through the IC. c) By testing any special instruction decode, such as a decode that initiates an internal test function, against only one instruction, one special instruction decode that does not initiate its internal test function and internal test function Determine if the instruction has started. d) Special instruction decoding (such as an instruction decoding bit to turn off the pull-up of an IC pin) is verified for active and inactive instructions as in c) above. e) The rest of the test is a sequence of simply entering the instruction whose decoding must be verified, entering the INDEC instruction and scanning out the corresponding decoding for verification.

The operation will be described. 1149.1 When the device is in test mode, it uses the TCLK input to clock data into the instruction shift register and
According to the standard, a test instruction to be executed by the ASIC's JTAG circuit is first serially transmitted to the ASIC on the TDI input pin. After receiving the instruction and putting it in the instruction shift register,
The instructions are sequentially decoded by the instruction decoding circuit to become expanded test instructions. The instruction decoding circuit typically comprises conventional combinatorial logic for decoding, or other decoding circuits, as is well known to those skilled in the art. Next, the decoded instruction is captured in the instruction holding register. The output of the instruction holding register is the ASI to perform the desired test.
Drive various circuits on C. At the same time, the data in the instruction decode holding register is captured by the instruction decode test register.

The instruction decoding test register is a parallel load serial shift register. After the instruction decode test register is loaded with the decoded instruction from the instruction holding register,
This instruction is shifted out via the TDO serial test data output pin in response to a control signal sent on the TDI serial test data input pin. The contents of the instruction decode test register are captured by another device and compared to the expected decode for a particular test instruction. In this way, the decoding of the JTAG instruction can be verified as correct or identified as incorrect. The use of the invention described herein allows for quick verification of the correct operation of the instruction register, shift register, instruction decoding circuit, and instruction holding register. Quick verification of this correct operation was not possible with prior art JTAG circuits.

A possible alternative configuration includes not only an instruction decode test register to receive the contents of the instruction holding register, but also an on-board comparator and an additional test register to receive the expected decoded data word. It is a thing. In this configuration, the above steps are performed to decode the instruction after the expected decoded data word is shifted into the comparator logic using the TDI input. In this case, instead of sending out the contents of the instruction decode test register serially for off-chip comparison with the expected decode as described above, the comparator on the board compares the contents of the instruction decode register with the expected decode. Compare and output an indicator indicating a match or mismatch based on the result of the comparison.

Although the present invention has been described in terms of particular embodiments, many modifications and variations will readily occur to those skilled in the art. Therefore, the appended claims should be read as broadly as possible in light of the prior art to encompass all such changes and modifications.

With respect to the above description, the following items are further disclosed. (1) A system for testing a semiconductor device, comprising: a semiconductor chip having a functional circuit for performing a function in a predetermined manner and a test circuit for testing a correct operation of the functional circuit. And the test circuit
(I) a decoding circuit for decoding instruction data;
i) an instruction holding register for storing the decoded instruction, and (iii) receiving the output of the instruction holding register and outputting decoded instruction data for comparison with expected instruction decoding. An instruction decoding test register;
And a semiconductor device test system.

(2) The semiconductor device test system according to (1), wherein the instruction decoding test register includes a comparing circuit for comparing the contents of the instruction decoding test register with expected decoded instruction data. Semiconductor device test system. (3) The semiconductor device test system according to (1), wherein the test circuit is an IEEE standard 1149.1-19.
90, a semiconductor device test system. (4) The semiconductor device test system according to (2), wherein the test circuit is an IEEE standard 1149.1-19.
90, a semiconductor device test system.

(5) The semiconductor device test system according to item 1, wherein the device is an integrated circuit. (6) The semiconductor device test system according to (2), wherein the device is an integrated circuit. (7) The semiconductor device test system according to item 3, wherein the device is an integrated circuit. (8) The semiconductor device test system according to (4), wherein the device is an integrated circuit.

(9) The semiconductor device test system according to (1), wherein the command data is applied to an input of the functional circuit in response to the device being in a test mode, and a test of the chip is performed. A circuit for capturing and observing an internal operation of the chip in response to a circuit. (10) The semiconductor device test system according to (2), wherein the circuit is configured to apply the command data to an input of the functional circuit in response to the device being in a test mode, and is responsive to a test circuit of the chip. And a circuit for capturing and observing the internal operation of the chip. (11) The semiconductor device test system according to (3), wherein the circuit applies the command data to an input of the functional circuit in response to the device being in a test mode, and responds to a test circuit of the chip. And a circuit for capturing and observing the internal operation of the chip. (12) The semiconductor device test system according to (4), wherein the circuit applies the command data to an input of the functional circuit in response to the device being in a test mode, and responds to a test circuit of the chip. And a circuit for capturing and observing the internal operation of the chip.

(13) The semiconductor device test system according to (1), further comprising a circuit for comparing the output of the instruction decoding test register with the expected output, outside the chip. (14) The semiconductor device test system according to (2), further comprising a circuit for comparing an output of the instruction decoding test register with the expected output, outside the chip. (15) The semiconductor device test system according to (12), further including a circuit for comparing the output of the instruction decoding test register with the expected output, outside the chip.

(16) An integrated circuit having a test circuit, (a) an application logic circuit for giving a desired function to the integrated circuit, and (b) an operation logic circuit for verifying the operation of the application logic circuit (I) a test data input for receiving serial test data and instructions; (ii) a test data output for transmitting serial test data and instructions; iii) an instruction shift register coupled to the test data input for receiving a test instruction; and (iv) an instruction shift register coupled to decode a plurality of predetermined test instructions received at the instruction shift register. And (v) receiving an output of the instruction decoding circuit and outputting a test control signal representing a specific test instruction. And instruction decode holding register for, (vi) integrated circuit anda instruction decode test register for receiving the output of the instruction decode holding register.

(17) The integrated circuit according to item 16, wherein the test circuit further comprises: (vii) a comparison circuit for comparing the contents of the instruction decoding test register with an expected decoded test instruction. Integrated circuit. 18. The integrated circuit of claim 16, wherein the instruction decode is for transmitting the contents of the instruction decode test register to an external comparator for comparing a decoded test instruction with the expected decode. An integrated circuit, wherein a test register is coupled to said test data output.

(19) A method for testing a semiconductor device, comprising: (a) a function circuit for performing a function in a predetermined manner; and a test circuit for testing a correct operation of the function circuit. A semiconductor chip, the test circuit comprising:
A decoding circuit for decoding instruction data; (ii) an instruction holding register for storing the decoded instruction;
(Iii) an instruction decoding test register for receiving the output of the instruction holding register; (b) the instruction data is decoded by the decoding circuit; and (c) the instruction data is decoded by the instruction holding register. (D) capturing the decoded instruction data in the instruction decoding test register; and (e) outputting the contents of the instruction decoding test register for comparison.

(20) The method of testing a semiconductor device according to item 19, wherein the test circuit is an IEEE standard 114.
A semiconductor device test method conforming to 9.1-1990. (21) The semiconductor device testing method according to item 19, wherein the device is an integrated circuit. (22) The semiconductor device test method according to item 20, wherein the device is an integrated circuit.

(23) The method of testing a semiconductor device according to claim 19, further comprising: applying the command data to an input of the functional circuit; and capturing an internal operation of the chip in response to an output of the chip. A semiconductor device test system including a step of observing. (24) The semiconductor device test method according to claim 20, further comprising: applying the command data to an input of the functional circuit, and capturing and observing an internal operation of the chip in response to an output of the chip. And a semiconductor device test system. (25) The semiconductor device test method according to claim 21, further comprising: applying the command data to an input of the functional circuit, and capturing and observing an internal operation of the chip in response to an output of the chip. And a semiconductor device test system.

(26) A system for testing a semiconductor device, comprising: a semiconductor chip having a functional circuit for performing a function in a predetermined manner and a test circuit for testing a correct operation of the functional circuit. Provided. The test circuit includes a decoding circuit for decoding instruction data (instruction decoding)
And an instruction holding register (instruction holding register) for storing the decoded instruction and an output of the instruction holding register,
An instruction decoding test register (instruction decoding test register) for outputting decoded instruction data for comparison with expected instruction decoding.

[Brief description of the drawings]

FIG. 1 is a block diagram of a simple prior art integrated circuit for use in describing a procedure in accordance with the present invention.

FIG. 2 is a table showing test vectors of a simple circuit according to the prior art.

FIG. 3 shows a simple integrated circuit with JTAG according to the prior art.

FIG. 4 illustrates a simple integrated circuit with features according to JTAG and the present invention.

FIG. 5 is a block diagram of an instruction decoding test register block of FIG. 4;

[Explanation of symbols]

 TDI serial test data input pin TDO serial test data output pin

Claims (2)

[Claims] 1. A system for testing a semiconductor device, comprising: a functional circuit for performing a function in a predetermined manner; and a test circuit for testing a correct operation of the functional circuit. Wherein the test circuit comprises: (i) a decoding circuit for decoding instruction data; (ii) an instruction holding register for storing the decoded instruction; and (iii) the instruction holding. An instruction decoding test register for receiving the output of the register and outputting decoded instruction data for comparison with expected instruction decoding. 2. A method for testing a semiconductor device, comprising: (a) a functional circuit for performing a function in a predetermined manner; and a test circuit for testing correct operation of the functional circuit. A semiconductor chip comprising: (i) a decoding circuit for decoding instruction data; (ii) an instruction holding register for storing the decoded instruction; and (iii) the instruction holding register for storing the decoded instruction. An instruction decoding test register for receiving the output of the instruction holding register; and (b) decoding the instruction data with the decoding circuit; and (c) storing the decoded instruction in the instruction holding register. (D) capturing the decoded instruction data in the instruction decoding test register; and (e) outputting the contents of the instruction decoding test register for comparison. It is tested method.