JP2002373086A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems of increase in the number of clocks, increase in external terminals, etc., needed for TAP controller control and data setting when a processor is debugged. SOLUTION: In a semiconductor integrated circuit including a plurality of processors, increase in external terminals and the number of clocks is prevented and a fast on-chip debugging can be realized by diverting a TRST terminal of a JTAG test access port as a select terminal of a selector circuit, inserting an inverter between the TRST terminal and one processor to be a selector function, using a first control circuit including a counter and a decoder instead of the selector circuit and using a TMS terminal instead of the TRST terminal to be a second control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having internal circuits such as a plurality of processors and logic blocks, and more particularly to a debug circuit for supporting software debugging.

[0002]

2. Description of the Related Art For debugging a processor built in a semiconductor integrated circuit, a test access port (TCK, TMS, TDI, TDO, TRST) of JTAG and other terminals are usually used to debug from outside the semiconductor integrated circuit. ,
JTAG circuit inside or outside the processor (IEEE
A method is used in which a debug support circuit such as a TAP controller compliant with E1149.1 is controlled.

Conventional example 1. FIG. 5 is a block diagram showing a conventional semiconductor integrated circuit incorporating a processor. In the figure, 1-1 and 1-2 are processors, and 2-1 and 2-2 are J.
It is a TAG circuit. Here, processors 1-1 and 1
-2 have JTAG circuits 2-1 and 2-2 each including a plurality of JTAG scan registers (not shown), and these JTAG circuits have JTAG test access ports (TCK,
Signals can be exchanged with the outside via TMS, TDI, TDO, TRST).

In a semiconductor integrated circuit incorporating such a processor, the JTAG circuits 2-1 and 2-2 are connected in series to the TDI terminal and the TDO terminal, and
Generally, the processors 1-1 and 1-2 are debugged in a configuration in which the G scan registers are connected in series.

Next, the operation will be described. Processor 1
A predetermined clock is input from the TCK terminal corresponding to the number of JTAG scan registers chained by serial connection of -1 and 1-2, the JTAG circuits 2-1 and 2-2 become active, and a test pattern is input from the TDI terminal. And
Debugging of the two processors 1-1 and 1-2 is performed at a time. Thereafter, a predetermined clock is similarly input from the TCK terminal, and a debug result is output to the outside from the TDO terminal. As described above, connecting the JTAG scan registers of a plurality of processors in series is a conventional method of the conventional JTAG on-chip debugging.

Conventional example 2. Alternatively, there is a method of debugging only the selected processor by inserting a selector between the JTAG test terminal (TAP) and the processor. FIG. 6 is a block diagram of a semiconductor integrated circuit incorporating such a conventional processor, in which 1-1 and 1-2 are processors, 2-1 and 2-2.
Is a JTAG circuit, and 60 is a selector circuit. Conventional example 1
The difference is that an external select terminal (SEL) is provided and a selector circuit 60 controlled by this select terminal is inserted.

Next, the operation will be described. In accordance with the SEL signal input from the external select terminal, the selector circuit 60 determines whether the J included in one of the processors 1-1 and 1-2 includes
The TAG circuit is controlled. For example, while the JTAG circuit 2-1 of one processor 1-1 is being controlled, the JTAG circuit 2-2 is held on the other processor 1-2 by holding a test logic reset state. Is controlled not to operate. Thereby, the processor 1 to be debugged
-1 and 1-2 are selected to enable debugging.

[0008]

Since the conventional semiconductor integrated circuit is configured as described above, in the conventional example 1, as shown in FIG. 5, the JTAG of the processors 1-1 and 1-2 is used.
Since the scan registers are connected in series via the JTAG circuits 2-1 and 2-2, the processors 1-1 and 1--1
2, the number of shift clocks required to set an instruction in the instruction register of each TAP controller and to set data in the data register increases, so that the debugger control device outside the semiconductor integrated circuit controls the processor, There has been a problem that the time required for downloading data to the internal memory and the external memory of the processor increases.

Further, when the types of the plurality of processors are different, there is a problem that it is difficult to simultaneously control the TAP controllers of the plurality of processors by the external debugger program.

Further, as shown in FIG. 6, in the conventional example 2, there is a problem that the provision of the external terminals increases the manufacturing cost of the semiconductor integrated circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and makes it easy to perform JTAG on-chip debugging of an LSI on which an internal circuit such as a plurality of processors and logic blocks is mounted without increasing external terminals. It is another object of the present invention to provide a semiconductor integrated circuit capable of realizing control of an internal circuit and reduction of time for downloading data to a memory.

[0012]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention has first and second circuits each having a JTAG circuit.
And a JTAG test access port connected to the selector circuit and forming an external terminal. The first and second circuits use the debug support circuit.
As a select terminal of a selector circuit for selecting an internal circuit to be debugged at the time of on-chip debugging of the internal circuit, the TRST of the JTAG test access port is used.
A terminal is used.

A semiconductor integrated circuit according to the present invention includes a first and a second internal circuit each having a JTAG circuit, a JTAG test access port connected thereto and forming an external terminal, and a TRST terminal and a JTAG test access port. An inverter circuit provided between one of the first and second internal circuits, and a debug support circuit comprising a JTAG circuit and an inverter for debugging one of the first and second internal circuits. Is to execute.

A semiconductor integrated circuit according to the present invention includes a plurality of internal circuits each having a JTAG circuit, a JTAG test access port connected to the plurality of internal circuits to form an external terminal,
A first control circuit connected to the TRST terminal and the TCK terminal to form a functional block including a counter. The debug support circuit configured by the JTAG circuit and the first control circuit has a TRST terminal and a TCK terminal. The TRST signal and the TCK signal are input via the CPU, respectively, and any one of the plurality of internal circuits is debugged by a functional block.

A semiconductor integrated circuit according to the present invention comprises: a plurality of internal circuits each having a JTAG circuit; a JTAG test access port connected to the internal circuit to form an external terminal;
A second control circuit which is connected to the TMS terminal and the TCK terminal of the JTAG test access port and constitutes a functional block including a counter; and a JTAG circuit and a second control circuit.
The debug support circuit constituted by the control circuit of TM
TMS signal and TC via S terminal and TCK terminal
A K signal is input, and any one of a plurality of internal circuits is debugged by a functional block.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
Reference numerals 1 and 1-2 denote processors (internal circuits).
Reference numeral 2-2 denotes a JTAG circuit, and reference numeral 10 denotes a selector circuit that uses a JTAG test access port TRST terminal as a control terminal. Here, the JTAG circuits 2-1 and 2-2 and the selector circuit 10 constitute a debug support circuit.

Next, the operation will be described. In FIG. 1, the TR applied from the outside by the selector circuit 10 is shown.
When the ST signal is at the HIGH level, the TRST signal sig1 on the processor 1-1 side becomes HIGH level, and the TRST signal sig2 on the processor 1-2 side becomes LOW level. At this time, the processor 1-2 is in the test logic reset state.

When the externally applied TRST signal is at the LOW level, the selector circuit 10 sets the TRST signal sig1 of the processor 1-1 to the LOW level and sets the TRST signal sig2 of the processor 1-2 to the HI level.
GH level. At this time, the processor 1-1 is in a test logic reset state.

In debugging the processor 1-1, first, the TRST signal applied from the outside is set to the LOW level, and the JTAG circuit 2-1 of the processor 1-1 is reset (test logic reset). Next, the external TRST signal is set to HI
Set to GH level, JTAG circuit 2 of processor 1-1
-1 is released from the test logic reset state, and JTAG
Test access ports (TCK, TMS, TDI, TD
O) is used to debug the processor 1-1. During debugging of the processor 1-1, the processor 1-
2 does not operate in the test logic reset state.

On the other hand, when debugging the processor 1-2, first, the external TRST signal is set to the LOW level,
-2 JTAG circuit 2-2 is reset (test logic reset). Next, the external TRST signal is set to the HIGH level, the JTAG circuit 2-2 of the processor 1-2 is released from the test logic reset state, and the processor 1-JTAG test access port (TCK, TMS, TDI, TDO) is used. Perform debugging of 1. During the debugging of the processor 1-2, the JT of the processor 1-1 is executed.
The AG circuit 2-1 does not operate in the test logic reset state.

As described above, by using the TRST terminal of the JTAG test access port as a select terminal, a processor to be debugged can be selected from the processors 1-1 and 1-2 without adding an external terminal, thereby achieving a T
High-speed debugging of the processor can be easily performed without increasing the number of clocks required for controlling the AP controller and setting data.

As described above, according to the first embodiment, two processors, that is, processors 1-1 and 1-
In the on-chip debugging using the debug support circuit of the semiconductor integrated circuit incorporating the semiconductor device 2, it is possible to debug one of the selected processors without adding an external terminal, thereby increasing the number of clocks. Thus, an effect is obtained that high-speed on-chip debugging can be realized.

Embodiment 2 FIG. FIG. 2 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention, where 1-1 and 1-2 are processors, 2-1 and 2-2.
Is a JTAG circuit, and 20 is an inverter. Where J
The TAG circuits 2-1 and 2-2 and the inverter 20 form a debug support circuit.

Next, the operation will be described. In FIG. 2, TRS applied from outside by inverter 20
When the T signal is at the HIGH level, the TRST signal sig1 on the processor 1-1 side becomes HIGH level, and the TRST signal sig2 on the processor 1-2 side becomes LOW level. At this time, the processor 1-2 is in the test logic reset state.

When the externally applied TRST signal is at a low level, the inverter 20 causes the TRST signal sig1 on the processor 1-1 side to be at a low level.
The TRST signal sig2 of the processor 1-2 is HIGH.
Become a level. At this time, the processor 1-1 is in a test logic reset state.

To debug the processor 1-1, first, the external TRST signal is set to the LOW level, and the JTAG circuit 2-1 of the processor 1-1 is reset (test logic reset). Next, the external TRST signal is set to a high level, the JTAG circuit 2-1 of the processor 1-1 is released from the test logic reset state, and the processor 1-JTAG test access port (TCK, TMS, TDI, TDO) is used. Perform debugging of 1. During debugging of the processor 1-1, the JTAG circuit 2-2 of the processor 1-2 does not operate in the test logic reset state.

On the other hand, when debugging the processor 1-2, first, the external TRST signal (the output signal of the inverter 20) is set to L level.
OW level, JTAG circuit 2- of processor 1-2
2 (test logic reset). next,
The external TRST signal (output signal of the inverter 20) is set to HI
GH level, JTAG circuit 2 of processor 1-2
-2 is released from the test logic reset state and JTA
G test access port (TCK, TMS, TDI, T
DO) is used to debug the processor 1-2. During debugging of the processor 1-2, the processor 1-
The JTAG circuit 2-1 does not operate in the test logic reset state.

As described above, according to the second embodiment, by inserting the inverter 20 between the TRST terminal of the JTAG test access port and the processors 1-1 and 1-2, the second embodiment differs from the first embodiment. Similarly, it is possible to achieve an effect that high-speed on-chip debugging can be realized by preventing an increase in the number of clocks without adding an external terminal.

Embodiment 3 FIG. 3 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. In the figure, 1-1 to 1-N represent processors (N is a natural number), and 2-1 to 2-N represent JTAG circuits. , 30 is a first control circuit, 300 is a counter, 301 is a decoder with reset, 302 and 31-1 to 31-N (N is a natural number) are AND gates, and 320 is an OR gate. The semiconductor integrated circuit according to the third embodiment includes a processor 1-1 to a processor 1-N, a JTAG test access port, and a TTAG signal inserted between the JTAG test access port and the processors 1-1 to 1-N. The first control circuit 30 receives a signal as an input. Further, the first control circuit 30 includes a counter 300, a decoder 301, an AND gate 302, and 31-1 to 31-31.
N, OR gate 320.

Next, the operation will be described. In FIG. 3, the counter 300 counts the number of cycles of the TCK (clock) signal while the external TRST signal is at the LOW level. Decoder 30 which receives the output of counter 300
When the TRST signal transits to a high level, the signal 1 outputs a high level only to a signal having a bit number corresponding to the output of the counter 300, and outputs a low level to other signals. At this time, the JTAG test logic reset state is released only for the processor 1-n (1 ≦ n ≦ N, where N is a natural number) to which the HIGH level TRST signal is input. On the other hand, the other processors hold the test logic reset state.

Then, when debugging the processor 1-n, first, the external TRST signal is set to the LOW level. At this time, the output signals of the decoder 301 (sig1 to sig
N) are all LOW levels and all processors 1-
1 to 1-N are test logic reset states. While the TRST signal is at the LOW level, the TCK signal is applied for n cycles. The counter 300 counts the number of cycles of the applied TCK signal and outputs n to the decoder 301.

Next, the external TRST signal is set to HIGH level. When the TRST signal becomes HIGH, the decoder 301 outputs only HIGH to the signal sign of the n-th bit.
Level and LOW level for other signals.

As a result, the TRS is provided only to the processor 1-n.
The HIGH level of the T terminal is propagated, and the test logic reset state is released. Thereby, the processor 1-
Only n can be controlled from the test access port and can be debugged. On the other hand, the TRST signal input to the other processors keeps the test logic reset state while keeping the LOW level.

As described above, by inserting the first control circuit 30 having the counter 300 and the decoder 301 in place of the selector circuit 10 described in the first embodiment, two or more processors 1-1 can be provided. It is easy to arbitrarily select one processor to be debugged from .about.1-N.

As described above, according to the third embodiment, a plurality of processors, that is, processors 1-1 to 1-1-1.
One processor from N, for example, n-th processor 1
−n can be selected, and therefore, as in the first embodiment, the effect is obtained that the number of clocks is prevented from increasing and the high-speed on-chip debugging can be realized without increasing the number of external terminals.

Embodiment 4 FIG. 4 is a block diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention. In the figure, 1-1 to 1-N represent processors (N is a natural number), and 2-1 to 2-N represent JTAG circuits. , 40 are a second control circuit, 400 is a control circuit, 401 is a counter, 40
2 is a decoder, 41-1 to 41-N and 430 are OR gates, respectively, and 42-1 to 42-N are ANDs, respectively.
Gates 440 are AND gates, and 441 to 445 are registers. Here, the control circuit 400 is connected to the AND gate 4
The second control circuit 40 includes a control circuit 400, a counter 401, a decoder 402, and OR gates 41-1 to 440. The register 441 receives the TMS signal as a shift-in input and the TCK signal as a clock input. 4
1-N, 430 and AND gates 42-1 to 42-N
Consists of

Next, the operation will be described. In FIG. 4, when a HIGH level signal is applied for 5 cycles or more from the external TMS signal, the control circuit 400
While the signal is at the HIGH level, the TCK signal (clock) is transmitted to the counter 401. The counter 401 counts the number of cycles of the input TCK signal and inputs the output to the decoder 402. The decoder 402 has a counter 4
HIGH only for the signal of the bit number corresponding to the output of 01
Level, and other signals output LOW level.

At this time, among the OR gates (41-1 to 41-N) for inputting the output signal of the decoder 402, the HIG
Only the OR gate to which the H-level signal is input is activated. The external TMS signal is propagated only to the processor connected to the activated OR gate. In other processors, the TMS signal is held at the HIGH level. As a result, the processor through which the external TMS signal propagates is JTAG
The test logic reset state is released. Other processors remain in the test logic reset state.

The n-th processor 1-n (1 ≦ n ≦ N,
When n is a natural number, the external TMS signal is set to H
When the TCK signal (clock) is set to 5
Apply cycles. At this time, all the processors 1-1 to 1-1
1-N are in a test logic reset state.

Next, while the TMS signal is held at the HIGH level, the clock TCK signal is applied for n cycles. The counter 401 counts the number of cycles of the applied TCK signal and sets the output to the decoder 402 to n.

The decoder 402 outputs the signal si of the n-th bit.
Only gn outputs a HIGH level, and other signals output a LOW level. As a result, only the OR gate 41-n is activated, and the TMS signal propagates to the processor 1-n. At the same time as the transition of the TMS signal from the HIGH level to the LOW level (falling edge), the processor 1-n is released from the test logic reset state and can be controlled from the test access port, that is, can be debugged. On the other hand, T
The MS signal keeps the test logic reset state while keeping the HIGH level.

As described above, the TRST of the third embodiment is used.
By using a TMS terminal instead of a terminal, it becomes possible to select one processor 1-n to be debugged from two or more processors 1-1 to 1-N.

As described above, according to the fourth embodiment, one processor 1-n can be selected from a plurality of processors 1-1 to 1-N. An effect is obtained that high-speed on-chip debugging can be easily realized by preventing an increase in the number of clocks without increasing the number of external terminals.

In the first to fourth embodiments,
Although the description has been made by taking a plurality of processors as an example, the same applies to a case where a logic block is used instead, and the same effect can be realized even if a plurality of processors are mixed with a logic block.

[0045]

As described above, according to the present invention, the selector circuit which is connected to the first and second internal circuits each having the JTAG circuit and constitutes the debug support circuit together with the JTAG circuit, and J to connect and form an external terminal
A TAG test access port, and when debugging the first and second internal circuits using the debug support circuit,
Since the TRST terminal of the JTAG test access port is used as the select terminal of the selector circuit for selecting the internal circuit to be debugged, the processor to be debugged can be selected without adding an external terminal. Thus, there is an effect that high-speed debugging of an internal circuit can be easily realized without increasing the number of clocks required for controlling the TAP controller and setting data.

According to the present invention, the first and second internal circuits each having a JTAG circuit, the JTAG test access port connected thereto and forming an external terminal, the TRST terminal and the first and second internal circuits are provided. And an inverter circuit provided between one of the internal circuits.
Since the debug support circuit constituted by the G circuit and the inverter is configured to execute debugging of one of the first and second internal circuits, similarly, the processor to be debugged without adding external terminals Can be selected, and there is an effect that high-speed debugging of the internal circuit can be easily realized without increasing the number of clocks required for controlling the TAP controller and setting data.

According to the present invention, a plurality of internal circuits each having a JTAG circuit, a JTAG test access port connected to the internal circuit to form an external terminal, and a function including a counter connected to the TRST terminal and the TCK terminal. A debug control circuit comprising a JTAG circuit and a first control circuit, which inputs a TRST signal and a TCK signal via a TRST terminal and a TCK terminal, respectively. Is configured to execute debugging of any one of a plurality of internal circuits, and similarly, a processor to be debugged can be selected without adding an external terminal,
There is an effect that high-speed debugging of an internal circuit can be easily realized without increasing the number of clocks required for controlling the TAP controller and setting data.

According to the present invention, a plurality of internal circuits each having a JTAG circuit, a JTAG test access port connected thereto to form an external terminal, and a function including a counter connected to the TMS terminal and the TCK terminal. A debug control circuit comprising a JTAG circuit and a second control circuit, for inputting a TMS signal and a TCK signal via a TMS terminal and a TCK terminal, respectively; Is configured to execute debugging of any one of a plurality of internal circuits, and similarly, a processor to be debugged can be selected without adding an external terminal.
There is an effect that high-speed debugging of an internal circuit can be easily realized without increasing the number of clocks required for controlling the P controller and setting data.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a semiconductor integrated circuit according to Conventional Example 1.

FIG. 6 is a block diagram of a semiconductor integrated circuit according to Conventional Example 2.

[Explanation of symbols]

1-1 to 1-N processor (internal circuit), 2-1 to 2
−N JTAG circuit, 10, 60 selector circuit, 20
Inverter, 30 first control circuit, 40 second control circuit, 31-1 to 31-N, 42-1 to 42-N, 30
2,440 AND gate, 41-1 to 41-N, 32
0,430 OR gate, 300,401 counter,
301, 402 decoder, 320, 400 control circuit, 441 to 445 register.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 11/28 G06F 15/78 510K 15/78 510 G01R 31/28 G H01L 21/822 H01L 27/04 T 27/04 F term (reference) 2G132 AA14 AC00 AG01 AG08 AG12 AK07 AL09 5B042 GA11 GA32 GC01 HH01 5B048 AA20 DD08 DD10 FF06 5B062 AA02 JJ08 5F038 DF04 DT02 DT06 DT15 EZ20

Claims (4)

[Claims] 1. A first and a second internal circuit each including a JTAG circuit, a selector circuit connected to the first and the second internal circuit to constitute a debug support circuit together with the JTAG circuit, and a selector circuit A semiconductor integrated circuit having a JTAG test access port connected to a circuit and forming an external terminal, wherein when debugging the first and second internal circuits using the debug support circuit, the internal circuit to be debugged is A semiconductor integrated circuit, wherein a TRST terminal of the JTAG test access port is used as a select terminal of the selector circuit for selecting. 2. A first and a second internal circuit each including a JTAG circuit; a JTAG test access port connected to the first and the second internal circuit to form an external terminal; and a JTAG test access port. A semiconductor integrated circuit having an inverter circuit provided between the TRST terminal of the first and second internal circuits, and a debug support circuit comprising the JTAG circuit and an inverter. A semiconductor integrated circuit for executing debugging of one of the first and second internal circuits. 3. A plurality of internal circuits each including a JTAG circuit; a JTAG test access port connected to the first and second internal circuits to form an external terminal; a TRST terminal of the JTAG test access port; T
In a semiconductor integrated circuit having a first control circuit connected to a CK terminal and forming a functional block including a counter, the debug support circuit formed by the JTAG circuit and the first control circuit includes a TRST terminal and a TCK.
A semiconductor integrated circuit, wherein a TRST signal and a TCK signal are input via terminals, respectively, and any one of the plurality of internal circuits is debugged by the functional block. 4. A plurality of internal circuits each including a JTAG circuit; a JTAG test access port connected to the first and second internal circuits to form an external terminal; a TMS terminal of the JTAG test access port; TC
A semiconductor integrated circuit comprising a second control circuit connected to a K terminal and forming a functional block including a counter, wherein the debug support circuit formed by the JTAG circuit and the second control circuit includes the TMS terminal and the TCK A semiconductor integrated circuit, wherein a TMS signal and a TCK signal are input via terminals, respectively, and any one of the plurality of internal circuits is debugged by the functional block.