JPH0258800A - Circuit and system for on-chip test for semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the test executing time by providing plural ROMs which store plural different test procedures after micro-coding the procedures. CONSTITUTION:This circuit is constituted of ROMs 1-i, a control circuit TC, and inspection circuit CC. The ROMs 1-i store plural micro-coded test procedures and the control circuit TC reads out and decodes the test procedures. The inspection circuit CC compares and inspects the information on an input-output line IO read out of a memory cell 10 with a signal from the control circuit TC and outputs a discriminated result F. The control circuit TC reads the test procedures from the ROMs 1-i upon receiving a test start signal TS and decides the test procedure to be executed by means of a select signal S. Since the plural test procedures are separately stored in the ROMs and an on-chip test is performed by using one of the procedures or combining some of the procedures in such way, length of the test pattern, namely, the testing time can be reduced as compared with the case where the test procedures stored in all ROMs are executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an on-chip test circuit and test method for mounting a semiconductor memory.

(Prior art) In recent years, in order to avoid the increase in test time and the complexity of test procedures due to the increase in capacity of semiconductor memories, several on-chip test methods have been developed in which the test procedures are mounted on the same chip as the semiconductor memory. Proposed. Among these, in the test method using ROM proposed by Kinoshita et al., it is possible to generate complex test patterns that can detect defects due to the influence of adjacent memory cells. It is superior to other testing methods in that it can be implemented using
ACTION SON COMPUTER 8), October 1986 issue, pp. 862-870).

In this test method, a series of predetermined test procedures is encoded and stored in a ROM, and the output from the ROM is used to generate test address generation circuits, test data generation circuits, and readout information from memory cells. It controls the test circuit and tests the entire semiconductor memory. The test result (whether the semiconductor memory is good or bad) can be known after completing a series of test procedures determined by the ROM, that is, after generating and applying all predetermined test patterns.

(Problems to be Solved by the Invention) In the conventional on-chip test method as described above, it is possible to generate complex test patterns that can test the influence of adjacent memory cells. Memory cells can only be tested using a series of test patterns. To this end, a series of test procedures that include all test patterns necessary to detect possible memory cell defects, regardless of the level of defect detection ability of the test patterns, must be stored in ROM and executed. become. Therefore, there is a problem that the test pattern becomes long and the test execution time becomes long.

SUMMARY OF THE INVENTION An object of the present invention is to provide an on-chip test circuit and test method for a semiconductor memory that has a high ability to detect defects in memory cells and a short test execution time.

(Means for Solving the Problem) In order to solve the conventional problems, the means used in the on-chip test circuit and test method for semiconductor memory of the present invention is an R
OM, a control circuit that receives an output signal from the ROM and generates a signal for automatically testing the semiconductor memory, and receives an output signal from the control circuit and compares and inspects the output information of the semiconductor memory. It has a plurality of ROMs, each of which stores a plurality of different test procedures in the form of microcodes. Furthermore, any one of the plurality of test procedures stored in the plurality of ROMs is selected and executed by an external signal. Moreover, any plurality of test procedures among the plurality of test procedures stored in the plurality of ROMs are selected by an external signal and executed continuously.

(Function) In the on-chip test circuit and test method for semiconductor memory of the present invention, a plurality of test procedures for generating test patterns necessary for detecting possible memory cell defects are prepared, and one or more of them are prepared. By selectively executing these tests, the test execution time can be shortened while the defect detection ability is high.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block configuration diagram when the on-chip test circuit of the present invention is applied to a semiconductor memory.

In the figure, the on-chip test circuit includes ROM (1, 2
, . . . i), a control circuit TC, and a test circuit CC. ROM (1, 2, ..., i) stores a plurality of microcoded test procedures, and controls the control circuit TC.
The contents (test procedure) are read out and deciphered. The inspection circuit CC receives the output signal from the control circuit TC, compares and inspects the information read out from the memory cell on the human output line IO, and outputs a judgment result F as to whether it is good or bad. The control circuit TC receives the test start signal TS and reads the ROM (
The test procedure is read from 1, 2, ..., i).

At this time, the selection signal S determines which ROM test procedure is to be executed. For example, the contents of ROM2 will be executed. Then, the control circuit TC outputs the test address determined by the ROM 2 test procedure onto the address line AD, and the X decoder 20 and Y decoder 30 select a memory cell in the memory cell array 10. Then, during a write operation, test data is written into the selected memory cell via the input/output line IO. During a read operation, the stored information of the selected memory cell is taken into the test circuit CC via the human output line IO, and comparison and test are performed.

The above operation is an example of executing one test procedure. If you are performing more than one test procedure, please refer to step 1 above.
After one test procedure is completed, the control operation of the control circuit TC is switched by the selection signal S so that the next test procedure is started.

In this way, by storing multiple sets of test procedures in separate ROMs and performing an on-chip test on one or some of them, it is much easier than executing test procedures for all ROMs. Therefore, the test pattern length, that is, the test time can be shortened. At this time, the defective memory cell detection ability can be improved by omitting test procedures that have low defect detection ability when considering the physical arrangement of memory cells.
It is possible to keep it almost constant compared to the conventional method.

Further, in cases where the defect detection ability may be lowered depending on the usage state of the semiconductor memory, the test method of the present invention can be used to further reduce the test time, which is effective.

(Effects of the Invention) As explained above, according to the on-chip test method and circuit for semiconductor memory of the present invention, a plurality of ROMs storing test procedures for generating test patterns for detecting memory cell defects are prepared. However, by selectively executing any of them, it is possible to shorten the test execution time while maintaining the necessary defect detection ability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an on-chip test circuit for semiconductor memory according to the present invention.

Claims (1)

[Claims] 1) RO that stores microcoded test procedures
M. A control circuit that receives an output signal from the ROM and generates a signal for automatically testing the semiconductor memory; and a test that receives the output signal from the control circuit and compares and inspects the output information of the semiconductor memory. 1. An on-chip test circuit for a semiconductor memory, comprising a plurality of ROMs for storing a plurality of different test procedures in the form of microcodes. 2) The on-chip test circuit for semiconductor memory according to claim 1, wherein any one of the plurality of test procedures stored in the plurality of ROMs is selected and executed by an external signal. On-chip test method for semiconductor memory. 3) In the on-chip test circuit for semiconductor memory according to claim 1, any plurality of test procedures among the plurality of test procedures stored in the plurality of ROMs are selected by an external signal and continuously executed. An on-chip test method for semiconductor memory featuring: