JP2002278849A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To store many pieces of fail information by effectively using fail memory without increasing a memory capacity. SOLUTION: Concerning a semiconductor testing device, a prescribed pattern is inputted from the input pin of a semiconductor device to judge whether the pattern passes or fails from whether a value outputted from an output pin by the inputting and the result of judging is stored in a fail memory. The testing device can store much fail information by effectively using the fail memory without increasing a memory capacity, by storing only the fail information in the fail memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor test apparatus for performing a function test of a semiconductor device, and more particularly to a technique for storing fail information in a fail memory.

[0002]

2. Description of the Related Art Conventionally, the function of a semiconductor device has been tested using a semiconductor test apparatus. At that time, if the function test performed by the semiconductor test apparatus fails, the fail information (fail address, fail pin, loop information, information such as an expected value and a fail value).
Is stored in the fail memory.

FIG. 23 is a diagram showing a configuration of a fail memory of a conventional system. In the fail memory, pins are specified in the horizontal direction, and a fail address is set in the vertical direction.
In the fail memory, one record has an address, a loop count,
It consists of expected value and fail value information. When a failure occurs at any of the pins at a certain address, the fail information is stored in the fail memory. At this time, the horizontal direction of the stored fail memory is an area for the address.

FIGS. 24, 25 and 26 are diagrams showing specific examples of FIG. In this example, the configuration of the fail memory has eight pins (horizontal direction) and six addresses (vertical direction).

FIG. 24 is a diagram showing an expected value and a test value at each address for each pin. A, B, C, D, and E represent pin names, and pin numbers 1 to 5 represent pin numbers assigned in the semiconductor test apparatus. 0 to 5 in the vertical direction represent each address, and hatching represents a fail. In this example, it is assumed that five failures have occurred.

FIG. 25 is a view showing the result of storing fail memory fail information based on the result of FIG.
Numerals 1 to 5 correspond to the numbers assigned to the fail shaded display in FIG. Only the pin where a failure has occurred is stored in the fail memory. However, if a failure occurs in any of the pins, a memory area is secured for the pins other than the fail pin at the same address.

FIG. 26 shows the information stored in each fail memory storing the fail information in FIG. The address, the number of loops, the expected value, and the fail value are the stored information.

[0008]

However, the configuration of the fail memory in the conventional semiconductor test apparatus is as shown in FIG. In the conventional method, when fail information is stored in the fail memory, a large amount of fail information cannot be stored because the memory area is used even for pins that have not failed as shown in FIG. . In particular, at the time of the scan test, although the fail pin is limited to the scan-out pin, as shown in FIG.
Since a storage area other than the scan-out pin is allocated to the fail memory, much fail information cannot be stored.

As a result, when many failures occur in the function test for one test pattern, fail information may not be stored in the fail memory. In the current semiconductor test apparatus, fail information that cannot be stored in the fail memory is discarded. Also,
At present, it is necessary for the user to intentionally clear the fail memory to avoid the overflow.

In order to store a large amount of fail information at a time, a large-capacity fail memory may be used.
Then, since the test apparatus becomes expensive, there is a demand for the development of a semiconductor test apparatus capable of storing a large amount of fail information with the current memory capacity, saving labor and shortening the test time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor test apparatus capable of easily storing a large amount of fail information in a fail memory without increasing the memory capacity. It is to provide.

[0012]

In order to achieve the above object, a feature of the present invention is that a predetermined pattern is input from an input pin of a semiconductor device, whereby a value output from an output pin is expected. In a semiconductor test apparatus that performs a function test for determining whether the value matches the pass or fail based on whether the value matches the value and stores the determination result in a fail memory
A means for storing only the fail information in the fail memory is provided.

A feature of the present invention is that a save memory for saving the information stored in the fail memory and, when the information storage in the fail memory overflows, transfers the already stored information to the save memory. The means have been provided.

A feature of the invention according to claim 3 is that a fail log is output from the information of the fail memory and the save memory.

A feature of the invention according to claim 4 is that after fail information is saved from the fail memory to the save memory when the fail memory overflows, the fail memory is cleared and the function test is started again. From the address, the function test is advanced without storing the fail information in the fail memory up to the address before the overflow in the previous functional test, and the fail information generated in the functional test after the overflow address is stored in the fail memory. It is in.

A feature of the invention of claim 5 is that a function test is held when the fail memory overflows,
After saving the fail information from the fail memory to the save memory, clearing the fail memory, resuming the function test from the held address, and storing the fail information occurring thereafter in the fail memory. is there.

A feature of the invention according to claim 6 is that a means for storing all of the judgment results in the fail memory and that only the fail information is stored in the fail memory or that all the judgment results are stored in the fail memory. And a selecting means for selecting the above.

According to a seventh aspect of the present invention, the selection means stores only the fail information in the fail memory or stores all the determination results in the fail memory depending on the type of a test program for generating the pattern. Is selected.

An eighth feature of the present invention is that a means for designating an output pin to be observed by the semiconductor device and storing only fail information of the output pin in the fail memory is provided.

According to a ninth aspect of the present invention, there is provided a timing generator for generating a timing from a timing value of each pin;
A pattern generator for generating pattern data to be given to each pin, a waveform generator for generating a waveform from timing and a pattern, and a test unit for testing whether an output signal from the semiconductor device matches an expected value of the test pattern When,
A fail memory for storing a judgment result obtained by the test, and storing in the fail memory all judgment results obtained by the test result in correspondence with all output pins of the semiconductor device, or corresponding to an output pin that has failed. A fail memory storage method determining unit for determining whether to store only fail information, a first fail information output unit for storing the determination result in the fail memory for all the output pins, and a fail of the determination result. It is provided with a specific pin storage type fail information output unit that stores in the fail memory in correspondence with an output pin that has failed only information, and a fail log output unit that outputs a fail log from the information of the fail memory.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration according to an embodiment of the semiconductor test apparatus of the present invention. The semiconductor test apparatus of the present example acquires a test cycle and a timing value of each pin from information of a test program to generate a timing, and acquires a pattern to be given to each pin in order of addresses from a test pattern. A pattern generating unit 2 for generating data, a waveform generating unit 3 for generating a waveform from timing and pattern information, and giving a waveform generated by the waveform generating unit 3 to a device. A test unit 4 for testing whether they match, a fail memory storage method determining unit 5 for determining whether the storage method in the fail memory 8 is a conventional method or a new specific pin storage method, and the result of the test is In the case of a failure, fail information is stored in a conventional manner based on the information of the fail memory storage method determination unit. The conventional fail information output unit 6 stores the fail information in the fail memory 8 according to the specific pin storing method of the present invention based on the information of the fail memory storing method judging unit when the result of the test is a fail. A specific pin storage type fail information output unit 7, a fail memory 8 for storing fail information which is a function test result of a semiconductor device, and a fail for moving fail information to the fail accumulation area 10 when storage in the fail memory 8 overflows. It comprises a fail log output unit 11 that outputs a fail log 12 based on the information of the storage unit 9, the fail memory 8 and the fail storage area 10.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. In the initialization of the fail memory 8 (step 201), more fail information can be stored in the storage area of the fail memory 8,
Before performing the test, the fail memory 8 is initialized. Also,
At this time, the fail accumulation area 10 is also initialized. Next, in the test (Step 202), a test of the semiconductor device is performed to determine whether a failure has occurred (Step 203). If a failure has occurred, the fail memory 8 and the fail memory are output in a fail log output process (Step 204). The information of the storage area 10 is output as a fail log. next,
It is determined whether there is a remaining test pattern (step 20).
5) If there are remaining test patterns, the process returns to the fail memory initialization process in step 201, and the above process is repeated. If there is no remaining test pattern, the process ends.

FIG. 3 is a flowchart showing the procedure of the process of the repetitive test method in the test process of step 202 shown in FIG. In the function test of a semiconductor device, an input pattern is given to each test pattern for each address, and a test is performed to check that an output signal of the device has an expected value. In the test pattern, input data and expected value data for testing for each address are prepared, and a test for a semiconductor device is performed for each address.

For this purpose, first, 0 is set to a stop address for storing an address when the fail memory 8 overflows (step 301), and initialization is performed. Next, the start address of the test pattern is set to the test address (step 302).

Next, the semiconductor device is tested using the pattern corresponding to the test address (step 303). At this time, it is determined whether or not a failure has occurred (step 30).
4) If a failure has occurred, the stop address is compared with the tested address (step 30).
5) If the test address is large or the same, the fail information is stored in the fail information storing process (step 3).
At 06), the data is stored in the fail memory 8, and the test of one address is completed.

After the test, it is determined whether or not the fail information has been stored in the fail memory 8 (step 30).
7) If the fail memory 8 is full and writing is not possible, the test address is stored in the stop address (step 308), and the contents of the fail memory 8 are failed by the fail accumulation processing (step 309). The fail memory 8 is copied to the storage area 10, and the fail memory 8 is initialized by the fail memory clear processing (step 310), so that fail information after the stop address can be stored.

If the fail information can be stored in the fail memory 8, it is determined whether or not the tested address is the last address (step 311). If not, the address is incremented (step 311). 312), the process returns to step 303, and the next address is tested. If it is the last address, the process ends.

FIG. 4 is a flowchart showing the detailed processing procedure of the fail information storage processing shown in step 306 of FIG. There are two processes for storing the fail information in the fail memory 8. First, it is determined whether a fail information storage method has been designated (step 401). If the fail information storage method is designated, the presence or absence of a scan pattern in the test data is determined (step 402). If the scan pattern exists in the test data, a specific pin storage method is selected (step 40).
4) The fail information is stored in the fail memory 8 by the fail memory storing method shown in FIG. If the scan pattern does not exist in the test data, the conventional memory storage method is selected (step 405), and the fail information is stored in the fail memory 8 by the fail memory storage method shown in FIG.

If the automatic selection is not specified as the fail information storage method, the storage method is checked (step 403). If the conventional method is specified, the conventional memory storage method is adopted (step 405). If the specific pin storage method is designated, the specific pin storage method is adopted (step 404).

FIG. 5 is a diagram showing an example of the configuration of the fail memory in the specific pin storage method shown in FIG. One record of the fail memory 8 is composed of information of an address, a pin number, the number of loops, an expected value, and a fail value. The records are stored in the fail memory 8 of the semiconductor test apparatus for the number of fail. The pin number here indicates a specific pin, and the specific pin means a fail pin. Further, when a pin to be stored in the fail memory 8 is designated, it means that the pin failed.

FIGS. 6, 7, 8 and 9 show specific examples of the fail memory configuration shown in FIG.

FIG. 6 is a diagram showing a test program specifying a repetitive test method. The test pattern is called by “TESTPATT”, and the first argument (“P
ATI ") is the test pattern name, the second argument (" RE
PEAT ") indicates that the repetition method is used, and the third argument (" 0 ") automatically selects the conventional method and the specific pin storage method as the storage method in the fail memory 8.

FIG. 7 is a diagram showing an expected value and a test value at each address for each pin. A, B, C, D, and E represent pin names, and pin numbers 1 to 5 represent pin numbers assigned in the semiconductor test apparatus. Pin C is a scanout pin. 14 to 16 in the vertical direction indicate each address, and 1
4 and 16 are scan test cycles, and 15 is a system cycle. Further, the 14 and 16 scan test cycles are looped by the number of scan patterns. In this example, there are four scan patterns. Note that hatching indicates a failure, and in this example, five failures are generated.

FIG. 8 is a view showing the result of storing fail memory fail information based on the result of FIG. In this example, it is assumed that there are 48 fail storage areas. Numerical values 1 to 5 correspond to the numbers assigned to the fail shaded display in FIG. Only those pins that have failed are stored in the fail memory 8, and these are sequentially stored from the beginning of the fail memory 8.

FIG. 9 is a diagram showing the storage information of each fail memory storing the fail information in FIG. Stores the address, loop count, expected value, and fail value.

FIGS. 10 to 13 are diagrams showing specific examples of the overflow processing in FIG. In this example, the area of the fail memory is set to 10 fail memories.

FIG. 10 is a diagram showing an expected value and a test value at each address for each pin, similarly to FIG. A, B, C,
D and E represent each pin name, 0 to 6 in the vertical direction represent each address, and hatching represents fail. This example shows that 10 failures have occurred at the time when the test is completed up to the fourth address.

FIG. 11 is a diagram showing a state of storing the failure generated in FIG. 10 in the fail memory 8. Since the area of the fail memory 8 is only 10 pieces, the state where all the fail memories are used up at the time when the 10 fail addresses up to the fourth address shown in FIG. 10 are stored is shown.

Thereafter, after the fail up to the fourth address is transferred to the fail accumulating area 10, the test is performed again from the first 0 address.

FIG. 12 is a diagram showing an example of storage in the fail memory when the test is performed again from the 0 address. The fail up to the fourth address is not stored in the fail memory 8, but the fail obtained by continuing the test from the fifth address onward is stored in the fail memory 8. Therefore,
FIG. 12 shows that the fail after the fifth address is stored in the fail memory 8.

FIG. 13 shows an example in which the information of the fail memory 8 is moved to the fail storage area 10, the fail memory 8 is cleared, and two fail addresses from the fifth address shown in FIG. FIG. When all the fail memories have been used in this way, the information in the fail memory 8 is moved to the fail storage area 10 and the test is repeated again from the beginning. The fail is stored in the fail memory 8. As a result, information on all the failures stored in the fail memory 8 and the fail accumulation area 10 is output to the fail log.

FIG. 14 is a flowchart showing a processing procedure when the test is performed by the test hold method in the test processing in step 202 of FIG. In the function test of a semiconductor device, an input pattern is given to each test pattern for each address, and a test is performed to check that an output signal of the device has an expected value.

The test pattern is prepared with input data and expected value data for performing a test for each address.
In testing a semiconductor device, a test is performed for each address. Therefore, first, 0 is set to a stop address for storing an address when the fail memory 8 overflows (step 141), and initialization is performed.

Next, the start address of the test pattern is set to the test address (step 142). Next, the semiconductor device is tested using the pattern corresponding to the test address (step 143). At this time, it is determined whether or not a failure has occurred (step 144). If a failure has occurred, the fail information is stored in the fail memory 8 in a fail information storage process ((step 145)).
The test of one address is completed.

After the test, it is determined whether or not the fail information has been stored in the fail memory 8 (step 14).
6) If the fail memory 8 is full and writing cannot be performed, the contents of the fail memory 8 are copied to the fail accumulation area 10 in a fail memory fail accumulation process (step 147) (step 148). In the memory clear processing (step 149), the fail memory 8 is initialized so that fail information after the stop address can be stored. That is, in this example, when the fail memory 8 overflows, the test is temporarily stopped, and when the test is continued, the test is started from the address after the stop address and the obtained fail information is failed. The data is written to the memory 8.

If the fail information can be stored in the fail memory 8, it is determined whether the tested address is the last address (step 149). If not, the address is incremented (step 150). ), The process returns to step 143, and the next address is tested. If it is the last address, the process ends.

FIGS. 15 to 19 are diagrams showing specific examples of the overflow processing in FIG. FIG. 15 is a diagram showing a test program specifying the test hold method. The test pattern is called by “TESTPATT”, the first argument (“PAT2”) is the test pattern name, the second argument (“HOLD”) is the test hold method, and the third argument (“2”) is This shows that a specific pin storage method is used as a storage method in the fail memory.

FIG. 16 is a diagram showing an expected value and a test value at each address for each pin, similarly to FIGS. 7 and 10. A,
B, C, D, and E represent the names of the respective pins, 0 to 6 in the vertical direction represent the respective addresses, and hatching represents a fail. This example shows that 10 failures have occurred at the time when the test is completed up to the fourth address.

FIG. 17 shows a state in which all the fail memories are used up at the time when the ten fail addresses up to the fourth address shown in FIG. 16 are stored because the area of the fail memory 8 is only 10 pieces. FIG.

FIG. 18 is a diagram showing that the test is held at the fourth address where the fail memory 8 has been completely used. After the hold, the information in the fail memory 8 is moved to the fail storage area 10 and the fail memory 8 is cleared. Then, the test for the fifth and subsequent addresses is continuously performed.

FIG. 19 is a diagram showing an example in which three failures after the fifth address shown in FIG. 18 are stored in the failure memory 8. In this way, in the test hold method, the test is held when all the fail memories are used up,
After the information in the fail memory 8 has been moved to the fail storage area 10, the fail memory 8 is cleared and the fail generated in the subsequent address test is newly stored in the fail memory 8. As a result, information on all the failures stored in the fail memory 8 and the fail accumulation area 10 is output to the fail log.

FIGS. 20, 21 and 22 are diagrams showing examples in which only the specific pins shown in the processing of step 3 in FIG.

FIG. 20 is a view showing a test program designating that only fail information of a specific pin is stored in the fail memory 8. The test pattern is called by “TESTPATT” and the first argument (“PATPATT”)
3 ") is the test pattern name and the second argument (" HOL
D ") selects the test hold method, the third argument (" 2 ") selects the specific pin storage method as the storage method in the fail memory, and the fourth and fifth arguments select the terminal C and terminal D, respectively. It indicates that.

FIG. 21 is a diagram showing an expected value and a test value at each address for each pin, similarly to FIGS. 7, 10 and 16. A, B, C, D, and E represent each pin name, 0 to 6 in the vertical direction represent each address, and hatching represents fail. This example shows that 13 failures have occurred when the test is completed up to 6 addresses.

FIG. 22 shows the results of the test shown in FIG.
Only fail information of pins C and D is stored in fail memory 8
FIG. 10 is a diagram showing a fail memory storage state when it is designated to store in a fail memory.

According to the present embodiment, (1) in the fail memory 8 for storing the result of the failure of the function test, the storage area for each pin is not determined in advance, but the information on the failed pins is sequentially stored in the memory area. By storing, the memory can be used effectively without the unused area as in the related art. As a result, more fail information can be stored, and this is particularly effective at the time of a scan test in which a fail pin is limited to a scan-out pin. (2) If the number of failures is large and the fail memory 8 overflows, the fail information stored in the fail memory 8 can be moved and stored in the fail storage area 10. When the fail log is output, the information can be output from this area, so that more fail information can be output to the fail log. (3) In the fail memory 8 for storing the result of the failure of the functional test, the storage method of the fail memory 8 can be selected according to the test data and the type of the test, and the fail memory can be used effectively.
(4) When the fail memory 8 overflows in the fail memory 8 for storing the fail result of the function test, the fail information in the fail memory is saved to the fail storage area 10 at that time, and after the fail memory 8 is cleared, the function is cleared. By repeating the test again, the fail information that could not be stored in the fail memory 8 in the previous functional test can be stored in the fail memory 8, and all the fail information stored in the fail memory 8 and the fail storage area 10 can be stored. Can be output to the fail log. This is effective for analyzing the cause of failure.
(5) In the case of a semiconductor device capable of holding the function test in the middle of the pattern, the function test is held at the address where the fail memory 8 overflows, and the information in the fail memory 8 is saved in the fail storage area 10 to fail memory. By clearing 8, fail information generated after the overflow address can be stored in the fail memory 8. As a result, all the fail information stored in the fail memory 8 and the fail accumulation area 10 can be output to the fail log in one functional test. This is effective in analyzing the cause of the failure and shortens the test time. (6) Instead of storing the fail information of all the pins in the fail memory 8, only the fail information of the pin specified in advance is stored in the fail memory 8.
As a result, when investigating the cause of a failure that depends on a specific pin, for example, a large amount of fail information specific to the failure can be collected, and the fail memory 8 can be used effectively.

In the embodiment of the present invention, a mode in which the fail information can be stored in the conventional manner can be selected. However, this is not essential, and only the fail information is sequentially stored in the fail memory 8. Even with the configuration having only the above, the essence is not lost, and almost the same effect is obtained.

The present invention is not limited to the above-described embodiment, and may be embodied in various other forms in terms of specific structure, function, operation, and effect without departing from the gist thereof. .

[0059]

As described above in detail, according to the present invention, a large amount of fail information can be stored by effectively utilizing the fail memory without increasing the memory capacity, and the test of the semiconductor device can be efficiently performed. It can be performed quickly and in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration according to an embodiment of a semiconductor test apparatus of the present invention.

FIG. 2 is a flowchart showing an operation procedure of a function test by the device shown in FIG. 1;

FIG. 3 is a flowchart showing a procedure of a process of a repetitive test method in the test process of step 202 shown in FIG. 2;

FIG. 4 is a flowchart showing a detailed processing procedure of a fail information storing process shown in Step 306 of FIG. 3;

FIG. 5 is a diagram showing a configuration example of a fail memory in the specific pin storage method shown in FIG. 4;

FIG. 6 is a diagram showing an example of a test program specifying a repetitive test method to be performed by the apparatus shown in FIG. 1;

FIG. 7 is a schematic diagram showing an expected value and a test value at each address for each pin stored in the fail memory shown in FIG. 1;

FIG. 8 is a schematic diagram showing a result of storing fail memory fail information based on the result of FIG. 7;

FIG. 9 is a diagram showing information stored in each fail memory storing the fail information shown in FIG. 8;

FIG. 10 is a diagram showing an expected value and a test value at each address for each pin stored in the fail memory shown in FIG. 1;

FIG. 11 is a diagram showing a state of storing a failure generated in FIG. 10 in a fail memory.

12 is a diagram showing an example of storage in a fail memory when a test is performed again from address 0 in the apparatus shown in FIG. 1;

FIG. 13 shows fail 2 after the fifth address shown in FIG.
FIG. 9 is a diagram showing an example in which the number is stored in a fail memory.

FIG. 14 is a flowchart showing a processing procedure in the case of performing a test hold method in the test processing in step 202 of FIG. 2;

FIG. 15 is a diagram showing a test program specifying a test hold method in the apparatus of FIG. 1;

FIG. 16 is a diagram showing an expected value and a test value at each address for each pin stored in the fail memory shown in FIG. 1;

FIG. 17 is a diagram showing a state in which all fail memories are completely used.

FIG. 18 is a diagram showing that the test is held at the fourth address when the fail memory is completely used.

FIG. 19 is a diagram showing an example in which three failures after the fifth address shown in FIG. 18 are stored in a failure memory.

FIG. 20 is a diagram showing a test program designating that only the fail information of the specific pin shown in the process of step 3 in FIG. 4 is stored in the fail memory.

FIG. 21 is a diagram showing an example in which only the specific pin shown in the process of step 3 in FIG. 4 is stored in the fail memory.

22 is a diagram showing a fail memory storage state when it is specified that only the fail information of pins C and D among the test results shown in FIG. 21 is stored in the fail memory;

FIG. 23 is a diagram showing a configuration example of a fail memory of a conventional semiconductor test apparatus.

FIG. 24 is a diagram showing an expected value and a test value at each address for each pin stored in the fail memory of FIG. 23;

FIG. 25 is a diagram illustrating a result of storing fail memory fail information based on the result of FIG. 24;

26 is a diagram showing information stored in each fail memory storing the fail information shown in FIG. 25;

FIG. 27 is a diagram showing information of each scan-out pin stored in the fail memory of FIG. 23 and information of other pins.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Timing generation part 2 Pattern generation part 3 Waveform generation part 4 Test part 5 Fail memory storage method judgment part 6 Conventional type failure information output part 7 Specific pin storage type failure information output part 8 Fail memory 9 Fail storage part 10 Fail storage area 11 Fail log output unit 12 Fail log

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) G01R 31/28 H (72) Inventor Masaki 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Co., Ltd. Within the company (72) Inventor: Morikawa Noriyuki 25-1, Ekimae Honmachi, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Toshiba Microelectronics Co., Ltd. (72) Inventor: Mamoru Takatsuka 25-1, Ekimae-Honmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Corporation (72) Inventor Yusuke Inoue 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Toshiba Microelectronics Corporation (72) Inventor Daiji Takeuchi 25-1, Ekimae Honmachi, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Toshiba Microelectronics Corporation F-term (reference) 2 G132 AA08 AB01 AC03 AC14 AE06 AE14 AE19 AE23 AG12 AK23 AL09 AL12 5B018 GA04 KA03 QA15 5B048 CC02 DD08 5L106 DD03 DD08 DD22 DD24 DD25 GG05 GG07

Claims (9)

[Claims] 1. A function test in which a predetermined pattern is input from an input pin of a semiconductor device and a pass or fail is determined based on whether or not a value output from an output pin matches an expected value. A semiconductor test apparatus for storing a result in a fail memory, comprising: means for storing only the fail information in the fail memory. 2. A save memory for saving information stored in the fail memory, and means for transferring information already stored to the save memory when information storage in the fail memory overflows. 2. The semiconductor test apparatus according to claim 1, wherein: 3. A fail log is output from information on the fail memory and the save memory.
A semiconductor test apparatus according to claim 1. 4. After fail information is saved from the fail memory to the save memory when the fail memory overflows, the fail memory is cleared, and the function test is performed again from the head address. The function test proceeds without storing fail information in the fail memory up to the address before the overflow in the function test, and stores fail information generated in the function test after the overflow address in the fail memory. 4. The semiconductor test device according to 2 or 3. 5. A function test is held when the fail memory overflows, after fail information is saved from the fail memory to the save memory, the fail memory is cleared, and the function test is executed from the held address. 4. The semiconductor test apparatus according to claim 2, wherein fail information generated after the restart is stored in the fail memory. 6. A means for storing all of the judgment results in the fail memory, and a selecting means for selecting whether to store only the fail information in the fail memory or to store all of the judgment results in the fail memory. The semiconductor test apparatus according to any one of claims 1 to 5, further comprising: 7. The method according to claim 1, wherein the selecting unit selects whether to store only the fail information in the fail memory or to store all of the determination results in the fail memory according to a type of a test program for generating the pattern. 7. The semiconductor test apparatus according to claim 6, wherein: 8. The semiconductor device according to claim 1, further comprising means for designating an output pin to be observed by the semiconductor device and storing only fail information of the output pin in the fail memory. Testing equipment. 9. A timing generator for generating timing from a timing value of each pin, a pattern generator for generating pattern data given to each pin, a waveform generator for generating a waveform from the timing and the pattern, and a semiconductor device. A test unit that tests whether an output signal of the test pattern matches an expected value of the test pattern; a fail memory that stores a determination result obtained by the test; A fail memory storage method determining unit for determining whether to store all determination results obtained in the test result or to store only fail information in response to a failed output pin; and A first fail information output unit for storing the failure information in the fail memory in correspondence with the first failure information output unit; A specific pin storage type fail information output unit that stores in the fail memory in correspondence with an output pin that has failed only the file information, and a fail log output unit that outputs a fail log from the information of the fail memory. Semiconductor test equipment.