JP4704131B2 - Test apparatus and test method - Google Patents

Description

  The present invention relates to a test apparatus and a test method for testing a device under test having a plurality of output pins. In particular, the present invention relates to a test apparatus and a test method for performing a scan test of a device under test.

  Conventionally, a function test is known as a technique for testing a device under test such as a semiconductor device. The function test is a method of inputting a predetermined test pattern to the data input pin of the device under test, operating the device under test, and testing whether the output signal output from the device under test matches the expected value signal. It is.

  However, with the increase in scale and functionality of devices under test, it is difficult to improve test coverage in conventional function tests. For this reason, a scan test may be performed to improve test coverage.

  The scan test is performed by setting predetermined data from the outside to a flip-flop provided inside the device under test and reading the state of the flip-flop to the outside. The flip-flops used for the scan test are connected in series by a circuit wiring called a scan chain in addition to a circuit wiring for performing a normal operation inside the device under test. In the scan test, scan data is input to the first stage of the flip-flop connected by the scan chain, and the data of the last stage of the flip-flop connected by the scan chain is read.

  As described above, the test coverage can be improved by dividing the plurality of flip-flops provided in the device under test regardless of the actual operation unit and performing the test. Further, it is possible to specify which element of the device under test is defective by using a plurality of scan pattern data.

  Since related patent documents and the like are not currently recognized, description thereof is omitted.

  However, in order to determine which element is defective by the scan test, it is necessary to test using the same number of data patterns as the flip-flops connected by the scan chain of the device under test. Therefore, when a scan test is performed on a large device under test, it is necessary to input a very large number of data patterns.

  In order to analyze the test results, it is necessary to store the output data output for each data pattern. However, since a large amount of output data must be stored, a large-capacity storage device is required. Necessary. A conventional test apparatus includes a log memory for storing a test result or the like for each comparator pin that receives an output signal of a device under test. However, the conventional test apparatus is centered on the function test function. For this reason, the capacity of each log memory is designed to be a capacity capable of storing the test result of the function test, and the capacity is small for storing the test result of the scan test.

  In addition, when storing the test result of the scan test in the log memory, it is unclear which comparator pin is connected to the scan test pin. Must be large enough to store Since the log memory is provided for each comparator pin, it is difficult from the viewpoint of cost to increase the capacity of all the log memories.

  For this reason, the conventional test apparatus divides the test result of the scan test and stores it in the log memory. In other words, the same scan pattern is executed a plurality of times, and output data output for each scan pattern is divided and stored sequentially according to the capacity of the log memory. At this time, the data stored in the log memory needs to be read each time the scan pattern is executed. With this operation, the entire output data for the scan pattern is stored. However, since it is necessary to execute the same scan pattern a plurality of times and to read the data in the log memory for each execution, the test efficiency is greatly reduced.

  Therefore, an object of the present invention is to provide a test apparatus and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above problem, in the first embodiment of the present invention, a test apparatus for testing a device under test having a plurality of output pins, wherein a scan pattern for performing a scan test of the device under test is represented by A pattern input unit that inputs to the device, a pin selection unit that selects a scan output pin that outputs a signal corresponding to the scan pattern, and a signal that is output by the scan output pin selected by the pin selection unit A test apparatus including a capture memory storing corresponding data is provided.

  It further includes a plurality of log memories provided corresponding to the plurality of output pins and storing data corresponding to signals output from the corresponding output pins, and the storage capacity of the capture memory may be larger than the storage capacity of the log memory .

  The test apparatus compares each data value of the signal output from the scan output pin with an expected value given in advance and outputs a comparison result signal indicating whether or not they match, and a comparison result signal And a compression unit that compresses the data and stores it in the capture memory.

  In the comparison result signal, the compression unit determines whether or not at least one of the data values of the signal output from the scan output pin is a failure, and the comparison is performed when the determination unit detects a failure. You may have a memory control part which matches and stores a result signal and the pattern identification information which shows the signal which the scan output pin corresponding to the said comparison result signal outputs.

  The compression unit may stop the scan test of the device under test when the remaining amount of the storage area of the capture memory becomes a predetermined value or less. The compression unit resumes the scan test of the device under test after taking the data stored in the capture memory into the control device of the test apparatus when the remaining amount of the storage area of the capture memory becomes a predetermined value or less. Good.

  According to a second aspect of the present invention, there is provided a test method for testing a device under test having a plurality of output pins, a pattern input step of inputting a scan pattern for performing a scan test of the device under test to the device under test; , A pin selection stage for selecting a scan output pin that outputs a signal corresponding to a scan pattern from among a plurality of output pins, and a capture stage for storing data corresponding to the signal output by the scan output pin selected in the pin selection stage A test method comprising:

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 is a diagram illustrating an example of a configuration of a test apparatus 100 according to an embodiment of the present invention. The test apparatus 100 is an apparatus for testing a device under test 200 having a plurality of output pins, and includes a timing generation unit 10, a pattern generation unit 12, a waveform shaping unit 14, a driver 16, a comparator 18, a logical comparison unit 20, and a pin. A selection unit 22 and a capture memory 24 are provided. The test apparatus 100 has a function of performing a function test and a scan test of the device under test 200. First, the operation when the function test is performed will be described.

  The pattern generator 12 generates a test pattern to be supplied to the device under test 200 according to a given periodic clock. The timing generation unit 10 generates a periodic clock having a period corresponding to the timing set signal received from the pattern generation unit 12 and supplies it to the pattern generation unit 12. Further, the timing generation unit 10 generates a delay clock having a period corresponding to the timing set signal and supplies the delayed clock to the waveform shaping unit 14.

  The waveform shaping unit 14 shapes the waveform of the test pattern according to the given delay clock. The driver 16 functions as a pattern input unit that inputs the test pattern formed by the waveform forming unit 14 to the device under test 200. The pattern generation unit 12, the waveform shaping unit 14, and the driver 16 are provided for each input pin of the device under test 200, and each input a test pattern to the corresponding input pin.

  The logic comparison unit 20 receives an output signal output from the device under test 200 via the comparator 18. The logic comparison unit 20 compares the output signal with the expected value signal received from the pattern generation unit 12, and outputs a comparison result signal indicating whether or not they match. The comparison result signal is, for example, a signal that compares each bit of the output signal with each bit of the expected value signal and indicates “0” for the matching bit and “1” for the non-matching bit. . The logic comparison unit 20 and the comparator 18 are provided for each output pin of the device under test 200 and receive an output signal output from the corresponding output pin.

  Each comparison result signal is sequentially stored for each test pattern in a log memory provided for each output pin. The control device that controls the test apparatus 100 reads the comparison result signal stored in the log memory and analyzes the test result. The said control apparatus may be a workstation etc., for example.

  Next, an operation when a scan test of the device under test 200 is performed will be described. In this case, the pattern generation unit 12, the waveform shaping unit 14, and the driver 16 corresponding to the input pins to which the test pattern for the scan test (scan pattern) of the device under test 200 is to be input input the scan pattern to the input pins. To do.

  FIG. 2 is a diagram showing an example of the configuration of the internal circuit of the device under test 200. A plurality of flip-flops 202 for performing a scan test are provided inside the device under test 200. Each flip-flop 202 is provided on each wiring through which a signal is transmitted during the actual operation of the device under test 200. Further, the flip-flops 202 are connected in series by a wiring called a scan chain, which is different from the wiring used in the actual operation of the device under test 200.

  The scan pattern (SCAN IN) is input to flip-flops 202 connected in series by a scan chain. Each flip-flop 202 is supplied with a scan clock (SCAN CLK) given during a scan test in addition to an operation clock (CLK) given during actual operation.

  A signal (SCAN OUT) output from each flip-flop 202 connected in series is output from a scan output pin connected to the scan chain. The pin selection unit 22 selects a scan output pin that outputs a signal corresponding to a scan pattern from among a plurality of output pins of the device under test 200. In this example, the pin selection unit 22 selects a comparison result signal corresponding to the scan output pin from the comparison result signals output from the logic comparison unit 20 and inputs the comparison result signal to the capture memory 24.

  Which output pin the pin selection unit 22 selects as a scan output pin may be preset by the user, and based on the pin arrangement information of the device under test 200 given in advance by the user. 22 may select. The test apparatus 100 may further include a register that stores in advance control information indicating which output pin the pin selection unit 22 should select and controls the pin selection unit 22.

  The capture memory 24 stores data corresponding to the signal output from the scan output pin selected by the pin selection unit 22. In this example, the capture memory 24 stores a comparison result signal corresponding to the scan output pin. In another example, a signal output from the scan output pin may be stored, or data obtained by compressing the comparison result signal may be stored. With such a configuration, the test result of the scan test can be stored in the capture memory 24. Here, the capture memory 24 desirably has a larger storage capacity than a log memory provided for each pin. Thereby, in the scan test that requires a large storage capacity, the number of times of reading the test result from the test apparatus 100 can be reduced, and the test can be performed efficiently.

  FIG. 3 is a diagram illustrating another example of the configuration of the test apparatus 100. The test apparatus 100 in this example further includes a plurality of log memories 26, a compression unit 30, and a control device 28 in addition to the configuration of the test apparatus 100 shown in FIG. Further, the timing generation unit 10, the pattern generation unit 12, the waveform shaping unit 14, the driver 16, and the comparator 18 are the same as those in the test apparatus 100 shown in FIG.

  The plurality of log memories 26 are provided corresponding to the plurality of output pins of the device under test 200 and store data corresponding to signals output from the corresponding output pins. In this example, each log memory 26 stores a comparison result signal with respect to a signal output from a corresponding output pin for each test pattern input to the device under test 200 during a function test.

  In the scan test, it is necessary to input a large number of scan patterns to the device under test 200 and store a comparison result signal for each scan pattern. Therefore, the amount of test result data to be stored is larger than that in the function test. For this reason, it is desirable that the storage capacity of the capture memory 24 is larger than the storage capacity of the log memory 26. When output signals corresponding to the scan pattern are output from a plurality of output pins of the device under test 200, the pin selection unit 22 selects the plurality of output pins, and the capture memory 24 outputs the plurality of outputs. Stores data corresponding to pins. For example, each log memory 26 may have a storage capacity of about 256 to 1 kbit, and the capture memory 24 may have a storage capacity of about 64 kbit × 8 to 16 pins.

  The compression unit 30 also compresses the comparison result signal output from the pin selection unit 22 and stores it in the capture memory 24. A known method can be used as a data compression method in the compression unit 30. By storing the comparison result signal after data compression, a larger number of comparison result signals can be stored in the capture memory. For this reason, a scan test can be performed more efficiently.

  In general, the comparison result signal has better compression efficiency than the signal output from the device under test 200. Since the output signal of the device under test 200 has a random pattern, it is difficult to improve the compression efficiency. On the other hand, the comparison result signal is converted into a pass / fail indicating whether or not each bit of the output signal matches the expected value signal. For this reason, the comparison result signal is not a random pattern, and data compression can be performed with high compression efficiency.

  For example, when the pattern of the output signal of the device under test 200 is “10110101” and only the first bit of the output signal is “fail”, the pattern of the comparison result signal is “10000000”. Thus, although the pattern of the output signal is random, the pattern of the comparison result signal has a low probability of being random, so that data compression can be performed at a high compression rate. The test apparatus 100 in this example can store the test result in the capture memory 24 very efficiently by compressing the comparison result signal.

  The control device 28 is, for example, a workstation for controlling the test apparatus 100, reads the comparison result signal stored in the capture memory 24, and analyzes the test result. For example, the control device 28 may stop the scan test of the device under test 200 and read the data stored in the capture memory 24 when the remaining amount of the storage area of the capture memory 24 becomes a predetermined value or less. Further, the compression unit 30 may perform the determination of the remaining amount of the storage area of the capture memory 24, the scan test stop control, and the data read control of the capture memory 24. For example, the compression unit 30 monitors the total amount of data stored in the capture memory 24 and calculates the remaining storage area of the capture memory 24 based on the maximum storage capacity of the capture memory 24 given in advance and the total amount of data. You can do it. Further, the control device 28 may cause the test device 100 to restart the scan test after reading the data in the capture memory 24.

  FIG. 4 is a diagram illustrating an example of the configuration of the compression unit 30. In this example, the compression unit 30 receives the comparison result signals sequentially output by the pin selection unit 22, and when at least one of the data values of the signals output by the scan output pins is “fail”, the corresponding comparison result signal is output. Store in the capture memory 24. At this time, the compression unit 30 stores the pattern identification information indicating which of the signals output from the scan output pin corresponds to the comparison result signal and the comparison result signal in the capture memory 24. To do. In another example, the comparison result signal may be stored in the capture memory 24 in association with the pattern identification information for identifying the scan pattern corresponding to the comparison result signal. With such control, only the comparison result signal necessary for analysis of the test result can be stored in the capture memory 24. Therefore, many test results can be stored in the capture memory 24.

  The compression unit 30 includes a determination unit 40 and a memory control unit 32. The determination unit 40 includes an OR circuit 42 and an AND circuit 44. The OR circuit 42 sequentially receives the comparison result signals from the pin selection unit 22 and determines whether or not there is data indicating failure (data indicating data value 1 in this example) in each bit of each comparison result signal. To detect. When there is data indicating fail, the OR circuit 42 outputs a data value 1, and when there is no data indicating fail, the OR circuit 42 outputs a data value 0.

  The logical product circuit 44 controls whether or not the comparison result signal is stored in the capture memory 24 according to the logical product of the control signal received from the control device 28 and the signal output from the logical sum circuit 42, for example. Here, the control signal is a signal indicating a data value 1 when the test result is to be stored in the capture memory 24. A signal output from the AND circuit 44 is input to the write enable terminal WE of the capture memory 24 and controls the write operation of the capture memory 24.

  The memory control unit 32 includes a buffer 34, an address pointer 36, and a counter 38. The address pointer 36 sequentially designates the address at which the capture memory 24 stores the comparison result signal in accordance with a given operation clock. In this example, the address pointer 36 sequentially generates addresses according to the operation clock when the AND circuit 44 outputs a signal for writing the comparison result signal to the capture memory 24. By such control, every time the capture memory 24 stores the comparison result signal and the pattern identification information, the next address of the capture memory 24 can be designated. For this reason, the storage efficiency of the capture memory 24 can be improved.

  The counter 38 counts the applied operation clock while the control signal indicates the data value 1. The counter 38 inputs the count value of the operation clock as pattern identification information in association with the comparison result signal to the capture memory 24. Here, the cycle of the operation clock given to the address pointer 36 and the counter 38 is substantially the same as the cycle in which the scan pattern is input to the device under test 200 or the cycle in which the device under test 200 outputs an output signal.

  FIG. 5 is a diagram illustrating an example of pattern identification information and comparison result signals (capture data) stored in the capture memory 24. As described with reference to FIG. 4, the capture memory 24 in this example sequentially stores comparison result signals in which data indicating failure is present at addresses sequentially designated by the address pointer 36. Further, the pattern identification information given from the counter 38 is stored in association with the comparison result signal. In this example, the comparison result signal is an 8-bit signal.

  With such a configuration, a test result indicating whether a failure has occurred in which output signal of the output signals output from the device under test 200 and which bit of the output signal has failed, It can be stored efficiently.

  In the capture memory 24, when the remaining capacity of the storage capacity becomes a predetermined value or less, it is necessary to stop the input of the scan pattern and read the data stored in the capture memory 24. On the other hand, according to the test apparatus 100 in this example, the test result can be stored more efficiently, so that a larger number of scan patterns can be continuously input. Therefore, the scan test can be performed efficiently.

  FIG. 6 is a diagram illustrating another example of the configuration of the compression unit 30. The compression unit 30 in this example performs so-called run length compression (Run Length Encoding) on each comparison result signal and stores it in the capture memory 24. Run-length compression is a method of compressing a given data string by using a number of consecutive data values. The compression unit 30 is not limited to the configuration shown in FIG. 6 and may perform run-length compression using a known configuration. The compression unit 30 may perform run-length compression for each bit of the comparison result signal.

  The compression unit 30 includes a compression circuit 60, an address pointer 54, and a buffer 58. The compression circuit 60 includes flip-flops 45 and 46, an exclusive OR circuit 48, AND circuits 50 and 52, and a counter 56.

  The flip-flops 45 and 46 and the exclusive OR circuit 48 convert the data of each bit of the comparison result signal given continuously into data indicating the data value 1 when the bit value transitions from the previous bit. The AND circuits 50 and 52 and the counter 56 count the number of data during the transition of the data value in the comparison result signal for each data transition based on the data string output from the exclusive OR circuit 48.

  The address pointer 54 designates the next address to the capture memory 24 every time the data value transitions in the comparison result signal. Further, when the data value transitions in the comparison result signal, the buffer 58 associates the data value in the comparison result signal with the number of data counted by the counter 56 and writes it in the capture memory 24.

  With such a configuration, the comparison result signal can be compressed and stored in the capture memory 24. According to the compression unit 30 in this example, each comparison result signal is compressed as a continuous data string, so that data can be compressed more efficiently. That is, when comparison result signals without fail data are consecutive, a plurality of comparison result signals can be indicated by a set of compressed data. For this reason, data can be compressed more efficiently.

  Further, when testing the device under test 200 with high reliability, the ratio of the comparison result signal having no fail data in all the comparison result signals becomes high. In such a case, data can be compressed particularly efficiently.

  FIG. 7 is a flowchart showing an example of a test method according to the embodiment of the present invention. The test method in this example performs a scan test of the device under test 200 by the same method as the test apparatus 100 described with reference to FIGS.

  First, in a pattern input step S102, a scan pattern is input to the device under test 200. In the pattern input step S102, the scan pattern may be input by the same method as the timing generation unit 10, the pattern generation unit 12, the waveform shaping unit 14, and the driver 16 described with reference to FIG.

  Next, in the pin selection step S104, a scan output pin that outputs a signal corresponding to the scan pattern is selected from the plurality of output pins of the device under test 200. In the pin selection step S104, the scan output pin may be selected by the same method as the pin selection unit 22 described with reference to FIG.

  Next, in the compression step S106, signal data corresponding to the signal output from the scan output pin is compressed. For example, the data of the comparison result signal indicating the result of comparing the signal output from the scan output pin with the expected value signal is compressed. In the compression step S106, data compression may be performed by the same method as the compression unit 30 described with reference to FIG.

  Next, in the capture step S108, the compressed comparison result signal is stored in the capture memory. In the capture step S108, it is desirable to use a capture memory having a larger storage capacity than the log memory provided for each pin, as in the capture memory 24 described in relation to FIG.

  Next, in S110, it is determined whether or not all scan patterns have been input to the device under test 200. When all the scan patterns are input, the scan test is terminated. If all the scan patterns are not input, it is determined whether or not the remaining storage capacity of the capture memory 24 is equal to or less than a reference value (S112). When the remaining storage capacity of the capture memory 24 is larger than the reference value, the next scan pattern is input and the processing from S102 is repeated. Here, the reference value may be preset by the user. When the remaining storage capacity of the capture memory 24 is less than the reference value, the scan test is interrupted (S114). Then, data is read from the capture memory 24 (S116), and the processing from S102 is repeated. With such a test method, the scan test of the device under test 200 can be efficiently performed.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  As is apparent from the above, according to the present invention, a scan test of a device under test can be performed efficiently.

It is a figure which shows an example of a structure of the test apparatus 100 which concerns on embodiment of this invention. 2 is a diagram showing an example of the configuration of an internal circuit of a device under test 200. FIG. 3 is a diagram illustrating another example of the configuration of the test apparatus 100. FIG. 3 is a diagram illustrating an example of a configuration of a compression unit 30. FIG. It is a figure which shows an example of the pattern identification information and the comparison result signal (capture data) which the capture memory 24 stores. 6 is a diagram illustrating another example of the configuration of the compression unit 30. FIG. It is a flowchart which shows an example of the test method which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Timing generation part, 12 ... Pattern generation part, 14 ... Waveform shaping part, 16 ... Driver, 18 ... Comparator, 20 ... Logic comparison part, 22 ... Pin selection , 24 ... capture memory, 26 ... log memory, 28 ... control device, 30 ... compression unit, 32 ... memory control unit, 34 ... buffer, 36 ... address pointer , 38 ... counter, 40 ... determination unit, 42 ... logical sum circuit, 44 ... logical product circuit, 45, 46 ... flip-flop, 48 ... exclusive logical sum circuit, 50 52 ... AND circuit, 54 ... Address pointer, 56 ... Counter, 58 ... Buffer, 60 ... Compression circuit, 100 ... Test apparatus, 200 ... Device under test, 202 ... flip-flop

Claims (7)

A test apparatus for testing a device under test having a plurality of output pins,
A plurality of log memories that are provided corresponding to the plurality of output pins and store data corresponding to signals output by the corresponding output pins when performing a function test;
When performing a scan test of the device under test, the pattern input section of the scan pattern, and inputs the device under test,
Of the plurality of output pins, a pin selection unit that selects a scan output pin that outputs a signal according to the scan pattern;
A capture memory having a larger storage capacity than the log memory for storing data corresponding to a signal output by the scan output pin selected by the pin selection unit;
A logical comparison unit that outputs a comparison result signal indicating whether each data value of the signal output from the scan output pin and an expected value given in advance match each other;
And a compression unit that compresses the comparison result signal and stores it in the capture memory .   The test apparatus according to claim 1, wherein the compression unit executes run-length compression that compresses a given data string using a number of consecutive data values, and stores the comparison result signal in the capture memory. The compression unit is
A determination unit that determines whether at least one of the data values of the signal output from the scan output pin is a failure in the comparison result signal;
Memory control for storing the comparison result signal in the capture memory in association with the pattern identification information indicating the signal output from the scan output pin corresponding to the comparison result signal when the determination unit detects a failure The test apparatus according to claim 1 , further comprising: a testing unit. Said compression unit, when the remaining amount of the storage area of the capture memory is equal to or less than a predetermined value, the test device according the to the one scan testing claims 1 to stop 3 of the device under test. When the remaining amount of the storage area of the capture memory is equal to or less than a predetermined value, the compression unit causes the data stored in the capture memory to be taken into the control device of the test apparatus, and then the The test apparatus according to claim 4 , wherein the scan test is resumed.   The compression unit monitors the total amount of data stored in the capture memory, and compares the maximum storage capacity of the capture memory given in advance with the data total amount to calculate the remaining amount of the storage area of the capture memory The test apparatus according to claim 4 or 5. A test method for testing a device under test having a plurality of output pins,
A log storing step for storing data corresponding to a signal output by a corresponding output pin when the function test is provided corresponding to the plurality of output pins;
A pattern input step of inputting a scan pattern to the device under test when performing a scan test of the device under test;
A pin selection step of selecting a scan output pin that outputs a signal corresponding to the scan pattern among the plurality of output pins;
A capture step for storing data corresponding to a signal output by the scan output pin selected in the pin selection step with a storage capacity larger than the log storage step;
A logical comparison stage for outputting a comparison result signal indicating whether each data value of the signal output from the scan output pin and the expected value given in advance match each other;
A compression step of compressing the comparison result signal and storing it in the capture step .

Images