KR101034661B1 - Method and apparatus for testing memory device using 2 loading memories - Google Patents

Abstract

The present invention relates to a memory test method and an apparatus thereof, and more particularly, a plurality of test data provided to a device under test (DUT) to be tested are alternately loaded into a first loading memory and a second loading memory. The present invention relates to a test method and an apparatus of a memory device capable of reducing the loading time of test data and the generation time of a test pattern signal by alternately or sequentially outputting the loaded test data to the pattern signal generator.

The test apparatus of the memory device according to the present invention loads test data into a first loading memory and a second loading memory, and outputs the loaded test data to the pattern signal generator alternately or sequentially to generate a test pattern signal, thereby generating test data. It can reduce the loading time and the generation time of the test pattern signal. In addition, the test apparatus of the memory device according to the present invention can reduce the test time of the memory device by reducing the loading time of the test data and the generation time of the test pattern signal, thereby reducing the manufacturing cost of the memory device. .

Memory, DUT, Tester, Test Time, Data Loading

Description

Method and apparatus for testing memory device using 2 loading memories

The present invention relates to a memory test method and an apparatus thereof, and more particularly, a plurality of test data provided to a device under test (DUT) to be tested are alternately loaded into a first loading memory and a second loading memory. The present invention relates to a test method and an apparatus of a memory device capable of reducing the loading time of test data and the generation time of a test pattern signal by alternately or sequentially outputting the loaded test data to the pattern signal generator.

In general, memory products have a large amount of defects at the beginning of production and stabilize after a certain period of time, but suddenly increase as the product reaches the end of its life. Therefore, the high reliability that occurs early in the memory component must be effectively eliminated when the system is configured with memory to increase the initial reliability of the system.

In recent years, the capacity and performance of memory have increased greatly, but the process for testing memory has become more complicated and difficult. Therefore, the cost of testing memory is a high percentage of the total memory production cost. Therefore, the importance of test methods and equipment for accurately determining whether a memory is defective at an early time is increasing.

The test of the memory can be classified into a wafer test performed in a wafer state and a package test performed in a package state after the assembly process. The wafer test is further divided into a pre-laser test before the laser repair process and an electronic die sorting (EDS) test after the laser repair.

The die, which has been determined to pass the EDS test, is assembled into a packaged memory through an assembly process. The packaged memory is again subjected to a series of package tests. That is, first, a DC test is performed to determine whether there is an abnormality in the assembly process, a burn-in test is performed, and a high temperature package test and a low temperature package test are performed. Recently, burn-in tests and DC tests have been performed on wafers for efficiency.

In order to detect and eliminate the initial defect of the memory, a test pattern signal is applied to a memory device (DUT, Device Under Test) such as a die or a semiconductor on a wafer to test whether the device is normal (DC TEST), or the inherent function of the memory device. A system that tests this (Write / Read AC Test) is also called a memory tester.

1 and 2, a test system of a memory device and a test method of a memory device according to the related art will be described. 1 shows a schematic configuration diagram of a test system of a memory device according to the prior art, and FIG. 2 shows a flowchart of a test method of the memory device according to the prior art.

Referring to FIG. 1, a test system of a memory device according to the related art will be described in more detail. The main computer 1 includes an interface for inputting a user command and a processor and a memory device for test controlling the memory device according to the input user command. And a storage unit that stores test data for testing the data. When the user inputs a user command through an interface according to the type of memory device and the test type to be tested, the process reads test data corresponding to the user command from among a plurality of test data stored in the storage unit and loads the memory (3). To load. The pattern signal generator 5 generates a test pattern signal using the test data provided from the loading memory 3, and outputs the generated test pattern signal to the memory device DUT 7 to be tested. The test data is written to the memory device 7 according to the output test pattern signal, and the pattern signal generator 5 reads the data written in the memory diabis 7 again and transfers the read data to the main computer 1. do. The main computer 1 compares the test data written in the memory device 7 with the test result data read out from the memory diabis 7 to test the presence or absence of a failure of the memory device 7. An example of the pattern signal generator 5 may be an algorithm pattern generator (ALPG).

Meanwhile, referring to FIG. 2, in more detail, a test method of a memory device is loaded with test data corresponding to a test type of the memory device (S1). The pattern signal generation unit receives the test data to generate a test pattern signal corresponding to the test data, and provides the generated test pattern signal to the memory device (S3). The main computer determines whether the test of the memory device has ended (S5), and if the test is not finished, loads the next test data into the loading memory (S7) and the above-described steps S1 to S5 until the test of the memory device is completed. Repeat the steps.

The test method of the memory device according to the related art as described above generates a test pattern signal by loading test data into a loading memory every time and outputting the loaded test data to the pattern signal generator when a plurality of test data are used. In the field of memory devices, in which the test lead time plays an important role in determining the cost of the memory device, a test method of a memory device according to the prior art is used to test a memory device due to the loading time of repeated test data and the generation time of the test pattern signal. The problem is that it takes a long time.

In order to solve this conventional problem, another conventional technology uses a large capacity loading memory to load and use all test data used for testing a memory device at once. However, this conventional technology has a problem that the cost of the loading memory is increased and a high performance processor must be used together.

Accordingly, an object of the present invention is to provide a test device of a memory device that can reduce the test time of the memory device by reducing the loading time of the test data and the generation time of the test pattern signal.

Another object of the present invention is to provide a test device for a memory device that can reduce the test time of the memory device using only a small capacity of the first loading memory and the second loading memory.

Another object of the present invention is to provide a test device for a memory device that can quickly test the memory device in various modes according to the number of test data used for the test of the memory device.

In order to achieve the object of the present invention, a test apparatus for a memory device according to the present invention includes a first loading memory for storing first test data, a second loading memory for storing second test data, a first loading memory or The pattern signal generator for generating a test pattern signal according to the test data input from the second loading memory and the loading operation of the first loading memory or the second loading memory and the pattern signal generator according to the input mode selection command of the user. And a controller for controlling the generation order of the pattern signal.

The control unit generates a pattern signal according to the mode selection command based on the loading control unit for controlling the loading of the test data into the first loading memory or the second loading memory according to the mode selection command and the test data stored in the first loading memory or the second loading memory. It characterized in that it comprises a pattern signal control unit provided by the negative.

Preferably, the mode selection command selects one of a single mode using one test data, a dual mode using two test data, and a multiple mode using three or more test data.

The test apparatus of the memory device according to the present invention has various effects as follows in comparison with the prior art.

First, the test apparatus of a memory device according to the present invention loads test data into a first loading memory and a second loading memory, and alternately or sequentially outputs the loaded test data to the pattern signal generator to generate a test pattern signal. The loading time of the test data and the generation time of the test pattern signal can be reduced.

Second, the test apparatus of the memory device according to the present invention can reduce the test time of the memory device by reducing the loading time of the test data and the generation time of the test pattern signal, thereby reducing the manufacturing cost of the memory device .

Third, the test apparatus of the memory device according to the present invention utilizes a small capacity of the first loading memory and the second loading memory, thereby greatly improving the test efficiency while reducing the cost compared to the test apparatus of the conventional memory device. Can be.

Fourth, the test apparatus of the memory device according to the present invention operates in one of the modes of single, double, multiple according to the number of test data used, so that the memory device with an optimal test time according to the type and test type of the memory device You can test it.

Hereinafter, a test method and an apparatus of a memory device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a functional block diagram illustrating a test apparatus of a memory device according to an embodiment of the present invention.

Referring to FIG. 3, a test apparatus for a memory device according to the present invention includes a main unit 10, a storage unit 20 storing various types of test data used to test various types of memory devices, and test data. The control unit 30 controls the loading of the test data and the generation of the test pattern signal, the loading memory 40, 50 for loading test data under the control of the control unit 30 or outputting the loaded test data, and the loading memory 40, 50. And a pattern signal generator 60 for generating a test pattern signal using the test data output from The test pattern signal generated by the pattern signal generator 60 is output to the memory device DUT 70 to be tested, and the test result signal output from the memory device 70 is main through the pattern signal generator 60. Is sent to the computer 10. The main computer 10 compares the test pattern signal with the test result signal to test whether the memory device 70 is broken.

Referring to the test apparatus of the memory device according to the present invention in more detail, a user command for selecting a type and a test type of a memory device to be tested with the main computer 10 or a user command for selecting a test mode is input. When a user command for selecting the type of memory device and the test type is input, the main computer 10 determines a test mode mapped to the type of device and the test type. Preferably, the test mode is divided into a single mode using one test data, a dual mode using two test data, and a multiple mode using three or more test data. The main computer 10 determines the types of test data used and the order of use of the test data according to the test mode, and transmits the information about the type and the order of use of the determined test data to the controller 30.

The control unit 30 includes a pattern signal control unit 31 and a loading control unit 35. The loading control unit 35 extracts test data used in the test mode determined from the plurality of test data stored in the storage unit 20 using information on the type and use order of the test data, and uses the test data. The test data extracted to the first loading memory 40 and the second loading memory 50 are alternately or sequentially loaded in order. Meanwhile, the pattern signal controller 31 output-controls the test data stored in the first loading memory 40 or the second loading memory 50 to the pattern signal generator 60 according to the test mode. The pattern signal generator 60 receives test data output from the first loading memory 40 or the second loading memory 50, generates a test pattern signal, and generates a test pattern signal, and a memory device to test the generated test pattern signal ( 70)

4 is a flowchart illustrating a test method of a memory device according to an exemplary embodiment of the present invention, and FIG. 5 illustrates control of loading of test data and generation of a test pattern signal when the multi-mode is determined in the test method of a memory device according to the present invention. A flowchart for explaining the control.

Referring to FIG. 3 to FIG. 5, a method of testing a memory device according to an embodiment of the present invention will be described in detail. When a user command for selecting a test mode is input from the main computer 10 (S11), The test mode is determined according to the user command, and the type of test data used in the determined test mode and the order of using the test data are determined (S12). The user command entered includes the type of memory device, the type of test, and the test mode. When the test mode is determined in step S12, the test data is loaded into the first loading memory 40 or the second loading memory 50 according to the determined test mode, and the first loading memory 40 or the second loading memory 50 is loaded. The test pattern signal is generated according to the test data output from

First, referring to step S13 to step S15, the loading control of the test data and the control of the generation of the test pattern signal in the single mode will be described in detail. Since only one test data is used in the single mode, the loading control unit 35 performs the first loading. One test data used in the memory 40 is loaded (S13). The pattern signal controller 31 provides the test data stored in the first loading memory 31 to the pattern signal generator 60 to generate a test pattern signal (S14). The pattern signal controller 31 determines whether the test of the memory device 70 is completed after providing the test data to the pattern signal generator 60 (S15). If the test of the memory device is not completed, the steps S13 to S15 are repeated.

Meanwhile, referring to steps S16 to S19, the loading control of the test data and the generation control of the test pattern signal in the dual mode will be described in detail. Since the dual mode uses the two test data, the loading control unit 35 performs the first loading. The first test data of the two test data is loaded into the memory 40 (S16), and the second test data of the two test data is loaded into the second loading memory 50 (S17). The pattern signal controller 31 alternately patterns the first test data stored in the first loading memory 40 and the second test data stored in the second loading memory 50 in an alternating order or in the order of use of the test data. Provided to the signal generator 60 to generate a test pattern signal. The pattern signal controller 31 determines whether the test of the memory device 70 is completed after providing the first test data or the second test data to the pattern signal generator 60 (S19). If the test of the memory device is not completed, the steps S16 to S19 are repeated.

Meanwhile, referring to FIG. 5 (a), when a test mode is determined as a multi mode, an example of a method of controlling loading of test data and a control method of generating test data will be described in more detail. As a result, the loading control unit 35 alternately loads three or more pieces of test data used for the test of the memory device into the first loading memory 40 and the second loading memory 50 (S21). The pattern control unit 31 provides the test data stored in the first loading memory 40 and the test data stored in the second loading memory 50 to the pattern signal generation unit 60 alternately or in order of using the test data. The main computer 10 determines whether the test of the memory device 70 is completed based on the type of memory device and the test mode (S25), and the pattern signal controller 31 and the loading controller 35 determine the memory device 70. Repeat step S21 to step S25 until the test of) is completed.

For example, in the multi-mode in which three test data (first test data, second test data, and third test data) are used, the loading control unit 35 may include the first test data and the first test data among the three test data. 2 Test data is loaded into the first loading memory 40 and the second loading memory 50, respectively. The pattern signal controller 31 provides the first test data stored in the first loading memory 40 to the pattern signal generator 60. The loading control unit 35 loads the third test data into the first loading memory 40 while the pattern signal generation unit 60 generates the first test pattern signal according to the first test data. When the first test pattern signal is generated, the pattern signal controller 31 provides the second test data stored in the second loading memory 50 to the pattern signal generator 60. The loading controller 35 loads the first test data back into the second loading memory 40 while the pattern signal generator 31 generates the second test pattern signal according to the second test data. That is, until the test of the memory device 70 is completed, the loading control unit 35 alternately loads the first test data and the third test data into the first loading memory 40 and the second loading memory 50. The pattern signal controller 31 alternately generates test signals stored in the first loading memory 40 or the second loading memory 50 each time a test pattern signal is generated by the pattern signal generator 60. Provided to the unit 60 to control to generate a test pattern signal.

 Referring to FIG. 5B, when the test mode is determined as the multi-mode, another example of a method of controlling test data loading and generation of test data will be described in more detail. The loading controller 35 may include a memory device 70. Load a plurality of test data used for the test of the first loading memory 40 in sequence (S31), and stores the test data loaded in the first loading memory 40 to the second loading memory 50 ( S33). The loading control unit 35 loads a plurality of test data into the first loading memory 40 in order each time the test data stored in the first loading memory 40 is moved to and stored in the second loading memory 50. The pattern signal controller 31 sequentially provides the test data stored in the second loading memory 50 to the pattern signal generator 60 to generate a test pattern signal (S35). The main computer 10 determines whether the test of the memory device 70 is completed based on the type of memory device and the test mode (S37), and the pattern signal controller 31 and the loading controller 35 determine the memory device 70. Repeat steps S31 to S27 until the test of) is completed.

For example, in the multi-mode in which three test data (first test data, second test data, and third test data) are used, the loading control unit 35 may include the first test data and the second test data among the three test data. Test data is sequentially loaded into the first loading memory 40. The first test data stored in the first loading memory 40 is moved and stored in the second loading memory 50 when the second test data is loaded into the first loading memory 40. The pattern signal controller 31 provides the first test data stored in the second loading memory 50 to the pattern signal generator 60. When the first test data is provided to the pattern signal generator 60, the loading controller 35 loads the third test data into the first loading memory 40 and stores the first test data stored in the first loading memory 40. The two test data are moved and stored in the second loading memory 50. The pattern signal controller 31 provides the second test data stored in the second loading memory 50 to the pattern signal generator 60. When the second test data is provided to the pattern signal generator 60, the loading controller 35 loads the first test data into the first loading memory 40 again and is stored in the first loading memory 40. The third test data which has been transferred is stored in the second loading memory 50. The pattern signal controller 31 provides the third test data stored in the second loading memory 50 to the pattern signal generator 60. That is, until the test of the memory device 70 is completed, the loading control unit 35 sequentially loads a plurality of test data into the first loading memory 40, and the new test data is loaded into the first loading memory 40. Each time it is loaded, the test data stored in the first loading memory 40 is transferred to the second loading memory 50. The pattern signal controller 31 generates the test pattern signal by providing test data stored in the second loading memory 50 to the pattern signal generator 60 whenever the test pattern signal is generated in the pattern signal generator 60. To control.

 Meanwhile, the above-described embodiments of the present invention can be written as a program that can be executed in a computer, and can be implemented in a general-purpose digital computer that operates the program using a computer-readable recording medium.

The computer readable recording medium may include a magnetic storage medium (eg, a ROM, a floppy disk, a hard disk, etc.), an optical reading medium (eg, a CD-ROM, a DVD, etc.) and a carrier wave (eg, the Internet). Storage medium).

Although the present invention has been described with reference to the embodiment shown in the drawings, this is merely illustrative. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 shows a schematic configuration diagram of a test system of a memory device according to the prior art.

2 shows a flowchart of a test method of a memory device according to the prior art.

3 is a functional block diagram illustrating a test apparatus of a memory device according to an embodiment of the present invention.

4 is a flowchart illustrating a test method of a memory device according to the present invention.

5 is a flowchart illustrating control of loading test data and generating control of a test pattern signal when the multi-mode is determined in the test method of the memory device according to the present invention.

Description of the main parts of the drawing

1, 10: main computer

3: loading memory

5, 60: pattern signal generator

7, 70: DUT

30: control unit 31: pattern signal control unit

35: loading control unit 40: first loading memory

50: second loading memory

Claims (6)

A first loading memory for storing first test data; A second loading memory for storing second test data; A pattern signal generator configured to generate a test pattern signal according to test data input from the first loading memory or the second loading memory; A loading controller configured to control loading of test data into the first loading memory or the second loading memory according to an input mode selection command of the user; And A pattern signal controller configured to provide test data stored in the first loading memory or the second loading memory to the pattern signal generator according to the mode selection command, The mode selection command And a single mode using one test data, a dual mode using two test data, and a multiple mode using three or more test data. delete delete The method of claim 1, wherein when the dual mode is selected according to the mode selection command, The loading control unit controls the loading of the first test data and the second test data into the first loading memory and the second loading memory, respectively. The pattern signal controller may alternately provide the first test data and the second test data to the pattern signal generator. The method of claim 1, wherein the multi-mode is selected according to the mode selection command. The loading control unit load-controls three or more pieces of test data to be alternately loaded into the first loading memory and the second loading memory, And the pattern signal controller provides the test data stored in the first loading memory and the second loading memory to the pattern signal generator alternately or in order of using the test data. The method of claim 1, wherein the multi-mode is selected according to the mode selection command. The loading control unit load-controls three or more pieces of test data to be used in the first loading memory in order, moves and stores the test data stored in the first loading memory into the second loading memory, And the pattern signal controller provides test data stored in the second loading memory to the pattern signal generator.

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