JP2002005996A - Testing method and storage medium storing testing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a testing time for a semiconductor device by means of a tester and to lower a testing cost for the semiconductor device. SOLUTION: For each testing item on the semiconductor device, setting processes for respectively setting a voltage, an input/output level, and a plurality of measurement patterns are combined mutually for setting a testing condition, power is turned on, testing and result determination is carried out for a plurality of measurement patterns, and then, the power is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a test method.
In particular, the present invention relates to a test method for testing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a test method of this type is used for performing a test on a semiconductor device for each test item, determining pass / fail, and classifying a non-defective product or a defective product. The program is read by a computer-configured tester and executed. For example, FIG. 2 is a flowchart showing a processing procedure of a conventional test method.

Referring to FIG. 2, this conventional test method includes processing of a plurality of test items 1 to N. Each of the test items 1 to N is performed by processing a tester instruction executed by a tester having a computer configuration. Each is configured and includes a test condition setting unit and processes of power-on, test execution, result determination, and power-off.

The test condition setting section includes a process for setting a voltage, a waveform logic, a timing, an input / output level, and a measurement pattern, and sets a test condition by combining these processes. Each of these processes is executed by a tester instruction. Here, the tester instruction for setting the voltage sets the voltage of a power supply or the like supplied to the semiconductor device, and the tester instruction for setting the waveform logic sets the input / output pulse waveform of the semiconductor device and sets the timing. The tester command sets the change timing of the input / output waveform of the semiconductor device, the tester command sets the input / output level, the high / low level of the input / output waveform of the semiconductor device, and the tester command sets the measurement pattern. A measurement pattern is set which indicates the time series change of the input signal of the device and the time series change of the expected value with respect to the output signal in a pattern of 1 or 0.

The power-on process is executed by a tester instruction, performs the process at the time of power-on before the test is executed, and is required when the voltage or input / output level supplied to the semiconductor device changes. The test execution process is executed according to a tester instruction, applies an input signal under the test condition set by the test condition setting unit, compares the output signal with an expected value, and executes the test. The result determination process is executed by a tester instruction, and performs a pass / fail determination of the test execution result.
The power-off process is executed by a tester instruction, performs a power-off process after test execution, and is required when a voltage or input / output level supplied to the semiconductor device changes.

In this conventional test method, unless a failure is determined in the processing of each of the test items 1 to N, tests are sequentially performed in the processing of each of the test items 1 to N. When the pass is determined, the non-defective product is finally determined and classified, and the defective product is classified according to each of the test items 1 to N for which the failure is determined.

[0007]

Conventionally, since the test cost incurred when testing a semiconductor device is proportional to the test time per semiconductor device, efforts have always been made to reduce the test time.

However, since the operation of the semiconductor device has become higher in frequency at present, the power-on test performed by each test item in the tester used is longer than the processing time of the test execution in which the semiconductor device is actually operating. , The processing time for power-off and the processing time for setting the voltage, waveform logic, input / output level, timing, and measurement pattern are longer, making it difficult to reduce the test time.

Accordingly, it is an object of the present invention to reduce the test time of a semiconductor device by a tester and reduce the cost of testing the semiconductor device.

[0010]

Therefore, a test method according to the present invention provides a method for measuring a voltage,
A test condition is set by combining processes for setting an input / output level and a plurality of measurement patterns, a power is turned on, a test is executed for the plurality of measurement patterns, a result is determined, and a power is turned off.

The present invention also sets a test condition by combining a process for setting a voltage, an input / output level, and a measurement pattern for each test item of a semiconductor device, and performs power-on, test execution, result determination, and power-off, respectively. In a test method to be performed, the measurement pattern includes a plurality of measurement patterns, and a test is executed and a result is determined for the plurality of measurement patterns.

Further, classification is performed by a result judgment corresponding to each of the plurality of measurement patterns.

[0013] Further, the recording medium on which the test program of the present invention is recorded is provided for each test item of the semiconductor device.
A process of setting a test condition by combining a process of setting a voltage, an input / output level, and a plurality of measurement patterns, performing power-on, executing a test on the plurality of measurement patterns, determining a result, and performing power-off. Is executed by a computer-configured tester.

According to the present invention, a test condition is set by combining a process for setting a voltage, an input / output level, and a measurement pattern for each test item of a semiconductor device, and power-on, test execution, result judgment, and power-off are respectively performed. In a recording medium on which a test program for causing a computer-configured tester to execute processing to be performed is recorded, the measurement pattern includes a plurality of measurement patterns, and the test execution and the result determination are performed on the plurality of measurement patterns.

Further, the classification is performed by judging the result corresponding to each of the plurality of measurement patterns.

[0016]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing an embodiment of the test method of the present invention.

Referring to FIG. 1, the test method according to the present embodiment includes processing of a plurality of test items 1 to M. The processing of each of the test items 1 to M is the processing of a tester instruction executed by a tester having a computer configuration. Respectively, and includes a test condition setting unit and processes of power-on, test execution, result determination, and power-off, respectively.

The test condition setting unit includes a process for setting a voltage, a waveform logic, a timing, an input / output level, and a plurality of measurement patterns, respectively, and sets a test condition by combining these processes. Each of these processes is executed by a tester instruction. The test condition setting unit in the test method of the present embodiment differs from the conventional method in that the test condition setting unit includes a process of setting a plurality of measurement patterns. Except for this difference, the configuration is the same as the conventional one, and therefore, the duplicate description will be omitted.

The power-on process is executed by a tester command as in the prior art, performs the power-on process before the test is executed, and is required when the voltage or input / output level supplied to the semiconductor device changes.

The test execution process is executed by a tester instruction as in the prior art, and an input signal is applied under the test conditions set by the test condition setting unit, and the output signal is compared with an expected value to execute the test. At this time, in the test method of the present embodiment, a test is executed for each of the plurality of measurement patterns set by the test condition setting unit.

The result determination process is executed by a tester instruction as in the prior art, and a pass / fail determination is made on the test execution result. At this time, pass / fail judgment is performed for each of the plurality of measurement patterns set by the test condition setting unit.

The power-off process is executed by a tester instruction, as in the prior art. The power-off process is performed after the test is executed, and is required when the voltage or input / output level supplied to the semiconductor device changes.

As described above, in the test method of the present embodiment, the test conditions are set by combining the processes of setting the voltage, the input / output level, and the plurality of measurement patterns in each of the test items 1 to M, Performs power-on, executes tests for multiple measurement patterns, determines the results,
Power off and, as with the traditional test method,
Unless a fail determination is made in the processing of each of the test items 1 to M, the test is performed in order in the processing of each of the test items 1 to M, and when a pass determination is made for all the test items 1 to M, finally, It is judged as good and classified.
Defective products are classified according to each of the test items 1 to N for which a fail determination has been made.

In the test method of the present embodiment, a single test item can be used to test a plurality of measurement patterns, eliminating the need for testing with a plurality of test items unlike the conventional test method. The number is reduced by a factor. For this reason, the number of power-on and power-off processes before and after the test, which performs the processes required when the voltage and input / output levels change in each test item, is also reduced to a multiple of one. Test time is also reduced.

For example, in a memory product having a 1M × 1 bit configuration, “0” write, “0” read, “1” write, and “1” read for all cells are performed in an operation cycle of 5 ns.
Execution time is 5 ns × 1M × 4 times = 20 m
s. Also, the processing time of the test condition setting unit is set to 100
ms, the total processing time of power-on and power-off is 20 ms, two kinds of measurement voltages, and two input / output levels.
Type, two types of input timing, two types of waveform logic,
When testing four types of measurement patterns, the number of required test items is 2 × 2 × 2 ×
2 × 4 = 64. The total test time excluding the result determination time is (100 ms + 20 ms + 20 ms) × 64 times = 8.96 s. On the other hand, in the test method of the present embodiment, the number of necessary test items is 2 × 2 × 2 × 2 = 16, and the total test time excluding the result determination time is (10).
0 ms + 20 ms + 20 ms × 4) × 16 times = 3.2 s
Becomes

As a modification of the test method of the present embodiment, a test method in which a process for performing classification by result determination corresponding to each of a plurality of measurement patterns is added is also possible. Fail locations can be limited as in the conventional test method, and defective products are classified.

[0027]

As described above, the test method according to the present invention has the effects of shortening the test time of the semiconductor device by the tester and reducing the test cost of the semiconductor device.

The reason is that a single test item can be used to test a plurality of measurement patterns, and it is not necessary to perform a test with a plurality of test items as in the conventional test method. And the number of power-on and power-off processes before and after the test, which performs the processes required when the voltage and input / output levels change in each test item, are also reduced to a multiple. That's why.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of a test method of the present invention.

FIG. 2 is a flowchart showing an example of a procedure of a conventional test method.

Claims (6)

[Claims] 1. A test condition is set by combining a process for setting a voltage, an input / output level, and a plurality of measurement patterns for each test item of a semiconductor device, and power-on is performed. A test method that performs test execution, results judgment, and power off. 2. A test method in which a test condition is set by combining processes for setting a voltage, an input / output level, and a measurement pattern for each test item of a semiconductor device, and power-on, test execution, result determination, and power-off are performed. A test method, wherein the measurement pattern comprises a plurality of measurement patterns, and a test execution and a result determination are performed on the plurality of measurement patterns. 3. The test method according to claim 1, wherein the classification is performed by a result judgment corresponding to each of the plurality of measurement patterns. 4. A test condition is set by combining a process for setting a voltage, an input / output level, and a plurality of measurement patterns for each test item of a semiconductor device, and power-on is performed. A recording medium that records a test program that causes a computer-configured tester to execute a test, determine a result, and execute a power-off process. 5. A computer for performing a process of setting a test condition by combining a process of setting a voltage, an input / output level, and a measurement pattern for each test item of a semiconductor device and performing power-on, test execution, result determination, and power-off, respectively. In a recording medium on which a test program to be executed by a tester having a configuration is recorded, the measurement pattern includes a plurality of measurement patterns, and a test execution and a result determination are performed on the plurality of measurement patterns. A recording medium on which a program is recorded. 6. The recording medium according to claim 4, wherein the classification is performed by a result judgment corresponding to each of the plurality of measurement patterns.