JPH11174126A - Self-inspection pattern generation device for incorporation in logic circuit and pattern selection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an self-inspection for incorporation of all elements in circuit to be inspected quickly, by a circuit with a scale that is required at the minimum for a logic circuit that is subjected to scan path design. SOLUTION: An auxiliary pattern storage memory 116 is provided in addition to a random number generation circuit 102 as a circuit for generating a pattern for inspecting a logic circuit block 103 in the same semiconductor integrated circuit 101, first, the pattern being generated by the random number generation circuit is applied to each scan chain 105 of the circuit 103 to be inspected, and the pattern being stored is read from the memory 116 after the generation of a random number is completed and is applied to a scan chain 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-inspection pattern generator and a pattern selection method incorporating a logic circuit, and more particularly, to a failure inspection for all elements in a circuit to be inspected by incorporating an inspection circuit in a semiconductor circuit. The present invention relates to a built-in self-inspection pattern generation device for a logic circuit to be performed and a pattern selection method.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional built-in self-test pattern generator for a logic circuit having a scan path and a scan path. In FIG. 3, reference numeral 501 denotes a semiconductor integrated circuit, 503 denotes a logic circuit block designed as a scan path to be inspected, and 502
Is a random number generation circuit that generates a random number pattern for the circuit under test, 509 is an output pattern compression circuit that compresses a pattern output from the circuit under test, 511 is an expected value holding register, 510 is an output pattern compression circuit 509 and holds An output comparison circuit for comparing the obtained expected value and outputting a pass / fail result signal 512.

Here, the relationship between the logic circuit block 503 and the random number generation circuit 502 in FIG. 5 will be described in detail. Generally, a logic circuit block 5 incorporating a scan chain 505 composed of scan flip-flops 504
In the case of performing a failure test on the semiconductor device 03 using a self-inspection circuit device incorporated in the semiconductor integrated circuit 501, the structure in the logic circuit block 503 does not have the regularity of a memory block. It is necessary to apply a pattern to the flip-flop 504 such that all combinations occur.

Therefore, as one method, a random number generation circuit using a linear feedback shift register 514 composed of registers 513 of the total number of stages of all the scan flip-flops 504 in the logic circuit block 503 to be inspected. 502 to a logic circuit block 503
By controlling the selector 508 with the switching signal 507 using the pattern generated by each register 513 by the random number generation circuit 502 during the built-in self test, the scan on the scan chain 505 is designed inside the same semiconductor integrated circuit 501 as By shifting into the flip-flop 504, the states of all combinations are set in the scan flip-flop 504 in the logic circuit block 503. 506 is a scan input signal, 515
Is an exclusive OR gate.

[0005]

However, in this conventional pattern generator for generating all combinations, 2 ⁿ (2 n) patterns are required for a circuit under test having n flip-flops. And the number of patterns to be generated increases exponentially with respect to the number of flip-flops, and as the pattern generation progresses, patterns without the ability to detect undetected faults gradually and frequently occur. The problem is that the pattern generation time is very long for blocks with a large number of inputs, and the generated patterns are wasteful.
In addition, there is a problem that the built-in self-inspection pattern generation device becomes large, and it is not practically practical.

On the other hand, in order to reduce the pattern generation time and the circuit area, the linear feedback shift register 514 for generating a random number pattern for each scan chain is divided and configured as a register 51.
If the number 3 is smaller than the number of flip-flops 504 on each scan chain 505 and the number is set to m smaller than n, the number becomes 2 ^m (2 m), which is smaller than the reduction rate of the number of registers. Although the number of combinations of patterns to be performed rapidly decreases, the number of combinations of states that can be set in the scan flip-flop 504 also rapidly decreases, so that even if all the combination patterns are generated, a failure that is not controlled at all is generated. To increase. That is, since a sufficient failure detection rate cannot be reached, even if a failure has occurred in the target block circuit, it may be overlooked.

The present invention solves such a problem and provides a memory for storing patterns in addition to a random number generation circuit inside a semiconductor integrated circuit including a circuit to be inspected, so that it cannot be set by the random number generation circuit. It is an object of the present invention to provide a built-in self-test pattern generator of a logic circuit capable of performing a fault test on all elements in a circuit under test in a relatively short time by additionally generating a pattern.

Another object of the present invention is to provide a method of selecting a built-in self-test pattern of a logic circuit which can reduce the capacity of a pattern storage memory.

[0009]

According to a first aspect of the present invention, there is provided a logic circuit built-in self-test pattern generating apparatus for generating a pattern for self-testing a scan path-designed logic circuit block by the built-in circuit. A built-in self-test pattern generation device, comprising: a random number generation circuit for generating a random number pattern for testing a circuit under test; an auxiliary pattern storage memory storing a pattern for testing the circuit under test; A selection circuit for switching the output of the auxiliary pattern storage memory and inputting the output to the circuit to be inspected.

According to the built-in self-inspection pattern generation device for a logic circuit according to the first aspect of the present invention,
A pattern for detecting a failure that cannot be detected by the pattern generated by the random number generation circuit is stored in the auxiliary pattern storage memory, and the pattern generated by the random number generation circuit is first applied to each input of the circuit under test, and the random number is generated. After one cycle of generation of the pattern, the stored pattern is read out from the auxiliary pattern storage memory and applied to the input of the circuit under test.
As a result, the presence of the auxiliary pattern storage memory for storing the pattern allows the random number generation circuit to be configured with a linear feedback shift register having a smaller number of stages than the number of scan flip-flops, and targets all elements in the circuit under test. This makes it possible to perform a failure inspection using a pattern generator with a minimum necessary circuit scale, and to perform a failure inspection on all elements in the circuit under test in a short time. In addition, it is possible to reduce the time for generating a pattern generated in the entire pattern generator.

According to a second aspect of the present invention, there is provided a method of selecting a built-in self-test pattern for a logic circuit, the method including selecting a pattern to be stored in an auxiliary pattern storage memory constituting the built-in self-test pattern generating apparatus for a logic circuit. First, a failure simulation is performed on the circuit under test using a pattern generated by the random number generation circuit, a pattern capable of detecting an undetected failure in the failure simulation is generated, and the pattern is stored in an auxiliary pattern storage memory. It is characterized in that the data is replaced with data.

According to the method for selecting a built-in self-test pattern for a logic circuit according to the second aspect, a pattern having a high fault detection effect is selected using an automatic test pattern generation means, and only the pattern is stored in an auxiliary pattern storage memory. It is possible to minimize the required capacity of the auxiliary pattern storage memory.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. As a premise of the technology to be implemented by the present invention, a circuit to be inspected includes:
It is assumed that the logic circuit is a scan path-designed logic circuit having a built-in scan chain.

FIG. 1 shows an embodiment of the present invention.
FIG. 3 is a circuit diagram showing a built-in self-test pattern generation device for a logic circuit designed for a scan path. Note that scan path design is one of design techniques for facilitating fault inspection of a logic circuit. A flip-flop included in the logic circuit is passed through a dedicated test path (this is called a scan chain). This is a design method that enables control and observation.

In FIG. 1, reference numeral 101 denotes a semiconductor integrated circuit;
Reference numeral 103 denotes a logic circuit block designed to be a scan path to be inspected, 102 denotes a random number generation circuit that generates a random number pattern for the circuit to be inspected, 116 denotes an auxiliary pattern storage memory in which a pattern for the circuit to be inspected is stored in advance, 108 Is the logic circuit block 10 during the built-in self-test.
A selector, which is a selection circuit for selecting and controlling whether to use the pattern generated by the random number generation circuit 102 or the pattern stored in the auxiliary pattern storage memory 116 for the circuit No. 3, an output 109 from the circuit under test An output pattern compression circuit for compressing the pattern to be output, an expected value holding register 111, and an output comparison circuit 110 for comparing the output pattern compression circuit 109 with the held expected value and outputting a pass / fail result signal 112.

Logic circuit block 103 which is a circuit to be inspected
Are designed in the semiconductor integrated circuit 101 including the random number generation circuit 102, the auxiliary pattern storage memory 116, and the selector 108 for selecting and controlling them. The logic circuit block 103 is usually input from the outside or from another block, but at the time of self-test, a pattern is generated by the random number generation circuit 102 and the logic circuit block 103 is generated.
, Or a pattern that cannot be generated from the random number generation circuit 102 is read out from the auxiliary pattern storage memory 116 which has been stored in advance and input to the logic circuit block 103. The random number generation circuit 102 calculates 2 ^m (2) regardless of the total number of the scan flip-flops 104 in the logic circuit block 103.
(M raised to the power of m) is determined so that the number of patterns can sufficiently fall within the allowable total test time, and the random number generation circuit 102 is constituted by a linear feedback shift register 114 in which m is the number of registers 113. And design. The auxiliary pattern storage memory 116 stores the scan chain 10
The number of bits corresponds to the total number of 5 and has the same number of memory output lines 118 as the total number. Memory control signal 117
, The output value of the address counter 119 changes by one, and by changing the address for reading and accessing the auxiliary pattern storage memory 116 by one, the read value changes one after another. The auxiliary pattern storage memory 116 stores data to be shifted into the scan chain 105 by one clock signal for each address. Therefore, the auxiliary pattern storage memory 116 has addresses of the total number of clocks necessary to shift in the scan flip-flop 104 through the scan chain 105.

Next, when the built-in self-test is performed on the logic circuit block 103, first, the selector 108 is controlled by the switching signal 107, so that the random number generation circuit 102 is used as the self-test generation pattern generation circuit. The scan flip-flop 10 on the scan chain 105 selects the pattern generated by the random number generation circuit 102.
4, the scan flip-flop 1 connected to the scan chain 105 in the logic circuit block 103 is sequentially shifted in for each scan chain 105.
Then, a scan path test is performed by using the scan path test 04. When the state of all the combinations that can be generated by the random number generation circuit 102 is set for the scan flip-flop 104,
Next, by controlling the selector 108 with the switching signal 107, the auxiliary pattern storage memory 116 is selected as a self test generation pattern generation circuit, and the patterns stored in advance in the auxiliary pattern storage memory 116 are sequentially read and the scan chain is generated. By sequentially shifting in the scan flip-flops 104 on the scan chain 105 for each scan chain 105, the logic circuit block 10
In 3, a scan path test is performed using the scan flip-flop 104 connected to the scan chain 105. Reference numeral 106 denotes a scan input signal, and 115 denotes an exclusive OR gate.

FIG. 2 is a flowchart showing a processing procedure for selecting a test pattern to be stored in the auxiliary pattern storage memory 116 in FIG. The part of the random number generation circuit 102 and the logic circuit block 103 shown in FIG. 1 are directly connected without the intervention of the selector 108, and the output pattern compression circuit 109, the output comparison circuit 110, the expected value holding register 1
11 are added to each other to create a logic circuit model 201 having the pass / fail result signal 112 as an output terminal, and using the fault definition means 202 for all signal lines in the circuit under test in the logic circuit model 201 And outputs it to the simulation target failure list 203.

An output signal is observed in the pass / fail result signal 112, and a failure simulation is performed by the failure simulation means 205 using the clock signal 204 for shifting the linear feedback shift register 114 included in the random number generation circuit 102. Execute in order. At the initial time, all faults included in the current simulation target fault list 203 are set in the logic circuit model, a clock signal is input once, and the normal value and the influence of the fault are propagated. When the time for observing the output from the logic circuit model at the observation point set in the logic circuit model has been reached, a list of undetected faults that classify faults that are not likely to be detected at that observation point is created. Each cycle is repeated by setting it as the simulation target failure list 203 in the next cycle. When the pattern generated by the random number generation circuit makes a round, the simulation target fault list 203 at that time is output as final undetected fault information 206 in the random number generation pattern.

Next, a logic circuit model 207 corresponding to the portion of the logic circuit block 103 of FIG. 1 is created, and is included in the undetected fault information 206 by a test pattern automatic generation means 208 realized on a computer. A pattern for detecting each fault is determined. This process is performed until the required failure detection rate is satisfied in the logic circuit block, and an auxiliary pattern table 209 in which signal values to be shifted into each scan chain 105 are arranged in time order is created. The arrangement of signal values at one time in the auxiliary pattern table 209 is assigned to each address and stored in the auxiliary pattern storage memory 116 in FIG.

Table 1 is an example of an auxiliary pattern table.

[0022]

[Table 1]

In this example, three scan chains 105 existing in the logic circuit block 103 to be inspected are used.
, The state of each of the five scan flip-flops 104 is set. The input terminals a of the three scan chains 105 in the logic circuit block,
For b and c, at time T1, a = 1, b = 0, c =
0, a pattern giving an input signal value such as a = 0, b = 1, c = 0 at time T2. Time T1, T
2, T3, T4, and T5, the input terminals a,
The test data entered from b and c is the scan chain 10
5 is shifted by one scan flip-flop 104, and such a shift-in operation is continuously performed for five clocks. Next, at time T6, the scan flip-flop 104 performs an operation of sending normal data from the input to the output in synchronization with the clock. At time T6,
Since the shift-in operation to the scan chain 105 is not performed, the input terminals a,
Since the value to be put in b and c may be 0 or 1, it is described as “×”. The same applies to times T7 to T12.

Table 2 explains the storage contents of the auxiliary pattern storage memory 116 corresponding to the contents of the auxiliary pattern table of Table 1.

[0025]

[Table 2]

Each bit of the auxiliary pattern storage memory 116 corresponds to each scan chain 105, and each address corresponds to a time from the head. The input signal values of the input terminals a, b, and c at the time of shift-in are assigned to the first bit, the second bit, and the third bit, respectively.
Corresponding to the times 1, T2, and T3, they are stored in the auxiliary pattern storage memory 116 in order of time, such as a first address, a second address, a third address, and so on.

[0027]

According to the built-in self-test pattern generation device for a logic circuit according to the first aspect, a pattern for detecting a failure that cannot be detected by the pattern generated by the random number generation circuit is stored in the semiconductor circuit as the auxiliary pattern. First, the pattern generated by the random number generation circuit is applied to each input of the circuit under test, and after the generation of the random number has completed one cycle, the stored pattern is read out from the auxiliary pattern storage memory. Applied to the input of the circuit under test. As a result, the presence of the auxiliary pattern storage memory for storing the pattern allows the random number generation circuit to be configured with a linear feedback shift register having a smaller number of stages than the number of scan flip-flops, and targets all elements in the circuit under test. This makes it possible to perform a failure inspection using a pattern generator with a minimum necessary circuit scale, and to perform a failure inspection on all elements in the circuit under test in a short time. In addition, it is possible to reduce the time for generating a pattern generated in the entire pattern generator.

According to the method for selecting a built-in self-test pattern of a logic circuit according to the second aspect, a pattern having a high fault detection effect is selected by using an automatic test pattern generating means, and only the pattern is stored in an auxiliary pattern storage memory. It is possible to minimize the required capacity of the auxiliary pattern storage memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a built-in self-test pattern generation device for a logic circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure for selecting a test pattern to be stored in an auxiliary pattern storage memory of FIG.

FIG. 3 is a block diagram showing a configuration of a conventional built-in self-test pattern generation device for a logic circuit.

[Explanation of symbols]

 Reference Signs List 101 semiconductor integrated circuit 102 random number generation circuit 103 logic circuit block 104 scan flip-flop 105 scan chain 106 scan input signal 107 switching signal 108 selector 109 output pattern compression circuit 110 output comparison circuit 111 expected value holding register 112 pass / fail result signal 113 register 114 linear Feedback register 115 Exclusive OR gate 116 Auxiliary pattern storage memory 117 Memory control signal 118 Memory output line 119 Address counter

Claims (2)

[Claims] 1. A built-in self-test pattern generator for a logic circuit for generating a pattern for self-testing a scan path-designed logic circuit block by a built-in circuit, comprising a random number pattern for testing a circuit under test. , An auxiliary pattern storage memory storing a pattern for inspecting the circuit under test, and a selection of switching the outputs of the random number generation circuit and the auxiliary pattern storage memory to input to the circuit under test. Self-inspection pattern generator for a built-in logic circuit having a circuit. 2. A method for selecting a pattern to be stored in an auxiliary pattern storage memory constituting a built-in self-inspection pattern generation device for a logic circuit according to claim 1, wherein the pattern is first selected by a pattern generated by a random number generation circuit. Performing a failure simulation on a test circuit, generating a pattern capable of detecting an undetected failure in the failure simulation, and replacing the pattern with data stored in the auxiliary pattern storage memory; Self-test pattern selection method.