JP2007172778A - Memory test circuit and memory test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory test circuit and a memory test method capable of easily obtaining a state of defect and collecting all defect information even with a small capacity of memory for storing the defect information. <P>SOLUTION: The memory test circuit constitutes a part of a test pattern, executes the test to a memory 2 according to a pattern mode signal for specifying the partial pattern consisting of a plurality of operation and stores the pattern mode signal in a defect information storing register 17 as the part of the defect information. Moreover, the device is equipped with a storage determination circuit 16 for determining if the defect information is stored or not in the defect information storing register 17, according to the information on the preset defect information storing method. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory test circuit and a memory test method, and more particularly to a test circuit and a test method for detecting a defective portion of a memory.

  In recent years, with the increase in scale of system LSIs, the capacity of built-in memories has been increased and the number of bits has been increased, and the number of mounted memories has also increased. As a test method for this memory, BIST (built-in self test) is generally used. The BIST is a method of performing a self test inside an LSI by incorporating a test pattern generation circuit for generating a test pattern to be applied to the test target circuit and a comparison circuit for comparing the data read from the test target circuit with the expected value data. It is. The BIST uses a test pattern generation circuit and an expected value comparison circuit in the LSI to generate a memory test pattern in the LSI, inspects the memory to be tested, and outputs only pass / fail information to the outside. .

  However, the information obtained by a general BIST test method is only information indicating whether or not there is a failure in the memory, and the failure location of the memory cannot be determined. In order to improve the quality of the memory, it is necessary to locate and analyze the failure location and feed back the cause of the failure to the memory manufacturing process. For this reason, there is a need for a technique for obtaining information on a failure location necessary for analyzing a memory failure.

  Japanese Patent Application Laid-Open No. 2004-133867 discloses a technique for detecting a failure location in a memory test. FIG. 1 shows a block diagram of a memory test circuit of Conventional Example 1 disclosed in Patent Document 1. In FIG. Conventional example 1 will be described with reference to FIG.

  A memory test circuit shown in FIG. 1 includes a test memory control circuit 101, a write data generation circuit 102, a memory 103, an expected value generation circuit 104, an expected value comparison circuit 105, a compare register 106, a test item detection circuit 107, and an address register 108. A defective bit detection circuit 109, an FBM (fail bit map) memory control circuit 110, and an FBM memory 111.

  The test memory control circuit 101 performs write control and read control for testing the memory 103. The write data generation circuit 102 generates data to be written to the memory 103 in the memory test. The memory 103 is a test target memory. The expected value generation circuit 104 generates a comparison expected value that matches the output data value output from the memory 103 when the memory test is normal. The expected value comparison circuit 105 compares the comparison expected value with the output data value output from the memory 103. The compare register 106 holds comparison results for all bits compared by the expected value comparison circuit 105. The test item detection circuit 107 detects a test item number in the entire test pattern of the memory test being performed. The address register 108 holds the address of the memory cell that is outputting the output data value being compared by the expected value comparison circuit 105. The defective bit detection circuit 109 detects a bit in which the expected value and the output data value do not match among the comparison results of all the bits held in the compare register 106. The FBM memory control circuit 110 controls a write operation to the FBM memory 111 in which defect information is written. The FBM memory 111 accumulates values output from the test item detection circuit 107, the address register 108, and the defective bit detection circuit 109 as defect information.

  The memory test mode signal TESTMOD and the test start signal MEMRST input from outside the LSI are input to the test memory control circuit 101. The read address signal RADR output from the test memory control circuit 101 is input to the expected value generation circuit 104 and the address register 108. The read control signal RE output from the test memory control circuit 101 is input to the expected value generation circuit 104 and the test item detection circuit 107.

  The test start signal MEMRST is also input to the write data generation circuit 102 and the FBM memory control circuit 110. The write data generation circuit 102 outputs write data WDATA to the memory 103. This write data is input to the memory 103. The test memory control circuit 101 outputs a write address signal WADR, a write control signal WE, a read address signal RADR, and a read control signal RE. These signals are input to the memory 103.

  Read data RDATA output from the memory 103 and expected value data EXDATA output from the expected value generation circuit 104 are input to the expected value comparison circuit 105. The pass / fail judgment signal PASSNG output from the expected value comparison circuit 105 is output outside the LSI. The comparison data COMPDATA output from the expected value comparison circuit 105 is input to the compare register 106. The comparison result data COMPDATA2 output from the compare register 106 is input to the defective bit detection circuit 109. Further, the test interruption signal COMPPNG output from the expected value comparison circuit 105 is input to the test memory control circuit 101 and the FBM memory control circuit 110.

  A memory analysis mode signal DEBGMOD and an analysis result read signal DEBGREAD input from outside the LSI are input to the FBM memory control circuit 110. The FBM memory control circuit 110 outputs an FBM address signal FBMADR, an FBM write control signal FBMWE, and an FBM read control signal FBMRE. These signals are input to the FBM memory 111.

  The FBM memory 111 has three signals: a test item data signal TESTNO output from the test item detection circuit 107, an address data signal FAILADR output from the address register 108, and a defective bit signal FAILBIT output from the defective bit detection circuit 109. Are written as one data signal FBMDATA.

  Here, the memory 103 has a configuration of, for example, 256 addresses and 8 bits. The FBMDATA to be written into the FBM memory 111 has a 14-bit configuration, for example, the 3 bits from the upper bits are the output signal TESTNO of the test item detection circuit 107, the next 8 bits are the output signal FAILADR of the address register 108, and the remaining Three bits are the output signal FAILBIT of the defective bit detection circuit 109.

  If memory cells having a width of 14 bits or more are used as the FBM memory 111, defect information can be stored at a time. The capacity of the FBM memory 111 is determined by the bit width of the memory 103 to be tested and the number of stored defect information. The output of the FBM memory 111 is an FBM read signal FBMOUT output to the outside of the LSI.

  An operation of the memory test circuit shown in FIG. 1 will be described. The memory test mode is set by the memory test mode signal TESTMOD input from the outside of the LSI, and the test memory control circuit 101, the write data generation circuit 102, and the FBM memory control circuit 110 are set by inputting the test start signal MEMRST. Reset. The write data generation circuit 102 starts generating the write data WDATA.

  Subsequently, the test memory control circuit 101 generates a write address signal WADR and a write control signal WE for writing to the memory cell. Write data WDATA is written to the memory 103. When data is written to all addresses, the write address signal WADR and the write control signal WE are stopped.

  Next, the test memory control circuit 101 generates a read control signal RE and a read address signal RADR. In addition, the expected value generation circuit 104 generates expected value data EXDATA corresponding to the read address signal RADR.

  Expected value data EXDATA generated by the expected value generation circuit 104 and read data RDATA read from the memory cell are compared by the expected value comparison circuit 105. Based on the result, the expected value comparison circuit 105 outputs a high level if all bits match, and outputs a low level as a pass / fail judgment signal PASSNG if even one bit does not match. The read address signal RADR is stored in the address register 108 until a comparison result corresponding to the address value is obtained. Further, the test item detection circuit 107 counts the read control signal RE to detect the number of the test read out in the whole test pattern, and in which test item in the whole test pattern the defect has occurred. Information to be determined. The test pattern at that time can be known from the test item.

  Further, when the memory analysis mode signal DEBGMOD input from the outside of the LSI is at a high level and indicates the memory analysis mode, a clock period corresponding to the number of defective bits is detected when the expected value comparison circuit 105 detects a mismatch of the comparison results. Only the test interruption signal COMPPNG becomes high level. In the test memory control circuit 101, reading of the next address is stopped only for a period of one clock less than the period when the test interruption signal COMPPNG is at the high level. That is, if there is a defect of only one bit, it is not stopped, and if there is a defect of 3 bits, it is stopped for two clocks.

  Also, the comparison data COMPDATA for all bits compared by the expected value comparison circuit 105 is held in the compare register 106, and the defective bit detection circuit 109 detects the mismatched bit value, and the test item as one defect information. The number, defective address, and defective bit are simultaneously written in the FBM memory 111. If there is only 1-bit failure in one address, it is only necessary to write it once. However, if there are multiple-bit failures, the failure bit detection circuit 109 sequentially detects the failure bits and writes them to the FBM memory 111 a plurality of times. The FBM memory cell control circuit 110 counts up the FBM address signal FBMADR when the test interruption signal COMPPNG is at a high level.

  When the analysis result read signal DEBAGREAD is set to the high level after the end of all tests, the FBM memory control circuit 110 enters the read mode, and the defect information is read from the FBM memory 111 and output to the FBM read signal FBMOUT.

  On the other hand, Patent Document 2 discloses another example of a technique for detecting a fault location in a memory test. FIG. 2 shows a block diagram of a memory test circuit of Conventional Example 2 disclosed in Patent Document 2. As shown in FIG. A memory test circuit of Conventional Example 2 will be described with reference to FIG.

  The memory test circuit of Conventional Example 2 shown in FIG. 2 includes a memory 201, a memory BIST circuit 202, and a logic scan chain circuit 203. The memory BIST circuit 202 includes an address counter circuit 2021, a data generation circuit 2022, a comparison circuit 2023, and a BIST controller circuit 2024. The logic scan chain circuit 203 includes a plurality of scan register groups 203-1 to 203-n.

  The memory 201 is a memory to be tested. The address counter circuit 2021 generates an address for testing the memory 201. In the memory test, the data generation circuit 2022 generates an expected value for comparison that matches the output data value output from the normal memory. The comparison circuit 2023 compares the expected value for comparison generated by the data generation circuit 2022 with the output data value output from the memory 201. The BIST controller circuit 2024 controls the address counter circuit 2021, the data generation circuit 2022, and the comparison circuit 2023 to generate a memory test pattern.

  The logic scan chain circuit 203 improves the controllability and observability by connecting the flip-flops (F / F) of the circuits of the logic part other than the memory with the wiring 205 in the test mode, and adopting a shift register configuration. It is used in a test method called scan test. The logic scan chain circuit 203 is divided into scan register groups 203-1, 203-2,..., 203-n for each number of F / Fs that can store defect information. The scan register groups 203-1, 203-2,..., 203-n are configured such that data can be shifted in the direction 204 from the scan register group 203-1 to the scan register group 203-2.

  The operation of the memory test circuit of Conventional Example 2 will be described. By making the memory BIST circuit 202 active, the BIST controller circuit 2024 becomes active, and the test of the memory 201 is started. When performing a memory test, the logic scan chain circuit 203 shifts data in the direction 204 from the scan register group 203-1 to the scan register group 203-2.

The comparison circuit 2023 of the memory BIST circuit 202 compares the output data value from the memory 201 and the expected output value from the data generation circuit 2022. When a defect is observed as a result of the comparison, as the defect information, the address value when the defect is detected and the defect determination data value output by the comparison circuit 2023 are taken into the scan register group 203-1. Thereafter, the memory test is continued after observing the defect, and when the next defect is observed, the data taken into the scan register group 203-1 is shifted to the scan register group 203-2 and observed. The defect information is newly taken into the scan register group 203-1. In this way, by fetching defect information into the logic scan chain circuit 203 by a shift operation, a maximum of n pieces of defect information can be fetched. After the memory test is completed, the defect information held in the logic scan chain circuit 203 can be shifted and output from the SDO to the outside, thereby extracting the defect information.
JP 2004-86996 A JP 2002-32998 A

  In Conventional Example 1, a test item number, a defective address, and a defective bit are stored as defect information in the FBM memory 111. For the test item number, the test item detection circuit 107 counts the read control signal RE to detect the number of readings in the entire memory test pattern, and determines which test pattern caused the failure. Information. However, the test patterns for testing the memory 103 are “write“ 0 ”as a data value in order to the memory cells in which the addresses are in ascending order”, “read data from the memory cells so that the addresses are in descending order”. , “Alternately write“ 0 ”and“ 1 ”to memory cells so that addresses are in descending order” ”,“ Read out “0” and “1” alternately to memory cells so that addresses are in ascending order ”” It is configured by combining patterns. Therefore, since the memory test circuit of the conventional example 1 has only information on the number of read data in the entire memory test pattern, it must be compared with the pattern configuration contents of the entire memory test pattern. For example, it is impossible to determine how the memory was operated and tested when a failure occurred. That is, there is a problem in that it is not possible to confirm the state in which a failure has occurred unless the pattern configuration content of the entire memory test pattern is known.

  In Conventional Example 1, defect information is written in the FBM memory 111. However, when a memory having a capacity capable of storing defect information data cannot be prepared, there is a problem that defect information that cannot be collected occurs.

  On the other hand, Conventional Example 2 stores a defective address and a defective bit as defective information. However, there is a problem that it is impossible to know which pattern of the implemented memory test pattern and in what number pattern in the memory test pattern the defect is detected only by this address and defective bit information.

  Further, Conventional Example 2 captures defect information into the logic scan chain circuit 203. Similar to Conventional Example 1, however, there is a problem in that defect information that cannot be collected occurs when the size of the defect information that can be stored is exceeded.

  A memory test circuit according to the present invention is a memory test circuit for testing a memory, and constitutes a part of a test pattern, and the memory test circuit according to a pattern mode signal designating a partial pattern composed of a plurality of operations. The pattern mode signal is stored as part of the defect information. According to the present invention, the pattern mode signal designating the partial pattern is stored as part of the defect information, so that it is possible to easily grasp the state where the defect has occurred.

  Another memory test circuit according to the present invention is a memory test circuit for testing a memory, and includes defect information detection means for detecting defect information of the memory and preset defect information storage method information. And a storage determining means for determining whether or not the defect information detected by the defect information detecting means is stored in the defect information storing means. According to the present invention, since it is determined whether or not the defect information is stored by the defect information storage method information, it is possible to collect all the defect information even if the memory capacity for storing the defect information is small. Become.

  According to the present invention, a memory test circuit and a memory test method capable of easily grasping a state where a defect has occurred and collecting all defect information even if the capacity of a memory for storing defect information is small. Can be provided.

  First, the configuration of the memory test circuit according to the embodiment of the present invention will be described. FIG. 3 shows the configuration of the entire circuit (semiconductor device) including the memory test circuit according to the present embodiment.

  The memory test circuit 1a is a memory test circuit composed of a main defect information collecting circuit and a BIST circuit in the present invention. A memory test start control signal START and a memory test circuit clock signal BISTCLK are input to the memory test circuit 1a via respective terminals from an external tester or the like. The memory test circuit 1b is also a memory test circuit having a configuration similar to that of the memory test circuit 1a, and receives the same signals.

  A memory 2a indicates a memory to be tested. In this embodiment, in order to facilitate understanding, the memory 2a is a 4-address 3-bit memory. The memory 2a receives the write control signal WE, the write address WADR, the write data WDATA, the read control signal RE, and the read address RADR from the memory test circuit 1a, and the read data RDATA is output from the memory 2a to the memory test circuit 1a. . The memory 2b is also a memory having a similar configuration, and the same signals are input / output.

  The test mode register 3a outputs a control signal TESTRST1 that activates the memory test circuit 1a. The test mode register 3a receives the pass / fail determination result signal GO_NOGO1 from the memory test circuit 1a. The test mode register 3a is composed of a shift register, and a value to be set is input from an external terminal TDI. The test mode register 3b has the same configuration as the test mode register 3a, and the same signals are input / output.

  The selectors 4a and 4b are selectors (MUX) that select signals output from the external output terminal TDO. The selectors 4a and 4b respectively output the failure information output signals FBOUT1 and FBOUT2 collected by the memory test circuits 1a and 1b, or the test mode TMOUT1 input to the test mode registers 3a and 3b from the external input terminal TDI. , TMOUT2 is selected to be output.

  The memory test mode control circuit 5 outputs a pattern mode signal MEMTESTMODE instructing which partial pattern of the memory test pattern is to be generated. The pattern mode signal MEMTESTMODE is supplied to the memory test circuits 1a and 1b. In this embodiment, the memory test mode control circuit 5 is constituted by a shift register, and a pattern mode signal value to be set is input from the external terminal TDI. In this embodiment, the pattern mode signal MEMTESTMODE is supplied to the memory test circuit from outside the LSI, but may be generated by the memory test circuit itself.

  In the present embodiment, the memory test is performed by generating the partial pattern shown in FIG. 11 by the memory test circuits 1a and 1b. The partial pattern is a part of the test pattern and includes a plurality of action steps. For example, “0” is sequentially written as a data value for memory cells whose addresses are in ascending order, “data is read from the memory cells so that the addresses are in descending order”, and “addresses are in descending order”. "0" and "1" are alternately written to the memory cell ", and" 0 "and" 1 "are alternately read to the memory cell so that the addresses are in ascending order". It is a collection of steps.

  The pattern mode signal MEMTESTMODE for designating a partial pattern is composed of designated areas of three modes: {address mode, read / write mode, data mode}. The address mode area is an area for designating the address operation of the partial pattern to be generated. The Read / Write mode is an area for designating a partial pattern memory read operation and memory write operation to be generated. The data mode is an area for designating a data value to be written to the memory and an expected value to be generated. Each mode is composed of an arbitrary number of bits. As an example, the address mode is 3 bits, the Read / Write mode is 3 bits, and the data mode is 2 bits. A series of operations by partial patterns corresponds to one mode value.

  For example, when the address mode = “3′b001” is designated, the operation “generates the address value in ascending order from 0” is shown. When the Read / Write mode = “3′b001” is designated, “write data” When the data mode = “2′b00” is specified, the operation “outputs“ 0 ”” is indicated. When these three modes are combined to specify a pattern mode signal MEMTESTMODE = {“001”, “001”, “00”}, a partial pattern representing a series of operations “write data value“ 0 ”in ascending order of address” is displayed. This is the signal to be generated.

  In the present embodiment, a partial pattern as shown in FIG. 11 is generated, and the pattern mode signal MEMTESTMODE for specifying this partial pattern is address mode = 3′b101, read / write mode = 3′b101, data mode = 2′b11. The partial pattern shown in FIG. 11 is based on a 4-address 3-bit memory, and a data value “0” is written in all addresses of the memory before the test based on this partial pattern. Further, in FIG. 11, each of the Pattern-Number (pattern number) represents an operation step, and the partial pattern according to this example is composed of 40 operation steps from 1 to 40. Is executed automatically. In the table, Address indicates a memory address value, Write indicates a write data value, and Read indicates a read data value. Pattern number 2 is a pattern for requesting an operation of writing “111” in the area of address “0” of the memory to be tested.

  When the mode 1, mode 2, and mode 3 shown in FIG. 4 are set in the instruction control circuit 6, the instruction control circuit 6 outputs control signals CONTROL1 and CONTROL2 for operating in accordance with the mode. The control signals CONTROL1 and CONTROL2 are supplied to the selectors 4a and 4b and the memory test circuits 1a and 1b. As shown in FIG. 4, mode 1 is a mode for performing a memory test, mode 2 is a mode for setting a defect storage method, and mode 3 is a mode for outputting defect information.

  The TAP controller 7 is an IEEE Std. This is a state machine having 16 states defined by 1149. A clock signal TCK, a reset signal TRST, and a state transition control signal TMS are externally input via each terminal and controlled. Depending on the state of the TAP controller 7, control signals CLKIR, SFIR, UPDIR, CLKDR, SFDR, and UPDDR output from the TAP controller 7 are supplied to the test configuration circuits 1a, 1b, 3a, 3b, 5, and 6. The TAP controller 7 controls an operation of setting a value from the outside to a defect information storage method designation register 18 described later or outputting defect information from the defect information storage register 17 to the outside.

  As shown in FIG. 3, in order to store the defect information detected from each of the plurality of memories 2a and 2b in the memory test circuits 1a and 1b and output the same to the outside, a signal is input from the outside. That is, a signal flows through a connection line from the outside to the external terminal TDI, the memory test mode control circuit 5, TMCHAIN1, the memory test circuit 1a, FBOUT1, TMCHAIN2, the memory test circuit 1b, FBOUT2, TMCHAIN3, and the external terminal TDO. Is output. The connection line for outputting the defect information is activated by the CONTROL1 signal output in the mode 2 and mode 3 states of FIG. 4 from the instruction control circuit 6 of FIG.

  FIG. 5 shows the internal configuration of the memory test circuits 1a and 1b in FIG. The test control circuit 11 is a circuit that controls generation of a pattern for testing the memory 2 and an expected value. The test control circuit 11 receives a pattern mode signal MEMTESTMODE and a memory test start control signal START that instruct what pattern is to be generated, and outputs a memory test pattern control signal STDATA.

  The test pattern generation circuit 12 generates a write control signal WE, a write address WADR, a write data WDATA, a read control signal RE, and a read address RADR as a memory test pattern based on the control signal STDATA output from the test control circuit 11. Output to 2.

  The expected value generation circuit 13 generates an expected value corresponding to the memory test pattern generated by the test pattern generation circuit 12 based on the control signal STDATA output from the test control circuit 11.

  The expected value comparison circuit 14 compares the data output signal RDATA read from the memory 2 with the expected value EXDATA generated by the expected value generation circuit 13. If the expected values do not match, it is determined as defective and a fail signal (active = 1) is output to the pass / fail signal FAILFLAG.

  The clock counter 151 starts counting from the time when the test pattern output from the test pattern generation circuit 12 starts, and counts up by 1 every time one pattern is output to the memory 2, that is, every operation (one action). The clock counter 151 receives the pass fail signal FAILFLAG of the expected value comparison circuit 14, and when the pass fail signal FAILFLAG is a fail signal, outputs a count value at that time, that is, a count value corresponding to the fail signal, as a CNTDATA signal. . The count value indicates the number of operations performed from the start of the test on the memory cell determined to be defective, and the operation performed on the memory cell determined to be defective based on this count value. Can be identified.

  The address register 152 holds an address signal RADR (address value) corresponding to the data output signal RDATA read from the memory 2 and compared and determined by the expected value comparison circuit 14. The address register 152 receives the pass fail signal FAILFLAG of the expected value comparison circuit 14 and outputs the address value at that time as a FAILADR signal when the pass fail signal FAILFLAG is a fail signal.

  The defective data register 153 holds the data output signal RDATA (data output value) read from the memory 2 and compared and determined by the expected value comparison circuit 14. When the pass fail signal FAILFLAG of the expected value comparison circuit 14 is input to the defective data register 153 and the pass fail signal FAILFLAG is a fail signal, the data output value at that time is output as a FAILBIT signal.

  The selector 19 is a selection circuit (MUX) that selects a signal output from the memory test circuit. The selector 19 selects whether to output the output signal FBOUT of the defect information storage register 17 or to output the output signal FBSTOUT of the defect information storage method designating register 18. The selector 19 is controlled by a control signal CONTROL2 output from the instruction control circuit 6 shown in FIG. When the output signal FBOUT of the defect information storage register 17 is output from the memory test circuit, “0” is input to the selector 19 as the CONTROL2 signal so as to be set to the mode 3 state shown in FIG. When the output signal FBSTOUT of the defect information storage method designating register 18 is output from the memory test circuit, “1” is input to the selector 19 as the CONTROL2 signal so as to be set to the mode 2 state shown in FIG. .

  The defect information storage method designation register 18 is a register for setting storage conditions for detected defect information, and is composed of a shift register. The defect information storage method designation register 18 receives the shift operation control signal SFDR and the shift clock signal CLKDR output from the TAP controller 7 in FIG. 3, and the control signal CONTROL2 output from the instruction control circuit 6 in FIG. . When the instruction control circuit 6 of FIG. 3 is in the mode 2 state shown in FIG. 4, a value for specifying the storage condition input from TMCHAIN is set in the defect information storage method specifying register 18.

  When the pass fail signal FAILFLAG input from the expected value comparison circuit 14 is a fail signal, the storage determination circuit 16 receives the storage method control signal STOREDATA set in the failure information storage method designating register 18 and the defect information signal FAILDATA1 input thereto. The storage processing determination shown in FIG. 7 is performed, and if the storage condition is satisfied, the failure information FAILDATA2 is output to the failure information storage register 17. As will be described later, the storage determination circuit 16 determines the conditions specified in the storage mode (storage method code register, storage method condition value register, defect detection number, defect address), that is, the condition of FIG. When it is satisfied, the defect information FAILDATA 2 is output and stored in the defect information storage register 17.

  The defect information storage register 17 is a register that stores detected defect information, and includes a shift register. The defect information storage register 17 receives the shift operation control signal SFDR and the shift clock signal CLKDR output from the TAP controller 7 in FIG. 3, and the control signals CONTROL1 and CONTROL2 output from the instruction control circuit 6 in FIG. . The defect information storage register 17 stores defect information FAILDATA2 when the instruction control circuit 6 in FIG. 3 is in the mode 1 state shown in FIG. Then, in the mode 3 state shown in FIG. 4, the failure information stored in the failure information storage register 17 is output as the output signal FBOUT in accordance with the shift operation control signal SFDR and the shift clock signal CLKDR.

  FIG. 6 shows a configuration example of the defect information storage method designation register 18. The defect information storage method designation register 18 includes a storage method code register 181 and a storage method condition value register 182.

  The storage method code register 181 is a register circuit that stores a code value that determines a storage method (storage standard) of defect information. Here, the defect information storage method includes, for example, the order from the detection start of the defect information to be stored among the detected defect information, such as “store from the detected defect number counted from the start of the test”. There is information to be specified by specifying the information. In addition, in the storage information of the defect information, the defect information to be stored such as “store the defect detected at what number or more addresses” and “store the defect detected at other than the address N” on the condition of the address There is also information to specify. In the present embodiment, a method of “store from the first detected defect counting from the start of the test” in the storage mode 1 is set. In this case, “00 (binary number)” is set in the storage method code register 181 as shown in the storage mode 1 of FIG.

  In addition to this, in the case of setting the storage mode 2 method of “storing defects detected at what address or higher”, as shown in FIG. 7, “01 (binary number) is stored in the storage method code register 181. When “is set and the method of storing a defect detected at other than address N” in the storage mode 3 is set, as shown in FIG. 7, “10 (binary number)” is stored in the storage method code register 181. And “11 (binary number)” is stored in the storage method code register 181 as shown in FIG. 7 when the storage mode 4 method “store only defects detected at address N” is set. Is set. As described above, the storage method can be changed according to the set value of the storage method code register 181.

  The storage method condition value register 182 sets storage conditions in the storage method set in the storage method code register 181. As in this example, in the case of the storage method of “store from the first detected defect counting from the start of the test”, if “11 (binary number)” is set in the storage method condition value register 182, “test The storage condition is “store from the third defect detected from the start”.

  In addition to this, in the case of the storage method of “storing a defect detected at what address or higher”, a storage for storing a defect detected at an address of a value set by the storage method condition value register 182 or more. It becomes a condition. In the case of the storage method of “storing defects detected at addresses other than N”, the storage condition is to store defects detected at addresses other than the address set in the storage method condition value register 182. In the case of the storage method “store only defects detected at address N”, the storage condition is that defects detected at the address of the value set in the storage method condition value register 182 are stored.

  As shown in FIG. 6, both the storage method code register 181 and the storage method condition value register 182 are configured by shift registers. The storage method code register 181 includes registers FBST-A1812, FBST-B1814, and the storage method condition value register 182 includes registers FBST-C1822 and FBST-D1824. The signals TMCHAIN, CLKDR, and SFDR input to the registers FBST-A1812 to FBST-D1824 are controlled by the control signal CONTROL2 through the gate circuits 1801, 1802, and 1803. When the control signal CONTROL2 is "1", these signals Is supplied. The selectors 1811, 1813, 1821, and 1823 are controlled by the shift operation control signal SFDR, and the inputs of the registers FBST-A1812 to FBST-D1824 are switched to select whether to shift or hold the signal from TMCHAIN. The input data is shifted according to the shift clock signal CLKDR.

  When the storage method set value is input to each of the registers FBST-A1812 to FBST-D1824 of the storage method code register 181 and the storage method condition value register 182, the instruction control circuit 6 in FIG. 3 is in the mode 2 state shown in FIG. “1” is input to the control signal CONTROL 2, and the storage method setting value is shift-input from the TMCHAIN from the shift operation control signal SFDR and the shift clock signal CLKDR output from the TAP controller 7 of FIG. During the memory test, CONTROL2 is "0" in the state of mode 1 shown in FIG. 4, so the outputs from the registers FBST-A1812 to FBST-C1824 are self-looped, and the stored data is output as STOREDATA. Is done.

  FIG. 8 shows a configuration example of the defect information storage register 17. The defect information storage register 17 includes registers 177a and 177b that store defect information and a register 176 (FBOV or FB0) that stores a flag value indicating that a defect has been detected.

  The register 176 is a register that stores a flag value indicating that a defect has been detected in excess of the number that can be stored. The initial value of the register 176 is “0”, and when it is determined that the number of data that can be stored by the storage determination circuit 16 of FIG. 5 is exceeded, the FAILOVER signal is input from the storage determination circuit 16, The flag “1” indicating that the threshold is exceeded is stored.

  Registers 177a and 177b indicate register circuits for storing defect information. The registers 177a and 177b are composed of registers 1771, 1772, 1773, 1774, and 1775 for storing the defect data, the defect address, the clock count value at the time of defect detection, the memory test mode, and the defect flag information shown in FIG. . In the present embodiment, the number of pieces of defect information that can be stored is two. Further, since the test target memory has a 4-address 3-bit configuration, as shown in FIG. 9, the defective data register 1771 has 3 bits, the defective address register 1772 has 2 bits, and the clock count register 1773 has the memory test pattern shown in FIG. 6 bits, the memory test mode register 1774 is 8 bits, and the defect flag register 1775 is 1 bit so that the count value 40 can be stored. Since the number of pieces of defect information stored is two, the defect information storage register 17 is composed of 41-bit registers (FBO to FB40).

  The defect information register 177a stores the value of the FAILDATA2 signal when the storage condition is satisfied by the storage determination circuit 16 of FIG. The FAILDATA2 signal includes an output FAILBIT (data output value at the time of failure) of the defective data register 153 in FIG. 5, an output FAILADR (address value at the time of failure) of the address register 152, and an output CNTDATA (count value at the time of failure) of the clock counter 151. 3 and the output MEMTESTMODE of the memory test mode control circuit 5 of FIG. 3 and the pass / fail signal FAILFLAG of the expected value comparison circuit 14 of FIG.

  When new defect information is stored in the defect information register circuit 177a, the defect information register 177b receives the defect information value of the defect information register 177a stored immediately before.

  Signals TMCHAIN, CLKDR, and SFDR input to each register in the defect information storage register 17 are controlled via the gate circuits 171, 172, and 173 by the control signal CONTROL2, and when the control signal CONTROL2 is "0" A signal is supplied. The signal SFDR is supplied as the signal FBSEN, and the input of each register is switched via the selector 174 by the signal FBSEN, and it is selected whether to shift or hold the signals from the signals TMCHAIN, FAILOVER, FAILEN, and FAILDATA2. The clock signal FBCLK input to each register in the defect information storage register 17 is controlled via the selector 175 by the control signal CONTROL1, and either the clock signal BISTCLK or CLKDR is selected and supplied.

  FIG. 10 shows a circuit configuration of the defect information register 177a and the defect information register 177b. The defect information register 177a is configured by registers FB1 to FB20, and the defect information register 177b is configured by registers FB21 to FB40.

  During the memory test, since the shift operation control signal SFDR output from the TAP controller 7 in FIG. 3 is “0”, the FBSFEN signal is “0”, and the value of FAILDATA2 is input to the defect information register 177b. . Further, the shift information signals FBSFDATA1 to FBSFDATA20 from the defect information register 177b are input to the defect information register 177a. At this time, the clock signal FBCLK input to the registers 176, 177a and 177b is “0” in the state of the mode 1 shown in FIG. 4 because the control signal CONTROL1 connected to the selector 175 shown in FIG. It becomes BISTCLK that operates the test. When the defect information stored in the defect information storage register 17 is to be output to the outside, the instruction control circuit 6 in FIG. 3 is set to the mode 3 state shown in FIG. In the case of mode 3, since the control signal CONTROL1 is “1”, the clock signal FBCLK input to the register circuits 176, 177a, 177b operates with the shift clock signal CLKDR output from the TAP controller 7 of FIG. When "0" is input to the control signal CONTROL2 and the shift operation control signal SFDR becomes active (a value of "1"), the FBSFEN signal is "1", and the registers that constitute the register 176 and the defect information registers 177a and 177b FB0 to FB40 shift, and defect information is output to FBOUT.

  Under the control of the control signal CONTROL 1 of the instruction control circuit 6, the defect information is stored in the defect information storage register 17 using the clock signal BISTCLK (high-speed clock) used for the memory test. It is possible to do. When the stored defect information is extracted to the outside, it can be output at a speed that can be observed by a tester using a shift clock signal CLKDR (low speed clock) output from the TAP controller 7 of FIG.

  Next, the failure analysis operation in the memory test circuit according to the present embodiment will be described along the flow shown in FIG. In this embodiment, the memories 2a and 2b to be tested have a 4-address 3-bit configuration, two pieces of defect information are stored, and the defect information storage method is “store from the third detected defect”. Further, it is assumed that the memories 2a and 2b have a defect in which the data bit 0 of the address 2 has a fixed value “1” and a defect in which all the data bits of the address 3 have a fixed value “1”.

  First, in S101 of the flowchart shown in FIG. 12, an operation for setting a storage method in the defect information storage method designation register 18 is performed. First, the instruction control circuit 6 shown in FIG. 3 is set to the mode 2 defined by the table of FIG. Then, “1” is output to the control signal CONTROL2. As a result, the setting value of the storage method input from the external terminal TDI is input to the defect information storage method register 18 shown in FIG. 6 through TMCHAIN. In accordance with the shift operation control signal SFDR and the clock signal CLKDR output from the TAP controller 7 shown in FIG. 3, the input values from TMCHAIN are shifted to the registers FBST1 to FBST4 constituting the defect information storage method register 18 of FIG. Since the storage method is “store from the third detected defect”, it corresponds to storage mode 1 from the table shown in FIG. In the storage method code register 181 of FIG. 6, {FBST1, FBST2} is set to {"0", "0"}, and the storage method condition value register 182 is configured to the third in {FBST3, FBST4}. {"1", "1"} is set as a binary value to be indicated.

  Next, in S102 of the flowchart shown in FIG. 13, a memory test is performed. That is, the instruction control circuit 6 shown in FIG. 3 is set to the mode 1 defined by the table of FIG. Then, “0” is output to the control signal CONTROL 1 and “0” is output to the CONTROL 2. Thereby, the test mode registers 3a and 3b shown in FIG. 3 output the TESTRST1 and TESTRST2 signals, respectively, to set the memory test circuits 1a and 1b to the active state, and the memory test circuits 1a and 1b shown in FIG. In order to generate a partial pattern of the memory test pattern, a pattern mode value input to the memory test mode control circuit 5 is input from the external terminal TDI. This operation is also controlled by the shift operation control signal SFDR and the clock signal CLKDR output from the TAP controller 7 of FIG. The memory test mode control circuit 5 is set with 8 bits of address mode “3′b101”, Read / Write mode “3′b101”, and data mode “2′b11” which are the pattern mode signals of the partial patterns shown in FIG. To do.

  Then, by making the START signal active from the outside, the memory test circuits 1a and 1b start the memory test with the pattern shown in FIG. During this memory test, the control signal SFDR and the clock signal CLKDR output from the TAP controller 7 in FIG. 3 are both “0”, the FBSFEN signal in FIG. 8 is “0”, and the defect information register circuit 177a, The FAILDATA2 and FBSFDATA signal lines for storing defect information in 177b are activated. Since CONTROL1 is “0”, the defect information storage register 17 operates with the BISTCLK signal.

  First, the data at address 2 is read out as an RDATA signal from the memory 2 in FIG. 5 by the Pattern-Number 6 in the table shown in FIG. 11, and the expected value from the expected value generation circuit 13 in the expected value comparison circuit 14 in FIG. It is compared with the signal EXDATA. A failure is detected at data bit 0, the FAILFLAG signal becomes active (value of “1”), and the failure information signal FAILDATA1 is input to the storage determination circuit 16 of FIG.

  The storage determination circuit 16 in FIG. 5 performs storage determination according to the flow shown in FIG. 13 based on the signal STOREDATA from the defect information storage method designation register 18.

  That is, in S201, the storage determination circuit 16 initializes the defect detection number count k and the defect storage number count p, and sets the storage method condition value register 182 according to the value (storage mode) of the storage method code register 181. In S202, a memory test is performed and t is counted up for each test pattern. When a failure is detected in the memory test, in S203, in the case of the storage modes 2 to 4, the detected defective address is determined according to the value of the storage method code register 181. In the case of the storage mode 1 according to the value of the storage method code register 181, it is determined in S204 whether or not k has reached the number of detections at which storage is started. If the condition of S203 or S204 is satisfied, it is determined in S205 whether p is within the range of the number of defects that can be stored. If the condition of S205 is satisfied, the FAILEN signal and FAILDATA2 are output from the storage determination circuit 16 and stored in the defect information storage register 17 in S206. In S208, when the defect information is already stored in the defect information storage register 17, the stored defect information is shifted to the register in which the defect information is not stored, the defect information is stored in the empty defect information register, and the defect is stored. The number p is counted up. If the condition of S205 is not satisfied, the FAILOVER signal of the storage determination circuit 16 is made active in S207, and 1 is set in the register 176 in S209. After S208 or S209, in S210, the defect detection number k is counted up and the memory test is repeated.

  In this example, since the storage method is “store from the third detection failure”, since the condition is not satisfied in S204 in FIG. 13, the number of detections in S210 is counted up. Similarly, a defect is detected at address 3 in the table Pattern-Number 8 in FIG. 11, but only S210 is executed because the condition is not satisfied. In the table shown in FIG. 11, the defect detected by the read comparison of the address 2 at the Pattern-Number 16 is the third detected defect, and the storage determination circuit 16 satisfies the condition of S204 in FIG. Is also cleared, and the storing operation of S206 and S208 is performed.

  The defect information FAILDATA2 is output from the storage determination circuit 16 shown in FIG. At this time, the FAILEN signal output from the storage determination circuit 16 becomes active (value of “1”). The defect information FAILDATA2 is input to the defect information register 177b shown in FIG. 8, and the defect data register 1771 in FIG. 9 (registers {FB21, FB22, FB23} in FIG. 10) indicates the data output value “001” at the time of failure { The value of 0, 0, 1}, the value of {1, 0} indicating the address 2 at the time of failure in the failure address register 1772 (register {FB24, FB25} in FIG. 10), the clock count register 1773 (register {in FIG. 10) FB26 to FB31}) is a value of {0, 1, 0, 0, 0, 0} indicating the clock count value 16, and the memory test mode register 1774 (register {FB32 to FB39} in FIG. 10) is in the pattern mode of FIG. {1,0,1,1,0,1,1,1} values indicating {"101", "101", "11"}, failure flag register 1775 (FIG. The value of indicating that a defect is present in the 0 of the register {FB40}) {1} is stored. At this time, the number of pieces of defect information stored in S208 of FIG. 13 is 1 (p = 1).

  Next, a defect is detected by the read comparison of the address 3 of the Pattern-Number 18 in the table of FIG. The conditions of S204 and S205 in FIG. 13 are satisfied, and the storage operations of S206 and S207 are performed. The previously detected defect information stored in each of the registers FB21 to FB40 constituting the defect information register 177b of FIG. 10 is that the FAILEN signal output from the storage determination circuit 16 of FIG. 5 is active (value of “1”). Thus, the signals are shifted into the registers FB1 to FB20 constituting the defect information register 177a of FIG. 10 through the FBSFDATA1 to FBSFDATA20 signals. The defect information FAILDATA2 is input to the defect information register 177b in FIG. 8, and the defect data register 1771 in FIG. 9 (registers {FB21, FB22, FB23} in FIG. 10) indicates the data output value “111” at the time of defect {1 , 1, 1}, a defective address register 1772 (register {FB24, FB25} in FIG. 10), a value of {1, 1} indicating the address 3 at the time of failure, a clock count register 1773 (register {FB26 in FIG. 10) To FB31}) is a value of {0, 1, 0, 0, 1, 0} indicating the clock count value 18, and the memory test mode register 1774 (registers {FB32 to FB39} in FIG. 10) has the pattern mode { The value of {1, 0, 1, 1, 0, 1, 1, 1} indicating “101”, “101”, “11”}, the defect flag register 1775 (FIG. 10). The value of the register {FB40}) to indicate that the defect is present {1}, is stored. At this time, the number of pieces of defect information stored in S208 of FIG. 13 is two (p = 2).

  Further, a defect is detected by the read comparison of the address 2 of the Pattern-Number 21 in the following table of FIG. In the storage determination circuit 16 of FIG. 5, the flow process of FIG. 13 is performed. At this time, although the condition of S204 in FIG. 13 is satisfied, since the number of pieces of defect information that can be stored exceeds two in S205, the process proceeds to S207 and S209. The FAILOVER signal indicating that the number that can be stored is exceeded from the storage determination circuit 16 in FIG. 5 is output as active (value of “1”), and this flag signal is stored in the register 176 (FBOV) in FIG. The subsequent detected defects are similarly performed in S207 and S209 of FIG.

  When the memory test is completed, an operation of outputting defect information from the defect information storage register to the outside is performed in S103 of the flowchart shown in FIG. That is, the instruction control circuit 6 shown in FIG. 3 is set to the mode 3 defined by the table of FIG. The control signal CONTROL1 is “1” and CONTROL2 is “0”. As a result, the defect information stored in the defect information storage register 17 shown in FIG. 5 is output to the outside through the FBOUT signal. Since the control signal CONTROL1 is “1”, the clock signal FBCLK input to the registers 176, 177a, 177b in FIG. 8 operates with the shift clock signal CLKDR output from the TAP controller 7 in FIG. When "0" is input to the control signal CONTROL2 and the shift operation control signal SFDR becomes active (value of "1"), the failure information register 177b in FIG. 8 (registers {FB40 to FB21} in FIG. 10), failure The information register 177a (registers {FB20 to FB1} in FIG. 10) and the register 176 (FBOV) are shifted in order from FBOUT. This operation is performed in each of the memory test circuits 1a and 1b in FIG. 3, and the defect information detected from the memory 2b and the defect information detected from the memory 2a are output in order from the external terminal TDO.

  In the present embodiment, the memory test pattern portion illustrated in FIG. 11 corresponding to the memory test mode information {“101”, “101”, “11”} for the memories 2a and 2b from the output defect information. A test is performed on the pattern, and a defect is detected in the pattern 16 and the pattern 18 included in the partial pattern from the clock count value, and there is a defect such as data “001” at the address 2 and data “111” at the address 3. Recognize. Further, it can be known from the information of the flag indicating that there is a defect exceeding the number of stored, that there is a defect other than the stored one.

  Next, in S104 of the flowchart shown in FIG. 12, since there are more defects than can be stored, in order to obtain further defect information, the storage method setting is changed from S101 and the same operation is performed again. carry out.

  In the present embodiment, as in Conventional Example 1, it is possible to solve the problem that it is not possible to confirm the state in which a failure has occurred unless the contents of the partial pattern configuration of the implemented memory test pattern are known. That is, the pattern mode signal MEMTESTMODE output from the memory test mode control circuit 5 of FIG. 3 and instructing the partial pattern generated by the memory test circuits 1a and 1b is used as the memory test that constitutes the defect information registers 177a and 177b shown in FIG. Store in the mode register 1774. As a result, after performing other partial patterns constituting the memory test pattern including the partial pattern as shown in FIG. 11 this time, the defect information is stored in the memory test mode register 1774 when taken out to the outside. By confirming the pattern mode, it is possible to determine what kind of memory test pattern a defect is detected.

  Further, in the present embodiment, as in Conventional Example 2, it is possible to solve the problem that it is not known which part pattern of the implemented memory test pattern and in what number pattern in the partial pattern the defect is detected. Can do. That is, the pattern number counted by the clock counter 151 from the time when the partial pattern output of the memory test pattern starts from the test pattern generation circuit 12 of FIG. 5 is used as the clock count register constituting the defect information registers 177a and 177b shown in FIG. 1773. As a result, by confirming the pattern mode stored in the memory test mode register 1774 and the value stored in the clock count register 1773 as described above, it is possible to determine which partial pattern the defect is detected in. It becomes possible to discriminate.

  Furthermore, in the present embodiment, as in Conventional Example 1 and Conventional Example 2, it is possible to solve the problem that the defect information can be stored only up to the prepared size and the defect information beyond that cannot be known. That is, the defect information storage method designation register 18 and the storage determination circuit 16 shown in FIGS. 5 and 6 are prepared, and the defect information storage method designation register 18 sets the defect information storage method from the outside. 11 is performed according to the storage determination shown in FIG. In the above example, the storage method is set to the condition “store from the third detected defect”, and storage is performed by repeatedly storing defect information and outputting to the outside according to the flow shown in FIG. 12 while changing the storage method. Defect information exceeding the number that can be collected. Also, by preparing the flag register 176 indicating that there are defects exceeding the number that can be stored as shown in FIG. 8, it is possible to determine whether or not there are defects other than those stored.

  As described above, according to the present embodiment, in addition to data output and address at the time of failure detection as memory failure information, in which partial pattern of the memory test pattern, and what number pattern in the partial pattern It is possible to determine whether a defect has been detected. In addition, according to the present embodiment, a circuit for controlling a storage method of defect information such as “store the detected defect at what number”, “store the defect detected at what number or more”, and the number of stored items By preparing a 1-bit register indicating whether or not a defect has been detected beyond the threshold, it is possible to confirm the defect for all addresses of the test target memory.

  The present invention is not limited to the above-described embodiment, and various modifications and implementations are possible without departing from the scope of the present invention.

It is a block diagram of the memory test circuit of the prior art example 1. FIG. 10 is a configuration diagram of a memory test circuit of Conventional Example 2. It is a block diagram of the whole circuit containing the memory test circuit concerning this invention. It is an output control signal table | surface which shows operation | movement of the instruction control circuit concerning this invention. It is a circuit diagram which shows the structure of the memory test circuit concerning this invention. It is a circuit diagram which shows the structure of the defect information storage method designation | designated register concerning this invention. It is an operation | movement table | surface which shows operation | movement of the storage determination circuit concerning this invention. It is a circuit diagram which shows the structure of the defect information storage register concerning this invention. It is a circuit diagram which shows the structure of the defect information register concerning this invention. It is a circuit diagram which shows the structure of the defect information register circuit concerning this invention. It is a figure which shows an example of the partial pattern of the memory test pattern concerning this invention. 5 is a flowchart showing an outline of a test circuit failure analysis method according to the present invention. 4 is a flowchart showing operations of a storage determination circuit and a defect information storage register according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a, 1b Memory test circuit 2a, 2b Memory 3a, 3b Test mode register 4a, 4b Selector 5 Memory test mode control circuit 6 Instruction control circuit 7 TAP controller 18 Defect information storage method designation register 16 Storage determination circuit 17 Defect information storage register 11 Test control circuit 12 Test pattern generation circuit 13 Expected value generation circuit 14 Expected value comparison circuit 151 Clock counter 152 Address register 153 Defective data register 19 Selector 176 Register 177 Defective information register 181 Storing method code register 182 Storing method condition value register 1771 Defective data Register 1772 Defective address register 1773 Clock count register 1774 Memory test mode register 1775 Defective flag register

Claims (13)

A memory test circuit for testing a memory,
A memory test circuit that constitutes a part of a test pattern, performs a test on the memory in accordance with a pattern mode signal that designates a partial pattern consisting of a plurality of operations, and stores the pattern mode signal as part of defect information . The memory test circuit includes:
A test pattern generation circuit for generating a test pattern according to the pattern mode signal;
An expected value generating circuit for generating an expected value according to the pattern mode signal;
An expected value comparison circuit that compares the output data of the memory with the expected value generated by the expected value generation circuit and detects a defect;
2. The memory test circuit according to claim 1, further comprising defect information storage means for storing defect information detected by the expected value comparison circuit including the pattern mode signal. Furthermore, a counter that counts the number of a plurality of operations constituting the partial pattern is provided,
3. The memory test circuit according to claim 2, wherein a count value corresponding to a failure detected in the expected value comparison circuit is stored in the failure information storage means as a part of the failure information.   It further comprises a storage determination circuit for determining whether or not defect information detected in the expected value comparison circuit is stored in the defect information storage means according to preset defect information storage method information. The memory test circuit according to claim 2. The defect information storage method information includes information specifying defect information to be stored among the detected defect information by specifying rank information from the detection start,
5. The memory test circuit according to claim 4, wherein the storage determination circuit stores defect information corresponding to the rank information in the defect information storage means. The defect information storage method information includes information specifying defect information to be stored among detected defect information on the condition of an address,
5. The memory test circuit according to claim 4, wherein the storage determination unit stores defect information corresponding to the condition in the defect information storage unit. A memory test circuit for testing a memory,
Defect information detection means for detecting defect information of the memory;
A memory test circuit comprising: a storage determination unit that determines whether or not the defect information detected by the defect information detection unit is stored in the defect information storage unit according to preset defect information storage method information. The defect information storage method information includes information specifying defect information to be stored among the detected defect information by specifying rank information from the detection start,
8. The memory test circuit according to claim 7, wherein the storage determination unit stores defect information corresponding to the rank information in the defect information storage unit. The defect information storage method information includes information specifying defect information to be stored among detected defect information on the condition of an address,
8. The memory test circuit according to claim 7, wherein the storage determining unit stores defect information corresponding to the condition in the defect information storing unit. The defect information storage method information includes information on the number of defect information that can be stored in the defect information storage means,
8. The memory test circuit according to claim 7, wherein the storage determination unit stores the defect information of the number of pieces of defect information that can be stored in the defect information storage unit. The defect information storage means includes flag storage means,
11. The memory test circuit according to claim 10, wherein when the number of pieces of defect information exceeds the number of pieces of defect information that can be stored, a value indicating that the number of pieces of defect information has been exceeded is stored in the flag storage unit. . A memory test method for testing a memory,
A memory test method for configuring a part of a test pattern, performing a test on the memory in accordance with a pattern mode signal designating a partial pattern consisting of a plurality of operations, and storing the pattern mode signal as part of defect information . A memory test method for testing a memory,
Detecting defective information in the memory;
A memory test method for determining whether or not to store defect information detected in accordance with preset defect information storage method information.

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