JP2000353187A - Method and device for testing critical pass and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a critical pass testing method capable of simply judging whether a critical pass test is applied to all passes or an optional pass. SOLUTION: A semiconductor integrated circuit has a process (step S2) for executing 1st simulation and detecting cells synchronized with a clock signal, a process (step S3) for allowing the detected cells to store an output result outputted to the 1st simulation as an expected value, a process (step S4) for applying output delay to an optional cell out of the detected cells, a process (step S5) for executing the 2nd simulation of the detected cells, a process (step S6) for comparing the output result of each cell with an expected value, and a process (step S7) for judging that the critical pass test is not executed when the output value coincide with the expected value. It is preferable to use the same test pattern for the 1st simulation and the 2nd simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a critical path test method and apparatus for finding a critical path in a signal propagation path (hereinafter referred to as a "path") in a semiconductor integrated circuit, and more particularly, to a critical path test method and apparatus. The present invention relates to a critical path test method and apparatus that can determine whether a critical path test is performed on a path.

[0002]

2. Description of the Related Art With the recent increase in the scale and speed of semiconductor integrated circuits, critical path tests for logic circuits have become indispensable. As such a critical path test method, for example, a method disclosed in JP-A-1-297765 is known. In the critical path test method disclosed in this publication, the gate delay time of a cell forming an integrated circuit is gradually extended, and the critical delay is determined based on whether or not another cell related to the cell having given the output delay malfunctions. Determines whether it is a pass.

However, there are cases where a large number of paths are branched while following a circuit from a cell synchronized with a clock to a cell synchronized with the next clock, and it is necessary to check all paths in the circuit. Has the problem that it requires a rather complicated algorithm program.

In order to solve such a problem, a critical path check method disclosed in Japanese Patent Laid-Open Publication No. 6-19998 discloses a simulation of a hold time of a cell in a circuit operating in synchronization with a clock with respect to a clock. And whether the calculation result is within the allowable value is determined for all cells in the circuit.

However, according to this method, it is unclear whether the test pattern used in the simulation reflects the delay of all paths, that is, whether the critical path test is performed for all paths.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and performs a critical path test or a critical path test. To provide a critical path test method and apparatus capable of easily determining whether or not a path has been performed, and to determine whether a test pattern for simulation used in a critical path test covers all paths. It is an object of the present invention to provide a critical path test method and apparatus that can be easily determined.

[0007]

According to a first aspect of the present invention, a critical path test for simulating the operation of a semiconductor integrated circuit is performed on all paths or arbitrary paths in the semiconductor integrated circuit. Performing a first simulation on the semiconductor integrated circuit; detecting a cell synchronized with a clock signal; and Storing, as an expected value, an output result output from the detected cell with respect to the first simulation; providing an output delay to any of the detected cells; and detecting the detected cell. Executing a second simulation to compare the output result of the cell with the expected value, and when the comparison result matches, There as a method having a step of determining a critical path testing is not performed.

According to this method, the first simulation is executed using an existing test pattern, the result is set as an expected value, and the result is compared with the output result of the second simulation performed with an output delay. This makes it possible to easily determine whether the path to be determined has completed the critical path test.

The invention according to claim 2 is a method for sequentially giving an output delay to all the detected cells and performing the determination for each cell. According to this method, it is possible to easily determine whether the critical path test has been performed for all the paths in the circuit.

The invention according to claim 3 is a method in which the first simulation and the second simulation are executed by the same test pattern. According to this method, by performing the first and second simulations with the same test pattern, it is easy to determine whether or not the test pattern according to the simulation is highly reliable covering all cells. Can be determined.

According to a fourth aspect of the present invention, there is provided a critical path test for determining whether or not a critical path test for simulating the operation of a semiconductor integrated circuit is performed for all paths or an arbitrary path in a circuit. A test apparatus, comprising: a first simulation execution unit that executes a first simulation on the semiconductor integrated circuit; a detection unit that detects a cell synchronized with a clock signal; A memory for storing the output result output for the execution as an expected value, an output delay providing unit for providing an output delay to any of the detected cells, and a method for providing an output delay to the cell. 2nd simulation execution part which performs 2nd simulation, and the output result by execution of the said 2nd simulation A comparing unit for comparing the expected value read from the memory, it is constituted with the a determination unit critical path testing is not performed when the comparison result by the comparison unit are identical.

According to this configuration, the first simulation is executed using the existing test pattern, the result is set as an expected value, and the result is compared with the output result of the second simulation performed with an output delay. This makes it possible to easily determine whether the path to be determined has completed the critical path test.

According to a fifth aspect of the present invention, an output delay is sequentially applied to all the detected cells, and the determination is performed for each cell. According to this configuration, it is possible to easily determine whether the critical path test has been performed for all the paths in the circuit.

The invention according to claim 6 is configured such that the first simulation and the second simulation are executed by the same test pattern. According to this configuration, since the first and second simulations are the same, it is easy to determine whether or not the test pattern according to the simulation is highly reliable covering all cells. It is possible.

According to a seventh aspect of the present invention, there is provided a storage medium storing a program for executing the method according to any one of the first to fifth aspects. The storage medium includes a magnetic tape, a magnetic disk, an optical disk,
In addition to the memory chip, those that can execute the program via communication means are also included.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The critical path test method of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a flowchart for explaining a critical path test method according to an embodiment of the present invention, and FIG. 2 is a schematic diagram showing cells synchronized with a clock.

First, the principle of the present invention will be described with reference to FIG. The circuit shown in FIG. 2 includes a cell A, a cell B, and a cell C synchronized with a clock by executing a simulation. Cell A and cell B are connected to cell C via gate circuit 3 by paths P1 and P2 to be checked by a critical path.

In the circuit shown in FIG. 2, for example, a cell B is selected, and an output delay is given to the cell B. The delay time to be given is arbitrary, but is preferably set to a value that does not satisfy the setup time or the hold time of the cell C in the next stage. In this case, "1" is output from the cell A. In this state, the result of the simulation is collated using the existing test pattern. In the case where the existing test pattern does not include a change in the value of the cell B, if the simulation result matches the result before the output delay is given, the critical path test has been performed on the path P1. You can determine that there is no. Conversely, if they do not match, it can be determined that a critical path test has been performed.

For the path A, by giving an output delay to the cell A while outputting "1" from the cell B, it is possible to determine whether or not the critical path test is performed in the same manner as described above. . In this way, by repeating the above procedure for an arbitrary cell or all cells in a circuit, it is possible to determine whether a critical path test has been performed for an arbitrary path or all paths in a circuit. .

Next, an embodiment of the critical path test method of the present invention will be described with reference to FIG. First, a simulation is performed using an existing test pattern (step S1). Further, a cell synchronized with the clock is searched (step S2). On the other hand, the result output by executing the simulation is stored in a memory or the like as an expected value (step S3).

An output delay is given to an arbitrary cell (step S
4), a simulation is executed with the same test pattern as the previously executed simulation (step S)
5). Then, the result is compared with the expected value previously stored in the memory (step S6). If these results match,
It is determined that the critical path test has not been performed, and the result is displayed (step S8). If they do not match, it is determined that the critical path test has been performed.

If the above determination is made for all paths, the process returns to step S4, and the above steps S4 to S8 are repeated until the determination is completed for all cells. In this embodiment, since the simulation in step S1 and the simulation in step S5 are executed with the same test pattern, it is determined whether the simulation for performing the critical path test covers all paths in the circuit. It can be easily determined by the procedure.

In order to confirm whether or not a critical path test has been performed for some cells in the circuit, the simulation in step S1 and the
5 is not necessarily the same as the simulation of FIG. If both simulations give the same expected value in the state where no output delay is applied to the some cells to be tested, the simulation in step S1 is different from the simulation in step S5. It may be based on a test pattern.

Next, a critical path test apparatus for performing the above method will be described with reference to FIG. FIG.
1 is a block diagram illustrating a critical path test device according to one embodiment of the present invention.

The critical path test apparatus according to this embodiment includes a first memory 10 for storing a predetermined test pattern for executing a simulation on a semiconductor integrated circuit, and reading the test pattern from the first memory to perform a simulation. , A cell detector 12 for detecting a cell synchronized with a clock signal, and an output result extractor 1 for extracting an output result output from the cell for the simulation.
3, a second memory 14 for storing the extracted output result as an expected value, an output delay giving unit 15 for giving an output delay to any of the detected cells, and a state where an output delay is given The comparison section 16 compares the output result obtained by executing the simulation with the expected value read from the second memory 14, and determines whether or not the comparison result by the comparison section 16 matches the critical path test. Judgment unit 1 for judging whether or not it has been performed
7 and a display unit 18 for displaying the determination result on a display or a printer.

The test pattern for the simulation is stored in the first memory 10, and the simulation execution unit 11 reads out a predetermined test pattern from the first memory 10 and executes the simulation. Cell detector 1
2 searches for a cell synchronized with the clock from within the circuit, and stores the found cell in the second memory 14. The output result extraction unit 13 extracts an output result output by the cell discovered by the cell detection unit 12 by executing the simulation, and stores the output result in the second memory 14 as an expected value.

Thereafter, the output delay imparting section 15 imparts an output delay to an arbitrary cell among the cells read from the second memory 14, and the simulation executing section 11 reads from the first memory 10. The same simulation is executed by the test pattern. The output result of the simulation for each cell is extracted by the output result extraction unit 13,
The data is sent to the comparison unit 16. In the comparison unit 16, the second memory 14
Is compared with the expected value read from the above and an output result obtained by executing a simulation with an output delay.

Then, the judging section 17 judges whether or not the critical path test is being performed based on whether or not the comparison results match, and outputs the judgment result to the display section 18. The display unit 18 may display only cells for which it has been determined that the critical path test has not been performed, or may list and display the determination results for all cells.

[0029]

According to the present invention, the output of a signal of a cell in a synchronized circuit is given an output delay that does not satisfy the setup time or the hold time of the next stage cell C,
By judging whether the output signal of the next stage cell is different from or coincident with the expected value, a path that has not been subjected to the critical path test can be easily determined without judging which path is the critical path. Can be found.

By performing the above procedure for all cells, it is possible to easily determine whether or not the critical path test has been performed for all paths in the circuit. Further, the first simulation and the second simulation
By executing the simulation with the same test pattern, it is possible to easily check whether or not the existing test pattern covers all the cells in the circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a critical path test method according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating the principle of the present invention and is a schematic diagram illustrating cells synchronized with a clock.

FIG. 3 is a block diagram illustrating a critical path test apparatus according to one embodiment of the present invention.

[Explanation of symbols]

 A, B, C cells P1, P2 path 3 gate circuit 10 first memory 11 simulation execution unit 12 cell detection unit 13 output result extraction unit 14 second memory 15 output delay assignment unit 16 comparison unit 17 determination unit 18 display unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Taketoshi Hayakawa 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term within NEC Icy Microcomputer Systems Co., Ltd. 2G032 AA01 AC03 AC08 AD05 AG01 5B046 AA08 BA09 HA03 JA04 JA05 5B048 AA20 CC01 DD05 DD15 FF03 5F038 CD06 CD09 DT10 DT17 EZ10 EZ20

Claims (7)

[Claims] 1. A critical path test method capable of determining whether a critical path test for performing an operation simulation of a semiconductor integrated circuit is performed for all paths or an arbitrary path in the semiconductor integrated circuit. Performing a first simulation on the semiconductor integrated circuit; detecting a cell synchronized with a clock signal; and outputting an output of the detected cell to the first simulation. As an expected value; providing an output delay to any of the detected cells; performing a second simulation on the detected cells; and setting the output result of the cells to the expected value. A step of comparing with a value, and when the comparison result matches, it is determined that the critical path test has not been performed A critical path test method, comprising: 2. The critical path test method according to claim 1, wherein an output delay is sequentially given to all the detected cells, and the determination is performed for each cell. 3. The first simulation and the second simulation
3. The critical path test method according to claim 1, wherein the simulation is performed by the same test pattern. 4. A critical path test apparatus capable of determining whether a critical path test for performing an operation simulation of a semiconductor integrated circuit is performed on all paths or an arbitrary path in the semiconductor integrated circuit. A first simulation execution unit that executes a first simulation on the semiconductor integrated circuit; a cell detection unit that detects a cell synchronized with a clock signal; and the cell executes the first simulation. A memory for storing an output result output to the cell as an expected value; an output delay providing unit for providing an output delay to any of the detected cells; and a second simulation after providing a delay to the cell. A second simulation executing unit for executing the second simulation, and an output result obtained by executing the second simulation And a comparing unit that compares the expected value read from the memory with the comparing unit; and a determining unit that determines that the critical path test is not performed when the comparison result by the comparing unit matches. Critical path test equipment. 5. The critical path test apparatus according to claim 4, wherein an output delay is sequentially applied to all of the detected cells, and the determination is performed for each cell. 6. The first simulation and the second simulation
6. The critical path test apparatus according to claim 4, wherein the simulation is performed by the same test pattern. 7. A storage medium storing a program for executing the method according to claim 1. Description: