JP2003194890A - Failure analyzing method, and analysis of failure supporting device and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To follow up a failure propagation route in a case when a memory block having only the functional description and not having the information on a gate description level exists in a failure signal propagation route. <P>SOLUTION: Identifiers of write control, read control and an address and data input and output wire or signal are specified in steps 101-103 with respect to the memory block having functional description, a simulation time, a write control wire/read control wire state orresponding to the time, a selected address, and the data to be written/read out with respect to the selected address are extracted on the basis of these identifiers, and outputted with a format of binary digit display when the simulation is performed in a step 104. In the failure analysis, the failure propagation route is followed up by comparing the output with the created memory block internal state output. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI failure analysis, and more particularly to an LS having a memory block whose function is described.
The present invention relates to a failure analysis method, a failure analysis support device, and a failure analysis support program that are effective for I failure analysis.

[0002]

2. Description of the Related Art Even if an LSI whose design has been completed without any problems in layout verification and production has been started, a defect may occur due to a defect in the production, resulting in a defective product. In such a case, physical analysis is performed to identify the failure location and cause. If the failure propagation path reaches the memory in the physical analysis, the memory address accessed in the functional verification simulation, the value held by the memory cell, the expected value of each of the write control line and the read control line, or the good memory cell Of the memory address, the value held by the memory cell, the write control line, and the read control line, and the memory address of the defective product, the value held by the memory cell, the write control line, the measured value of the read control line are compared. Then, it is verified whether the cause of the failure signal propagating to the memory cell is the address designating the memory cell, the data held in the memory cell at the designated address, the data writing, or the data reading.

In general, it is difficult to nondestructively analyze all failures that have occurred in the wiring layers and diffusion layers of products having a multilayer wiring structure of three or more layers. Particularly in a hard macro whose layout arrangement is predetermined such as an embedded memory, it is rare that the wiring exists in the uppermost layer where the potential can be observed.
Therefore, by using a FIB (Focused Ion Beam) or the like, a fine hole reaching the surface of the wiring to be measured is formed, and the information of the electric signal of the lower layer wiring is repeatedly acquired to trace the failure location.

However, it takes a great deal of analysis time to form a fine hole by the FIB along the propagation path of the failure signal and trace the failure point. In order to reduce the time required to trace this physical fault signal, the fault propagation path is traced in software using the design information and the expected value obtained by simulation, with the fault output detected during testing as the starting point for tracing. A method of identifying a failure location is known. As one method, an inverse logic expansion method that identifies a failure location other than the functional failure of the flip-flop from the design information and the test result by tracing the failure propagation path while extracting the combinational circuit in which the failure may exist There is. For example, Japanese Unexamined Patent Application Publication No. 2001-21618 discloses an inverse logic expansion method applying a backtrack method, and a specific logic state of an input signal obtained by the inverse logic expansion method,
And a fault propagation path is extracted by comparing the logic state inside the combinational logic circuit obtained in the process with the logic state of each node (hereinafter referred to as an expected value) obtained by performing a logic simulation of a normal circuit in advance. . As another method, there is a method of executing a failure simulation in advance to create a failure dictionary and comparing the failure data recorded in the failure dictionary at the time of diagnosis to identify the failure location. Although it is specialized for SCAN design, software having a function of searching a failure factor by a failure dictionary method is commercially available.

In the functional description design in the top-down design method, the inside of the LSI is divided into functional blocks based on the specification design, the combinational circuit provided between the registers in the functional block is determined, and the circuit operation for each clock timing is determined. To decide. It is used for design verification of the entire chip by simulation etc. until the gate level description of the functional block is completed in the gate level description design which is the next design stage. However, the situation is different for hard macro blocks, such as embedded memory, whose layout has been decided in advance. The hard macro block has a separate means for testing the internal circuit, and its function has been verified in advance. For this reason, in functional verification of the entire chip by simulation, functional blocks having functional descriptions are used at any design stage.

As described above, there is a memory block in the LSI which is hard macrod and has only the information of the function description level and not the information of the gate description level, and an error signal is output when the test for accessing the memory is executed. In this case, in order to verify whether the error signal is output via the memory block, it is necessary to first refer to the data held by the memory cell at the accessed address. As an example of how to refer to the data held by the memory cell, construct a simulation model corresponding to the memory design specifications, and use the memory debug verification tool to observe the memory contents and detect errors during simulation. , It is possible to verify whether or not the failure signal has passed through the memory. When the failure signal does not pass through the memory, the above-mentioned JP-A-2001-216
The failure location can be identified by applying the failure location identification method or the like described in JP-A-18.

[0007]

In the failure analysis using the electron beam tester, by comparing the potential images of the layout coordinates corresponding to the good product and the defective product, the signal lines that do not match in the pattern recognition are propagated to the failure signal. It can be easily detected as wiring. However, the situation is different when comparing the expected value with the actually measured value. The expected value in the simulation is obtained by designating the virtual time defined as the time elapsed in the simulation when the simulation is executed and acquiring the value held by the specific wiring. The expected value is described in a format that refers to each net name that has changed with the passage of virtual time and the value that it holds, or in a format that refers to the value that has changed for each net according to the passage of virtual time. Therefore, it is not possible to verify the expected value of the simulation and the actual measurement value of the defective product with the pattern recognition convenience. For example, since the description of the design information of the memory block is functionally described in HDL (Hardware Description Language) as shown in FIG. 3, it is not easy to take correspondence of signals to be compared. Processing time to form fine holes for actual measurement when tracking the failure point by comparing the actual measurement value of the good product and the actual measurement value of the defective product instead of comparing the expected value of the simulation and the actual measurement value of the defective product. Is doubled, and the time required for failure analysis is significantly increased.

Further, in the LSI in which the functional description and the gate level description are mixed in the description of the design information, since the gate level connection is not defined in the functional block having the functional description, it is necessary in the failure dictionary method mentioned above. With respect to the embedding of the fault data, the fault data other than the stack fault in which the value held in the memory cell is fixed to either 1 or 0 cannot be embedded.

Further, the function of each memory cell can be expressed by a logic gate in which a flip-flop is replaced as shown in FIG. 5. In this case, the wrong address specification of the memory means that the control line of the flip-flop causes a failure. Is to be propagated. The failure diagnosis method based on the inverse logic expansion method described above cannot detect the failure location because the failure propagation path cannot be traced when the control line of the flip-flop fails. That is, it is difficult for the conventional failure diagnosis software to detect a failure location when a failure signal propagates in a memory block having a functional description, except when a specific memory cell has a stack failure.

Further, a CAD tool for observing and verifying the memory contents during execution of a simulation by using a verification tool for memory debugging is commercially available. With this CAD tool, the expectation of the cell held by the address at an arbitrary simulation time is expected. Although a value can be obtained, it has no means for determining whether an erroneous signal has propagated from the address line or the bit line of the memory, so it is difficult to use it as a tool for identifying the location of memory failure.

Software for extracting a netlist from layout data is known. It is also possible to extract a netlist of a memory block using this software and replace the functional description of the memory block with a netlist memory at the transistor level for simulation. It is possible. However, for example, the static RA having a relatively small capacity of 100 kb in the memory of the memory block having the function description is used.
Even in the case of M, the number of transistors is approximately one million, so it takes time to extract all the transistors in the memory block from the netlist.
It is not practical because the transistor level simulation also takes a huge amount of time.

As described above, in the known failure analysis method, an error signal is output at the time of executing a test for accessing a memory block which is hard macrod and has only the function description level information and does not have the gate description level information. In this case, it has been difficult to identify the failure location at a practical cost within a practical time.

An object of the present invention is to extend even to a memory cell of an accessed address inside a memory block even when a memory block which has only a functional description and does not have information at a gate description level exists on a propagation path of a failure signal. It is an object of the present invention to provide a failure analysis support device and a failure analysis method capable of executing in-depth tracking of a failure propagation path with practical labor and time.

[0014]

According to a first aspect of the present invention, there is provided a failure analysis method for a failure analysis method for an LSI having a memory block in which a function is described. And a procedure for specifying a data input / output wiring or signal identifier, and a write control signal and a read control signal at a time corresponding to the test vector each time a test vector for accessing the memory block is detected during the functional simulation of the LSI. And the binary representation of the selected address and the binary representation of the input / output data of the selected address based on the identifier to create an internal state list of a predetermined format, and a fault propagation path of the fault LSI. If the memory block exists in the write control signal, read A control signal, a selected address, the actual value of the input / output data of the selected address, and a corresponding expected value in the internal state list are matched and collated to trace the fault propagation path and identify the fault location. Have

The failure analysis support apparatus of the second invention is a failure analysis support apparatus for an LSI having a memory block having a function description, in which the function description of the memory block is input to write control, read control, address and data input / output. Identifier specifying means for specifying the identifier of the wiring or the signal, and the states of the write control signal and the read control signal at the time corresponding to the test vector each time the test vector for accessing the memory block is detected during the functional simulation of the LSI. And an internal state extracting means for extracting the binary representation of the selected address and the binary representation of the input / output data of the selected address based on the identifier and outputting it as internal state information in a predetermined format.

The failure analysis support program of the third invention is
In a computer program for supporting failure analysis of an LSI having a memory block having a function description, a procedure for inputting the function description of the memory block and specifying write control, read control, and wiring or signal identifier of address and data input / output, and , The state of the write control signal and the read control signal at the time corresponding to the test vector each time the test vector for accessing the memory block is detected during the functional simulation of the LSI, the binary representation of the selected address, and the selected address A procedure for extracting the binary representation of the input / output data based on the identifier and outputting it as internal state information in a predetermined format is executed by the computer.

According to a fourth aspect of the failure analysis method of the present invention, in the failure analysis method of an LSI having a memory block in which a function is described, access to a memory block that has occurred until a failure is output in a functional test and an address to be accessed. The procedure for extracting all of them, and when the trace starts from the data input / output line of the memory block in the layout data and reaches the branch wiring having the branch of the number of word lines or more, the trace is stopped and the branch wiring from the data input / output line. The procedure for extracting the layout data of the route up to and the route from the address input line to the selected word line is specified based on the address input in each access for all accesses, and the branch from the selected word line is performed. The procedure of tracing the layout until it reaches the wiring and extracting the layout data existing in the route A transistor-level netlist of a partial circuit related to a memory cell selected by access is created from the layout data from the input line to the branch wiring and the layout data of the path from the data input / output line to the branch wiring. Failure by using a procedure for synthesizing a partial circuit corresponding to each access to create a replacement transistor level netlist and an LSI design information description in which the functional description of a memory block is replaced with the replacement transistor level netlist. And the procedure for performing analysis.

The failure analysis support apparatus of the fifth invention is an LSI failure analysis support apparatus having a memory block in which a function is described, which accesses a memory block generated before a failure is output in a function test and an address to be accessed. And the access address holding means for extracting all of the data and the data input / output line of the memory block in the layout data, and when the trace reaches the branch wiring having more than the number of word lines, the trace is stopped and the data input / output is performed. After extracting the layout data of the route from the line to the branch wiring, the route from the address input line to the selected word line is specified for all accesses based on the address input in each access. Trace the trace from the word line to the branch line Related to the memory cell selected by access from the route data extracting means for extracting the data, the layout data from the address input line to the branch wiring, and the layout data of the route from the data input / output line to the branch wiring. And a netlist creating means for creating a transistor level netlist of the partial circuits and synthesizing partial circuits corresponding to respective accesses to create a replacement transistor level netlist.

The failure analysis support program of the sixth invention is
In a computer program that supports failure analysis of an LSI having a memory block having a functional description, a procedure for extracting all access to a memory block and an address to be accessed until a failure is output in a functional test, and layout data The trace is started from the data input / output line of the memory block, and when the branch wiring having the number of word lines or more is reached, the trace is stopped and the layout data of the path from the data input / output line to the branch wiring is extracted. For each procedure and all accesses, specify the route from the address input line to the selected word line based on the address input at each access, and trace the route until it reaches the branch wiring from the selected word line. Of the layout data existing in the address input line From the layout data to the branch wiring and the layout data of the path from the data input / output line to the branch wiring, a transistor level netlist of a partial circuit related to the memory cell selected by access is created, and It is characterized by causing a computer to execute a procedure of synthesizing partial circuits corresponding to access to create a replacement transistor level netlist.

[0020]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail with reference to the drawings. In the first embodiment of the present invention, with respect to a memory block whose function is described, write control, read control, address and data input / output wiring or signal identifiers are specified, and at the time of simulation, the simulation time and its time are determined based on these identifiers. The state of the write control line / read control line corresponding to the, the selected address, and the data to be written / read to / from the selected address are extracted and output as a memory block internal state in a predetermined format that can be easily understood by pattern recognition. . Further, in the fault propagation route tracking by measuring the potential of the signal line, when the failure propagation route has a memory block,
The failure is tracked by comparing with the created memory block internal state output.

FIG. 1 is a flow chart of creating an internal state file of a memory block in the first embodiment. Figure 2
FIG. 1 is a block diagram of a system including a failure analysis support device that creates an internal state file.

In FIG. 1, first, in step 100,
The memory capacity (address space) is extracted from the memory block in which the function is described. In the next step 101, the identifiers of the read control line and the write control line are specified from the description of the read control line and the write control line of the memory block. In the next step 102, the identifier of the address signal is identified from the description of the address selected for access. In the next step 103, the identifier of the data input / output signal is specified from the description relating to the input / output of the data of the memory section selected by the address. In step 104, a test vector for accessing the memory block is detected simultaneously with the execution of the functional simulation, and the virtual time (simulation time) in the simulation, the state of the write control line at that time, and the read control are detected correspondingly. The state of the line, the selected address, and the write data to the selected address or the read data from the selected address are extracted based on these identifiers, and regarding the selected address and the input / output data (write / read data) to / from the selected address, The data is converted into a binary number representation in an array order corresponding to the actual arrangement of address lines and data input / output lines in the LSI, and then output as the internal state of the memory block.

Referring to FIG. 2, the failure analysis support device 12
Has an identifier specifying unit 21 and an internal state extracting unit 22. The identifier specifying means 21 parses the function description of the memory block of the LSI in the function description file 10 and specifies the identifier of the wiring or signal to be extracted.
That is, the identifier identifying means 21 extracts the memory capacity from the functional description of the memory block, identifies the identifiers of the read control line and the write control line, identifies the identifier of the address signal, and identifies the data input / output line to the selected address. Identify and save the identifier. The internal state extracting means 22 detects a test vector that accesses a memory block simultaneously with the execution of the simulation in the functional simulator 11, and associates the detected test vector with a virtual time in the simulation and write control at that time. Line state, read control line state, selected address,
The write data to the selected address or the read data from the selected address is extracted based on the identifier information stored in the identifier specifying means, and the selected address and the input / output data (write / read data) to / from the selected address are stored in the LSI. It is converted into a binary number representation in an array order corresponding to the actual arrangement of address lines and data input / output lines, and then output to the internal state file 13. Instead of outputting to the internal state file 13, it may be displayed on a display device or may be directly output to a list on a printer.

The failure analysis support device 12 may be configured as dedicated hardware, but a general-purpose computer, a program having a function corresponding to the identifier specifying means 21, and a program corresponding to the internal state extracting means 22. It can also be realized by using and.

FIG. 3A is an example of an internal state list in which the internal state file 13 thus created is output as a list. Write control line (/ WRI) for each simulation time (/ SIMCLK) measured by the clock
TE) state, read control line (/ READ) state,
Expected values of the selected address (/ ADDR) and the data (/ DATA) input / output from the selected address are output in binary representation. Note that "Z" indicates a high impedance state.

FIG. 3B shows the 8-bit data bus lines DATA_BUS [0] to DATA_BUS of the LSI.
It is a figure which shows an example of the signal potential measurement result of [7]. The wiring with diagonal lines indicates the wiring whose high potential is actually measured. When the high-potential is “1” and the low-potential is “0”, the measurement result of the data bus is expressed in a binary number (10101010).
In the case of the actual measurement result corresponding to the time 110 in (a), it can be easily and clearly determined that the data matches the data (/ DATA). Further, in the case of the actual measurement result corresponding to the time 1210 in FIG. 3A, the data (/ DAT
It can be easily judged that it does not match A).

FIG. 4 is a flow chart of failure analysis. When tracing a fault location using the created internal state list, first, in step 110, a signal line in which fault data has propagated in a signal line outside the memory block is set as a trace target, and traced back from this trace signal line. Trace the failure propagation path. In the next step 111, it is determined whether the traced signal line reaches the memory block. If the memory block is not reached, the process proceeds to step 115, and if the memory block is reached, the process proceeds to step 112. In step 112, the potential of the read control line, the potential of the write control line, and the potential of the address line of the memory block are actually measured using an electron beam tester or the like, and the corresponding simulation is performed using the internal state list output in FIG. It is determined whether or not there is a match by comparing each expected value at time. If they do not match, it is determined that the signal line is in the failure propagation path, and the process proceeds to step 115. If they match, the process proceeds to the next step 113.

In step 113, by referring to the internal state list output in FIG. 3A, the time is traced back to the time when the data held at the selected address designated by the address line is written, and the time is stored in the memory. It is specified as the time when the failure propagated. The potential of the data input signal line (data bus) input to the memory set at this failure propagation time is measured, and the expected value of the input data (/ DATA) at the same time in the internal state list of FIG. A comparison is made to determine whether they match. If they do not match, it is determined that the data input signal line is in the failure propagation path and the process proceeds to step 115.
If they match, the process proceeds to the next step 114. In the next step 114, the potentials of the control lines of the memory block, that is, the read control line, the write control line and the address line at the fault propagation time specified in step 113 are measured, and the internal state output in FIG. In the list, the signal lines that do not match are compared with the respective expected values at the corresponding simulation times, and the signal lines are detected and specified as the failure propagation path, and the process proceeds to step 115.

In step 115, it is determined whether or not the fault propagation path can be further traced back. When the failure propagation path can still be traced, the process returns to step 110 and the tracking of the failure propagation path is repeated again. If the failure propagation path cannot be traced, the failure analysis is terminated assuming that the failure location can be identified.

Next, a memory block of 8 bits × 2048 words is converted into Verilog which is one of the LSI design languages.
-FIG. 5 which describes the function in HDL (Verilog is a registered trademark of Cadence Design Systems, Inc.),
The flow of FIG. 1 will be specifically described with reference to FIG. 6 in which the control for extracting the internal state of the memory block and storing it in the internal state file is described when the functional simulation is executed.

First, in step 100, the structure of the functional block in which the function is described is analyzed, and in the register declaration statement, reg [7: 0] iram8 [0: 11'h
The memory register (memory block) is 8 bits × 2048 words from the description (D100) defined as [7ff].
The character string iram8 sandwiched between the description range designation description is extracted as an identifier assigned to the memory register.

In the next step 101, a read control signal name rd and a write control signal name wr are read from a description (D101) for reading data to a specific address of the memory register iram8 and a description (D101) for writing data to a specific address. And extract.

In the next step 102, the description (D102) for designating the address of the memory block by the array variable,
A for specifying the selection address of the memory register iram8
ADDR that passes address data to ddr_in [10: 0] is extracted as the signal name of the address signal line.

In the next step 103, a description regarding data input / output of the memory register iram8 (D103).
Then, DATA_BUS that the data is transferred between the register that reads the data from the selected address and the register that writes the data to the selected address is extracted as the data signal line name.

A specific example of the processing in the next step 104 will be described according to the output control description in FIG. In step 104, first, the uppermost structure of the design information is written down to specify a read control line, a write control line, an address line, and a data line (D1040). At this time, the data input / output line and the address line are replaced with an array corresponding to the layout of the bus wiring in the LSI. The description of FIG. 6 is an example in which the address lines are arranged in the order of MSB to LSB of the address, and then the data input / output lines are arranged in the order of MSB to LSB of the data. Next, the file is opened by designating the internal state file name (dump_file) for storing the data (D1041), and a variable (clk_count) for measuring a virtual time elapse at the time of simulation is executed as the state information stored in the internal state file.
t) is defined (D1042), the simulation time is first output to the first line of the output file, and then the names of the signal lines are output in a predetermined order (D1043).
Subsequently, the simulation is executed, and each time the simulation progresses, the state information of each signal line extracted based on the simulation time and the identifier is stored in the internal state file in a predetermined order (D1044).

By referring to the internal state list, the address line ADDR at an arbitrary simulation time
The expected value of the binary representation held by [10: 0] can be easily specified, and similarly, the data input / output line DATA_BUS [7: 0] at any simulation time.
It is possible to easily specify the expected value of the binary number expression held by. The selected address of the defective product at the time corresponding to the simulation time is obtained by actually measuring the potential of the address line. Similarly, the write / read data of the defective product at the time corresponding to the simulation time can be obtained by actually measuring the potential of the data input / output line.

In the layout of an LSI, normally, the address lines of the memory blocks are arranged adjacently in parallel in order from the LSB of the address to the MSB or from the MSB to the LSB. Similarly, the data input / output lines of the memory block are arranged in parallel adjacent to each other in order from the LSB of the data to the MSB or from the MSB to the LSB. Therefore, it is usually possible to match the actual arrangement order of the address lines and the data input / output lines with the storage order of the binary number representation information of the address lines and the data input / output lines stored in the internal state file by a simple operation. is there.

In the present embodiment, even when a memory block which has only the functional description and does not have the information of the gate description level exists on the propagation path of the failure signal, the failure propagation path is the control signal or the data input / output. It becomes possible to trace whether there is any. Further, by changing the arrangement order of the expected value of the address line and the expected value of the data input / output line in the internal state list so as to match the actual arrangement order of the address line and the data input line in the LSI, As illustrated in FIG. 3, the comparison between the actual measurement value and the expected value becomes extremely easy, and in tracking the failure propagation path,
Compared with the case where the value held by the signal line is individually verified for each wiring using the expected value file, the labor and time of the tracking work can be significantly reduced.

Next, a second embodiment of the present invention will be described. In the second embodiment, with respect to a memory block whose function is described, a transistor-level netlist is created in which only the address portion accessed in the functional test of the LSI chip is expressed by elements such as transistors and connections between elements. To do. By replacing the memory block of the original functional description with the created transistor-level netlist, it becomes possible to trace the failure using a known failure analysis technique such as a commercially available failure analysis tool.

FIG. 7 is a flow chart for creating a transistor level netlist of only the portion related to the address accessed in the functional test.

In FIG. 7, first, at step 200, the memory address accessed up to the test vector at which a failure is output in the functional test is acquired for each test vector. In the next step 201, the trace of the layout data is started from the data input / output line of the layout data of the LSI chip, and when the power supply line or the ground line is reached, the trace is stopped and another path is traced. Stops the trace when it reaches a wire that has a branch.
When a wiring with more branches than the number of word lines, such as an input line to the read circuit, is reached, this wiring is used as a branch wiring and the layout data of the path from the data input / output line to the branch wiring is extracted and saved. To do.

In the next step 202, step 200
The last accessed address is selected from the addresses extracted in. In the first selection, the address of the memory access that is closest in time to the test vector from which the fault is output will be selected. Next step 20
In step 3, the word line selected from the address selected in step 202 is specified, the trace is started from the specified word line, and when the power line or the ground line is reached, the trace is stopped and another path is traced. To do. The trace is continued in the memory block until the branch wiring stored in step 201 is reached, and the layout data existing in the path is extracted.

In the next step 204, step 202
A transistor level netlist is extracted from the layout data extracted in step 201 and the layout data saved in step 201 to create a netlist of a partial circuit related to the accessed memory cell. The partial circuit includes an address input circuit, a selected word line, a selected memory cell, a write control line, a read control line data input / output line, a write circuit and a read circuit. Next step 205
Then, it is determined whether or not the netlist creation is completed for the access extracted in step 200, and if there are uncreated accesses, the process returns to step 202.
When it is determined that the netlist has been created for all accesses, the process proceeds to step 206. In step 206, all the extracted netlists are combined, the overlapping portions of the plurality of netlists are sorted into one, and a transistor level netlist for replacement is created, and the process ends.

FIG. 8 is a block diagram of a failure analysis support device for creating a transistor level netlist of only the portion related to the address accessed in the functional test.
The failure analysis support device 31 uses the access address holding means 4
1, a route data extracting means 42, and a netlist creating means 43. Access address holding means 41
Extracts the access to the memory block from the function test result 30 to the test vector where the failure is output and holds it together with the memory address of the access target. The route data extracting unit 42 specifies a word line selected from the address input, traces the inside of the memory block to a route until reaching a branch wiring having branches equal to or more than the number of word lines from the specified selected word line. Extract existing layout data. The netlist creating means 43 extracts a transistor level netlist from the extracted layout data, creates a netlist corresponding to the accessed address, and combines a plurality of netlists into one netlist. By using the analysis support device 31 of FIG. 8 and executing the procedure according to the flow of creating the netlist of FIG. 7, a netlist in which only the addresses accessed in the functional test of the LSI chip are described at the transistor level is created. can do.

The failure analysis support device 31 may be configured as dedicated hardware, but it corresponds to a general-purpose computer, a program having a function corresponding to the access address holding means 41, and a route data extracting means 42. It can also be realized by using a program and a program corresponding to the netlist creating means 43.

Next, with reference to FIGS. 9 and 10, a detailed description will be given along the flow chart of FIG. FIG. 9 shows Ve of FIG.
memory block i whose function is described in rilog-HDL
It is a circuit diagram of an address decoder unit of ram8. Eleven address signals ADDR [0] to ADDR [10] select one of the 2048 word lines M0000 to M2047.

FIG. 10 is a circuit diagram showing a portion of bit [0], which is a part of a circuit in which the memory cell of the memory block iram8 whose function is described in FIG. The memory block iram8 has a latch A2048.
And a latch A4096 constitute one memory cell,
Similarly, a total of 2048 memory cells are formed up to the memory cell configured by the latch A 4095 and the latch A 6143. When writing, AND circuits A0000 to A2048
Data_in [0] is written in the memory cell connected to the AND circuit to which the selected word line among the above is input. At the time of reading, data_out [0] is read from the memory cell connected to the buffer circuit activated by the selected word line of the 2048 three-state buffer circuits A6144 to A8191. 9 and 10, CLK is a clock signal, WE is an input control signal, OE is an output control signal, and CS is a memory block control signal.

Hereinafter, description will be made with reference to FIG. 7 using the net names of FIGS. 9 and 10. After extracting all the accessed addresses up to the failure output in step 200, in step 201, the layout data of the LSI chip corresponding to FIG. 10 is traced from DATA_BUS [7: 0] to have a word number branch. When the data_in [0] and M165 are reached, the extraction of the netlist is temporarily stopped. In step 203, the ADDR of FIG.
“0” or “1” of the input of [0] to ADDR [10]
A route for extracting layout data is selected according to
For example, if all address inputs are "0", 2048
Of the 11-input NAND circuits, only the NAND circuit connected to the word line M0000 outputs "1". In this case, the layout data of the memory cells (A2048 and A4096) connected to the word line M0000 is extracted, and tracing is continued to obtain the layout data of the control line and the data input / output line connected to this memory cell. Extract. Trace_i has a word number of branches
The trace is completed when n [0] and M165 are reached.

In step 206, the netlists extracted for all the addresses accessed up to the fault output in the functional test are combined to create a replacement netlist, and then the replacement netlist is further created (not shown). As a step of, the functional verification simulation is executed using this replacement netlist and the design information that replaces the memory block in which the functional description is performed, and it is verified whether the same expected value as the simulation using the functional description can be obtained. Is desirable to justify subsequent failure analysis.

FIG. 11 is a flow chart of failure analysis using the transistor level netlist of the memory block created according to the flow of FIG. First, step 2
At 10, the function description of the memory block is replaced with the transistor level netlist of the created memory block to execute the failure diagnosis software. As fault diagnosis software,
Both the one using the fault dictionary method and the one using the back trace method can be used.

At the next step 211, it is judged whether or not the failure candidate locations are narrowed down to a small number by the failure diagnosis. When the failure diagnosis has narrowed down the failure candidate locations to a small number, the process proceeds to step 212 and the functional information is executed by intentionally changing the design information so that a failure signal is generated at the failure candidate location. In the next step 213, it is judged whether the simulation output matches the actual failure signal output,
If they match, the failure analysis is terminated assuming that the failure location and the failure cause have been identified. If they do not match in step 213, the process returns to step 212, and step 212 is executed for another failure candidate part.

In step 211, if there are a large number of failure candidate locations and the simulation for embedding the failure requires a lot of time, so that it is practically impossible, it is judged as the performance limit of the failure diagnosis software and the failure candidates are judged. Abandoning the narrowing down of the locations and executing the physical failure analysis that traces the failure propagation path while comparing the expected value of the simulation with the actual measurement value to identify the failure location.

In the present embodiment, since the description of the memory cell block can be replaced with the transistor level netlist from the functional description, it is possible to easily and efficiently use known fault diagnosis software including commercial products. It is possible to proceed with failure analysis. In addition, the transistor level netlist is created after extracting only the layout data of the part that is related to the addresses accessed during the functional test, so a complete transistor description netlist of the memory block is extracted and created from all the layout data of the memory block. As compared with the conventional technique used for simulation, the time required to create a netlist can be reduced to about (the number of access addresses / the number of all addresses), and the simulation time can also be shortened. Especially when applied to a memory block having a large memory capacity, these shortening effects become remarkable. Thus, also in the second embodiment,
It is possible to significantly reduce the labor and time in the failure tracking work of the memory block whose function is described.

[0054]

As described above, by applying the present invention, even when a memory block which is only a functional description and does not have information at the gate description level exists on the propagation path of a fault signal, the memory block It becomes possible to carry out the tracing of the fault propagation path that has penetrated to the memory cell of the internally accessed address with practical labor and time.

[Brief description of drawings]

FIG. 1 is a flow chart of creating an internal state file of a memory block according to the first embodiment of the present invention.

FIG. 2 is a block diagram of a system including a failure analysis support device that creates an internal state file.

FIG. 3A is an example of an internal state list,
(B) is a figure which shows an example of a signal potential measurement result.

FIG. 4 is a flow chart of failure analysis.

FIG. 5 is an example of a functional description of a memory block of 8 bits × 2048 words.

FIG. 6 is an example of a control description that extracts an internal state of a memory block and stores it in an internal state file when executing a functional simulation.

FIG. 7 is a transistor level netlist creation flowchart according to the second embodiment of the present invention.

FIG. 8 is a block diagram of a failure analysis support device that creates a transistor-level netlist.

FIG. 9 is a circuit diagram of an address decoder unit of a memory block.

FIG. 10 is a circuit diagram showing a part of a circuit in which a memory cell of a memory block is expressed by a latch.

FIG. 11 is a failure analysis flow chart using a transistor level netlist.

[Explanation of symbols]

12, 31 Failure analysis support device 21 identifier specifying means 22 Internal state extraction means 41 Access address holding means 42 route data extraction means 43 Netlist creation means

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G01R 31/28 F

Claims (6)

[Claims] 1. A failure analysis method for an LSI having a memory block having a functional description, a procedure for specifying a write control, a read control, an address and a data input / output wiring or a signal identifier from the functional description of the memory block, and the LSI. Every time a test vector that accesses the memory block is detected during execution of the functional simulation, the states of the write control signal and the read control signal at the time corresponding to the test vector, and 2 of the selected address.
A procedure for extracting the base number representation and the binary representation of the input / output data of the selected address based on the identifier to create an internal state list of a predetermined format, and the case where the memory block exists in the fault propagation path of the faulty LSI. The write control signal, the read control signal, the selected address, and the actual value of the input / output data of the selected address and the corresponding expected value in the internal state list are matched and collated to trace the fault propagation path and identify the fault location. A failure analysis method, comprising: 2. In a failure analysis support device for an LSI having a memory block having a functional description, the functional description of the memory block is input, and write control, read control, address and data input / output wiring or signal identifiers are specified. The identifier specifying means, the states of the write control signal and the read control signal at the time corresponding to the test vector each time the test vector that accesses the memory block is detected during the functional simulation of the LSI, and the selection address
A failure analysis support device, comprising: an internal state extraction means for extracting a binary number representation and a binary number representation of input / output data of the selected address based on the identifier and outputting as internal state information in a predetermined format. . 3. A computer program for supporting failure analysis of an LSI having a memory block having a functional description, the functional description of the memory block is input, and write control, read control, address and data input / output wiring or signal identifiers are input. Of the write control signal and the read control signal at the time corresponding to the test vector each time the test vector for accessing the memory block is detected during the functional simulation of the LSI, and the selection address
A failure analysis support program for causing a computer to execute a procedure of extracting a binary expression and a binary expression of input / output data of the selected address based on the identifier and outputting the internal status information in a predetermined format. . 4. In a failure analysis method for an LSI having a memory block having a functional description, a procedure for extracting all access to a memory block and an address to be accessed until a failure is output in a functional test, and layout data. In the case of starting the trace from the data input / output line of the memory block and stopping the trace when reaching the branch wiring having the number of word lines or more, the layout data of the path from the data input / output line to the branch wiring is extracted. Procedure, and for all accesses, specify the route from the address input line to the selected word line based on the address input in each access, and trace it until it reaches the branch wiring from the selected word line. A procedure for extracting layout data existing in a path, and branching from the address input line. Creates a transistor-level netlist of the partial circuit related to the memory cell selected by access from the layout data up to the line and the layout data of the path from the data input / output line to the branch wiring, and supports each access And a procedure for synthesizing a partial circuit for creating a replacement transistor level netlist, and a procedure for analyzing a failure using the design information description of the LSI in which the functional description of the memory block is replaced with the replacement transistor level netlist. A failure analysis method comprising: 5. A failure analysis support device for an LSI having a memory block having a function description, access address holding means for extracting all access to a memory block that has occurred until a failure is output in a function test and an access target address. When the trace is started from the data input / output line of the memory block in the layout data and the branch wiring having the branch of the number of word lines or more is reached, the trace is stopped and the path from the data input / output line to the branch wiring is changed. After extracting the layout data, for all accesses, the path from the address input line to the selected word line is specified based on the address input in each access, and the branch wiring is reached from the selected word line. Route data extractor that traces up to and extracts layout data that exists on the route And a transistor-level netlist of a partial circuit related to a memory cell selected by access from layout data from the address input line to the branch wiring and layout data of a path from the data input / output line to the branch wiring. And a netlist creating means for creating a replacement transistor level netlist by synthesizing partial circuits corresponding to respective accesses, and a failure analysis support device. 6. A computer program for supporting failure analysis of an LSI having a memory block having a function description, a procedure for extracting all accesses to a memory block generated before a failure is output in a functional test and addresses to be accessed. When the trace is started from the data input / output line of the memory block in the layout data and the branch wiring having the branch of the number of word lines or more is reached, the trace is stopped and the path from the data input / output line to the branch wiring is changed. For the layout data extraction procedure and for all accesses, specify the route from the address input line to the selected word line based on the address input at each access, and reach the branch wiring from the selected word line. The procedure to trace and extract the layout data existing in the route, A transistor level netlist of a partial circuit related to a memory cell selected by access is created from layout data from an address input line to the branch wiring and layout data of a path from the data input / output line to the branch wiring. , A failure analysis support program for causing a computer to execute a procedure for synthesizing partial circuits corresponding to respective accesses and creating a replacement transistor level netlist.