JP2000250946A - Method and device for test facilitating design of lsi circuit and computer-readable recording medium where test facilitating design processing program is recorded - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the chip size from increasing as much as possible and to obtain a high fault detection rate by providing a means which obtains the fault detection rate and fault stop information relating to signal lines and a means which determines a test point insertion point according to the fault detection rate and fault stop information. SOLUTION: A fault simulation part 31 inputs test patterns to the LSI circuit and performs fault simulation, and fault stop information relating to the respective signal lines is recorded and held in the corresponding fault stop information list as the accumulated value of the patterns. The fault simulation part 33 obtains fault detection rate from detected faults. Then an insertion effect evaluation part 34 evaluates whether more faults than determined are newly detected and the fault detection rate is improved. Consequently, when the fault detection rate is improved, selected signal lines are registered in a test point insertion point list 35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for designing a testable LSI circuit, and a computer-readable recording medium storing a testable design processing program.

[0002]

2. Description of the Related Art In general, the work of creating a test pattern for testing a large-scale and complicated LSI circuit occupies a large part of the LSI design period. Usually, a combination that increases the fault detection rate is selected from the test patterns created for design function verification and used in manufacturing tests in many cases.
In this case, the problem is that the quality of the selected test pattern often does not reach the failure detection rate considered to be sufficient for the manufacturing test. The test pattern is created on the basis that each function operates as designed, but this is different from the criterion on whether a failure in the circuit is detected. In a large-scale circuit, it takes an enormous amount of time to execute a fault simulation for finding a fault detection rate.Therefore, a fault simulation is performed by sampling faults, and an activation rate of each signal obtained by a logic simulation is also reduced. And select a pattern. In these cases, the failure detection rate cannot be obtained accurately.

[0003] Design for testability (hereinafter referred to as DFT (Design
gn For Testability)
Is to improve the testability of the LSI circuit by adding a test circuit as small as possible to the LSI circuit, and to optimize the test pattern creation period, test pattern size, test time, and final failure detection rate. Technology.

One of the design techniques for testability is as follows.
Scan design is widely known. In this scan design, as shown in FIG. 16, all registers 95 (flip-flops or latches) in a sequential circuit (a circuit whose output is determined by an input and an internal state of the circuit) are replaced with a special register called a scan register. , 1
It is configured to be serially connected as one or more shift registers. In FIG. 16, reference numeral 90 denotes a combinational circuit (a circuit whose output is determined only by an input) of a semiconductor integrated circuit device, 91 denotes an external input terminal, 92 denotes an external output terminal, 96 denotes a shift input terminal, and 97 denotes a clock input. , 98
Is a shift output terminal. By using the scan register in this manner, control and observation of the register inside the circuit, which is normally difficult, can be performed by the external input terminal 91 and the external output terminal 9.
2, serial input 96, and serial output 98. This greatly simplifies the task of creating test patterns. In particular, automatic test pattern generation means by a program (ATPG: Autom
atic Test Pattern Generat
(ion), a test pattern having a high failure detection rate can be created in a short period of time.

An advantage of the scan design is that all registers can be directly controlled and observed, so that a sequential circuit can be virtually treated as a combinational circuit. However, due to an increase in the circuit scale and the complexity of the circuit, the scale of the combinational circuit part is increased or complicated, and the processing by the program requires time. In addition, when a partial scan method in which only some registers are replaced with scan registers is used to suppress an increase in circuit area, test patterns are created in consideration of the sequential operation of registers not replaced with scan registers. Must be performed, so that the pattern creation time increases. In addition, the processing time for automatic test pattern generation increases, and a pattern having a sufficient failure detection rate cannot be created.

In such a case, it is necessary to improve the testability by changing the structure of the logic circuit other than the register in the circuit. Among such methods, a method of inserting a test point for improving testability of an internal signal line has been widely used.

The two main concepts used to evaluate and improve the testability of a circuit under test are controllability and observability. Controllability is a measure of the difficulty in setting a signal line to the value required to activate a fault, and observability is a measure of the difficulty in propagating the effects of a fault signal from a signal line to an external output. It is. Controllability affects not only activation of a fault, but also difficulty in setting a certain signal line to a value required for fault propagation. It is often difficult to set the signal to 1 as an index of controllability and observability of each signal line (1-controllability: 1-c
(controllability), difficulty of making signal 0 (0-controllability: 0-controllability)
y), and difficulty in observing the effect of the fault from the signal line to the external output (observability: observability). In some cases, the difficulty is estimated based on the experience of the designer, but it can also be obtained as actual numerical values by a method called testability analysis.

The testability analysis is a static analysis (Static Testab) that analyzes the testability of each signal based on only the structural information of the circuit without using an input pattern.
dynamic analysis (Dynam) for inputting a certain test pattern to a circuit and observing the behavior of each signal line to obtain controllability and observability.
ic Testability Analysis),
It is classified into a method of specifying a signal line in which it is difficult to detect a failure by actually applying the ATPG to a circuit.

Here, a typical static testability analysis method called SCOAP will be described. SCO
0 controllability of AP in the signal line X, respectively 1-controllability and observability of the CC ⁰ (X), expressed in ^{CC 1 (X), CO (} X). CC ⁰ (X) = CC when signal line is external input
¹ (X) = 1, and CO (X) = 0 at the time of external output. By transmitting these values, controllability and observability of all the internal signal lines are finally obtained. As for the two-input element (input X, Y, output X), FIG.
The propagation is performed in the form shown in FIG. Using these propagation equations,
FIG. 18 shows the controllability and the observability of each signal line of a certain circuit. In FIG. 18, for example, (1, 1, 9) displayed on one input signal line of the exclusive OR gate 101 is such that the first numeral (= 1) is 0 of the signal line.
The second number (= 1) indicates the 1-controllability of the signal line, and the third number (= 9) indicates the observability of the signal line. As can be seen from FIG. 18, the closer the signal line is to the input side, the better the controllability (lower value), and the closer to the output side, the better the observability (lower value).

Although more algorithms have been developed for static analysis than before, there is a problem in that it is difficult to reflect the reconvergence of the signal (a state in which a signal that has branched once merges later) into a value. For example, in the circuit shown in FIG. 19, the 1-controllability of the output of the final gate 112 of the circuit is calculated to be 7, but since this output cannot be controlled to 1, this value has no meaning. Several algorithms have been proposed to make corrections to take into account reconvergence, but none are sufficient. In general, static testability analysis is not considered a reliable indicator.

In the dynamic analysis, since the behavior of the signal line is observed using a test pattern generated from the ATPG, the controllability is higher in accuracy than the static analysis. However, the observability must be obtained only from the structure of the circuit and the state of the signal line in the middle, and is similar to the static analysis in that reconvergence cannot be accurately reflected. The analysis using the ATPG has the highest accuracy, but is generally not performed when the analysis must be repeated because the execution time is long.

As a result of the testability analysis, a signal line with low controllability can be improved by inserting a test point for improving controllability. As shown in FIG. 20B, a two-input AND element 123 is inserted into the signal line 121 with low 0-controllability of the circuit shown in FIG. By fixing the test external input 122 to the logical value 1, the signal line 124 can be controlled to 0. However, since the failure of the logic block 121 cannot be observed with the fixed state, the signal line 122 is set to 0 during the test.
/ 1 needs to be controlled so as to take both values. FIG.
For the signal line 133 with low observability (FIG. 21A)
), And an observation test point 134 is inserted (see FIG. 21B). The test point 134 may be an external output signal or an internal signal that can be controlled and observed (for example, a scan register).

FIG. 22 shows a flow of the test point insertion work. A failure simulation (see step F32) is performed using the created test pattern (see step F31). If the detection rate does not reach the target value, a testability analysis is performed (steps F33 and F33).
F34), candidates are extracted (see step F35), and test points are inserted (see step F36). From now on, the work of calculating the failure detection rate by the failure simulation again (see step F32) and creating a test pattern (see step F31) must be repeated until the detection rate reaches the target value. At this time, if the accuracy of the testability analysis is low, an enormous amount of work time may be required to obtain the target detection rate, or the target may not reach the target. Further, the analysis by the ATPG with high accuracy requires a long execution time, so that the work time may be further increased in a large-scale circuit. The fact that each of these processes is a separate program or manual work further complicates the work.

Another design method for testability of a logic circuit is a logic BIST (Build-In Se).
(lf TEST) or built-in self-test. The BIST automatically generates a test pattern to be applied to a test block and analyzes a test result output from the test block, all automatically by a logic circuit arranged around the test block.

FIG. 23 is a general block diagram of a BIST. The semiconductor integrated circuit including the block under test 155 is set to the test mode by the external input signal 151a for setting the test mode. As a result, the input / output of the test block is connected to a test input / output signal different from that in the normal operation. After initializing the BIST circuit, a self-test is executed by inputting a predetermined number of BIST clocks. Tested block 1 during self test
Input 153 to 55 is automatically generated by test pattern generator 152. The test result output 156 from the block under test is input to the test result analyzer 157, and is compared with an expected value one by one or converted into data (signature) of a specific pit length. Finally, the test analysis result 158 of the block under test 155
Is output, and the quality is determined by a test.

In the test by the BIST, it is not necessary to prepare a test pattern on an external tester memory, and the cost of the tester is reduced. All operations are BIST
In order to perform in the device in synchronization with the clock, BIST
If the clock can be operated at a high speed, a test at an operation speed higher than the test operation frequency by the tester becomes possible. As a result, a product test in actual operation can be performed. Further, since only a small number of test external input / output signals are required in the BIST test, a plurality of blocks can be tested in parallel. As a result, the entire test time can be significantly reduced.

In the logic BIST, LFSR (Linear Feedback Shi) is used for normal pattern generation.
ft Register) or a pseudo-random pattern generator. However, with a random pattern, it is difficult to reach the target failure detection rate even if the number of patterns is spent. Therefore, test points are generally inserted in the logic BIST. At this time, testability analysis is also performed for selecting a test point. However, testability based on a random pattern has a different meaning from analysis based on ATPG. For example, N input AND
If one wants to set the output of a device to a logical value of one, all of its inputs must be set to one. That is, 1-controllability in the random number pattern is 1/2 ^N in probability, and is very low if N is large. However, in ATPG, N
In this case, it is not possible to say that 1-controllability is low because a pattern in which all the inputs are set to 1 can be found immediately. Under the situation of random number pattern generation, the controllability and the observability are reworded as follows: 1-controllability (0-controllability) is obtained by changing the value of a signal line having a randomly given test pattern input. The probability set to 1 (0), and the observability of a signal line is the probability that a randomly applied test pattern input will activate one or more paths from that signal line to an external output.

A fault simulation is performed with random input, and a test point candidate can be selected by extracting low controllability or low observability from the fault detection state. It is difficult to determine the order. In particular, it is difficult to quantify the observability by using only the failure detection information in the failure simulation.

[0019]

As described above,
When all the registers in the sequential circuit are replaced with scan registers, there is a problem that the chip size becomes large.

Further, when only some of the registers are replaced with scan registers, a problem arises in that it is difficult to accurately determine a failure detection rate.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has an LSI testability design method and apparatus capable of preventing an increase in chip size as much as possible and obtaining a high failure detection rate. It is another object of the present invention to provide a computer-readable recording medium in which a testability design processing program is recorded.

[0022]

SUMMARY OF THE INVENTION According to the present invention, a method for designing a testable LSI circuit is provided for testing a model circuit constructed on a computer having the same configuration as a circuit having a plurality of logic elements and a plurality of signal lines. Inputting a pattern and performing a fault simulation to obtain a fault coverage and fault prevention information associated with each of the plurality of signal lines; and determining a test point insertion point based on the fault coverage and the fault prevention information. And step.

The failure prevention information is the first failure prevention information, that is, the accumulated value of faults that have been propagated to the corresponding signal line but are not propagated to the output of the logic element to which this signal line is input. Preferably, there is.

In the step of determining the test point insertion point, it is determined whether or not the obtained fault detection rate is sufficient. If it is, the process is terminated. Extracting test point insertion candidates from the plurality of signal lines based on the failure prevention information; determining whether there are test point insertion candidates; extracting test point insertion candidates if there are no candidates Returning to the step of selecting, if there is a candidate, selecting at least one candidate, virtually inserting a test point into the selected candidate, and then selecting a model circuit in which the test point is virtually inserted. Inputting a test pattern and performing a second failure simulation to determine failure detection.

The failure prevention information further includes the second failure prevention information, that is, the corresponding signal line among the failures transmitted to the other input signal lines of the logic element to which the corresponding signal line is input. The step of inserting a virtual test point is a cumulative value of faults not propagated to the output of the logic element, and the step of virtually inserting the test point into the selected candidate is an observation test point or It is preferable that the method further comprises a step of determining whether or not the test point is a service test point based on the second failure prevention information.

It is preferable that the second fault simulation is performed for faults other than faults that have already been detected.

Further, according to the present invention, there is provided an LSI circuit testability designing apparatus which inputs a test pattern into a model circuit constructed on a computer having the same configuration as a circuit having a plurality of logic elements and a plurality of signal lines. A failure simulation unit for performing a failure simulation to determine a failure detection rate and failure prevention information related to each of the plurality of signal lines; and a test point insertion determining a test point insertion point based on the failure detection rate and the failure prevention information. And a point determining unit.

According to the present invention, there is provided a computer-readable recording medium on which a testability design processing program is recorded, wherein a model circuit constructed on a computer has the same configuration as a circuit having a plurality of logic elements and a plurality of signal lines. A procedure for inputting a test pattern and performing a fault simulation to obtain a fault detection rate and fault prevention information related to each of the plurality of signal lines, and a test point insertion point based on the fault detection rate and the fault prevention information. The decision procedure is recorded.

In the procedure for determining the test point insertion point, it is determined whether or not the obtained fault detection rate is sufficient. If it is, the process is terminated. Extracting test point insertion candidates from the plurality of signal lines based on the failure prevention information;
A procedure for determining whether there is a test point insertion candidate,
If there is no candidate, the procedure returns to the step of extracting test point insertion candidates. If there is a candidate, at least one candidate is selected, and a test point is virtually inserted into the selected candidate. Inputting a test pattern to the model circuit into which the test points are virtually inserted, and performing a second fault simulation to obtain a fault detection rate.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a method for designing a testable LSI circuit according to the present invention will be described with reference to FIGS. FIG. 1 shows a processing procedure of the testability design method of the first embodiment, and FIG. 2 shows a configuration of an apparatus for realizing the design method.

First, as shown in step F1 of FIG.
Circuit information, that is, a plurality of signal lines, a plurality of elements, and connection information between the signal lines and the elements are input, whereby a model circuit is constructed on a computer. The circuit information is input by the design database construction unit 22 based on the design description 21 shown in FIG. 2, and the model circuit is constructed and stored in the model circuit design database 23.

Next, a test point insertion processing unit 30 is added to the model circuit stored in the design database 23.
The random simulation pattern is generated by the failure simulation unit 31 in the above, and the failure simulation is executed (see step F2 in FIG. 1). At this time, the design conditions relating to the processing such as the number of patterns, the final target failure detection rate, the maximum value of the pattern length given at the time of the test, and the upper limit of the number of test points that can be inserted are set in the target condition input unit 28 of FIG. Has been entered in advance.

The fault simulation is performed for both a normal circuit having no fault and a circuit having a fault (fault circuit).
Each output response to the same input pattern is calculated, and if the faulty circuit responds differently even at one point from the normal circuit, the fault can be detected, and if it responds exactly the same, it cannot be detected.

In the present embodiment, during the execution of the fault simulation, information on the point where the propagation of the fault is stopped is stored for each signal line in the circuit. For example, in the circuit having the two-input AND gate 6 shown in FIG. 3, the fault propagation information propagated to the input signal lines 2 and 4 of the AND gate 6 is the fault propagation information list 12,
The fault propagation information, which is stored in each of the error propagation information 14 and propagated to the output signal line 8, is stored in a fault propagation information list 18.
Even if a fault propagates to one of the input signal lines 2 of the AND gate 6, if the logical value of the signal on the other input signal line 4 is "0", the fault will be transmitted to the output signal line 8. The number of faults that have been blocked and no longer propagated is added to the column corresponding to the signal line 2 in the fault blocking information list (not shown). The number of the faults is added and recorded each time the signal is blocked, so that the signal line whose frequency is frequently blocked is recorded in the failure blocking list associated with the signal line. Information based on existing failure prevention information.

Next, the failure simulation unit 3 shown in FIG.
1 confirms whether or not the failure detection rate obtained by executing the failure simulation has reached the target failure detection rate (see step F3 in FIG. 1). Based on the data recorded in the related failure prevention list, a plurality of test point insertion candidates are extracted from the signal lines (step F6 in FIG. 1).
And the extracted candidates are stored in the test point candidate list 32.
Store inside. If not, the process proceeds to step F4. The contents of step F4 will be described later.

The extraction of the test point insertion candidate will be described by taking the LSI circuit 40 shown in FIG. 4 as an example. This L
The SI circuit 40 includes a logic circuit 41, a logic circuit 48, and logic elements 42, 43,
44, 45 and signal lines 42a, 42b, 43a, 43
b, 44a, 44b, 45a, 45b.
The failure simulation unit 31 inputs a plurality of test patterns to the LSI circuit 40 and performs a failure simulation. Failure prevention information related to each signal line is included in a corresponding failure prevention information list as a cumulative value over a plurality of patterns. Records are kept.

FIG. 5 shows the recorded failure prevention information. The obtained failure prevention information is rearranged by the failure simulation unit 31 in descending order of the number of times the failure has been prevented. FIG. 6 shows the rearranged result. On the basis of the rearranged result, a predetermined number of signal lines or the number of signal lines in which the number of times of failure prevention is greater than a predetermined number are determined in step F6 shown in FIG. The test point candidate is extracted and stored in the test point candidate list 32.

Next, the failure simulation unit 33 in the test point insertion processing unit 30 determines whether or not there is a candidate which is held in the test point candidate list 32 and whose test point insertion effect is not evaluated.
A search is performed (see step F7 in FIG. 1). If no candidate exists, the process returns to step F3 and the above steps are repeated. When the repetition reaches a predetermined number of times, all the processes are terminated. When there is a candidate, one signal line is selected from the candidates by the failure simulation unit 33 (see step F8 in FIG. 1).

Then, a test point is virtually inserted into the selected signal line by the fault simulation unit 33, and a fault simulation is executed (see step F10 in FIG. 1). The failure simulation here is performed for failures other than the failures already detected (faults stored in an undetected failure list (not shown)). For this reason, the execution time is shortened each time the failure simulation of step F10 is repeated.

The result of the failure simulation in step F10 is evaluated by the insertion effect evaluation section 34 shown in FIG. This evaluation is performed as follows. First, by the above-described failure simulation, the insertion effect evaluation unit 34 evaluates whether or not a failure beyond a predetermined level is newly detected and the failure detection rate is improved (step F in FIG. 1).
11). If the signal line is improved, the selected signal line is registered as a test point insertion point in the test point insertion point list 35 by the insertion effect evaluation unit 34 (see step F12 in FIG. 1).
And the above processing is repeated. The failure detection rate is determined by the failure simulation unit 33 from the failures detected up to this point. If not improved, the selected signal line is excluded from the test point insertion candidates by the insertion effect evaluation unit 34, and thereafter, the process returns to step F7 to repeat the above-described processing.

When the test point insertion candidate no longer exists and the fault detection rate becomes equal to or higher than the target value, a test point insertion unit is added to the signal line registered as the test point insertion point in order to improve observability. 36, an observation test point is inserted (step F4 in FIG. 1).
), And the model circuit after insertion is the design database 2
3 recorded. Then, this design database 23
The circuit information is output as the design description 25 by the design description creating unit 24 based on the model circuit recorded in the step S5 (see step F5 in FIG. 1).

As described above, according to the present embodiment, the test point is inserted only into the signal line whose fault detection rate is improved, so that the chip size can be prevented from increasing as much as possible. . Further, the failure detection rate can be accurately obtained.

In the first embodiment, only the information on which the failure has been prevented (first failure prevention information) has been obtained and stored in each signal line. It is possible to improve the accuracy of the detection rate. For example, a 4-input AND gate 5 shown in FIG.
At 0, the input signal lines 50a and 50b have the logical value "0".
In this state, most of the faults that have propagated to the input signal line 50d at this point are prevented here. At this time, as in the case of the first embodiment, the input signal line 5
Add “the number of faults that have been propagated and blocked” to “the number of times the fault has been blocked” held in the fault blocking information list of 0d, and use the added result as the first fault blocking information. The information is recorded and held in the failure prevention information list. Further, for the input signal lines 50a and 50b, the accumulated value of the "number of times the failure was prevented" is recorded and held as the second failure prevention information in the failure prevention information list of each of the signal lines 50a and 50b. After giving a certain number of patterns, the second failure prevention information is analyzed. For example, if the number of failures prevented by the signal line 50a is larger than that of the other signal lines, the signal line 5
0a is 1-a candidate for test point insertion for improving controllability. If there are many faults blocked by the signal lines 50b, 50c, and 50d, and many faults blocked by the signal line 50a, the signal lines are more likely to be inserted into the signal lines 50b, 50c, and 50d than by inserting test points for observation. It is considered that inserting a 1-control test point into 50a is more effective.

A case where the first and second failure prevention information are recorded and held will be described as a second embodiment of the present invention.

A second embodiment of the design method for testability of an LSI circuit according to the present invention will be described with reference to FIGS. FIG. 8 shows a processing procedure of the testability design method of the second embodiment, and FIG. 9 shows a configuration of an apparatus for realizing this design method.

The processing procedure of the design method of the second embodiment is the same as that of the design method of the first embodiment shown in FIG. 1 except that steps F8a and F8b are provided between steps F8 and F9. , F8c are inserted. In response to this, the test point insertion processing unit 30A of the device shown in FIG. 9 includes a test point type selection unit 37 in the test point insertion processing unit 30 of the device shown in FIG.
The failure list reconstructing unit 38 is newly provided.

In the design method of the second embodiment, unlike the first embodiment, during execution of the failure simulation in step F2, the failure prevention information list corresponding to each signal line includes The first and second failure prevention information described above are recorded and held.

Next, the operation of the second embodiment will be described.
Steps up to step F8 are performed in the same manner as in the first embodiment. Subsequently, an observation test point is inserted into the selected signal line or propagated on the selected signal line based on the first and second failure prevention information relating to the signal line selected as a candidate. Whether to insert a control test point into another signal line that prevents the failure is selected by the test point type selection unit 37 shown in FIG. 9 (see step F8a in FIG. 8).

The selection of the type of the test point will be described by taking the LSI circuit 50 shown in FIG. 10 as an example. The LSI circuit 50 includes logic circuits 51 and 52 and logic elements 52 and 53 provided between the logic circuits 51 and 52.
54, 55 and signal lines 52a, 52b, 53a, 53
b, 54a, 54b, 55a, 55b, 55c, 55d
And The failure simulation unit 31 inputs a plurality of test patterns to the LSI circuit 50 to perform a failure simulation, and records first and second failure prevention information related to each signal line in a corresponding failure prevention information list. Will be retained. FIG. 11 shows the first and second failure prevention information recorded and held. The first and second pieces of fault prevention information are rearranged by the fault simulation unit 31 in the order of the number of times the fault was stopped and in the order of the number of times of the faults, and the rearranged results are shown in FIG. 12 and FIG. As shown in FIG.

Based on the first failure prevention information obtained in this way, a predetermined number of signal lines whose number of failures has been prevented or a signal line whose number of times of failure exceeds a predetermined value are tested. The failure simulation unit 31 selects a point insertion candidate (see step F8 in FIG. 8). In the circuit 50 shown in FIG.
From the list of the first failure prevention information shown in FIG.
Is selected as a candidate. Subsequently, among the input signal lines of the element 55 for preventing a failure on the selected signal line 55a, the signal lines 55d and 55b are positioned higher in the list of the second failure prevention information shown in FIG. Therefore, insertion of a control test point for virtually improving 0-controllability into these two signal lines 55d and 55b is selected by the test point type selection unit 37 (see step F8a in FIG. 8). ). The circuit 5 shown in FIG.
At 0, the control test point was selected,
An observation test point may be selected depending on the second failure prevention information.

After the type of the test point is selected in this way, if the selected test point is for observation, the process proceeds to step F9, and the same processing as that described in the first embodiment is performed. Will be If the selected test point is for control, a new gate element is inserted on the signal line, so even if a fault has already been detected, it can be detected by inserting the gate element. Some things may no longer be available. For this reason, the parts affected by the insertion of the gate element are analyzed by the failure list reconstructing unit 38 shown in FIG. 9, and the failures in these parts are not detected again, and the undetected failure list is reconfigured. (See step F8c in FIG. 8). Thereafter, the process proceeds to step F9, and the same processing as the processing after step F9 described in the first embodiment is performed.

As described above, in the second embodiment, more detailed failure prevention information is obtained and recorded and held by the failure simulation than in the first embodiment, so that less tests are performed. High fault coverage can be obtained by inserting points. Therefore, an increase in chip size can be prevented as much as possible.

In the second embodiment, when the control test point is selected, the undetected fault list is reconstructed. However, since the fault simulation in step F10 is repeatedly executed, the undetected fault list is re-executed. The fault is not considered (that is, the undetected fault list is not reconstructed), and when the test point insertion candidates are exhausted (No in step F7), the process returns to step F2 and a new fault simulation is performed. You may comprise. By doing so, the processing time can be reduced.

In the design method for testability according to the first embodiment, the processing procedure from step F1 to step F12 shown in FIG. 1 is used, and in the design method for testability according to the second embodiment, The processing procedures from step F1 to step F12 shown in FIG. 8 are each performed as a recording medium (for example, a CD-ROM, a magneto-optical disk, or a DVD (Digital Versatile D)) as a program.
disk), a floppy disk, a memory card, etc.).

This recording is performed as follows. First, as shown in FIGS. 14 and 15, the computer 80 is started up, and the recording medium (FD 92 or C in FIG. 14) is started.
The D-ROM 94) is set in a recording device (the FD drive 81 or the CD-ROM drive 82 in FIGS. 14 and 15). Subsequently, the input means 84 (for example, the keyboard 8
For example, in the case of the first embodiment, the processing procedure from step F1 to step F12 shown in FIG. 1 is sequentially input as a program using the mouse 4a or the mouse 84b). Then, the input program is written on a recording medium by a CPU (not shown) of the computer 80. At the time of this writing, the display device 86 and the printer 87
It is convenient to use.

The case of executing the program for the testability design processing procedure recorded on such a recording medium will be described. First, a recording medium on which the testability design processing procedure is recorded as a program is set in a reading device (the FD drive 81 or the CD-ROM drive 82 in FIG. 15). Subsequently, the programs are sequentially read from the recording medium by the CPU of the computer 80 connected to the reading device and loaded into the internal memory of the computer 80. Thereafter, when the circuit information is input using the reading device and the target conditions and the like are input via input means, the programs are sequentially read and executed.

[0057]

As described above, according to the present invention, an increase in chip size can be prevented as much as possible, and a high fault detection rate can be obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure of a first embodiment of a testability design method according to the present invention.

FIG. 2 is a block diagram showing a configuration of a design apparatus for implementing the testability design method according to the first embodiment;

FIG. 3 is a schematic diagram for explaining a main point of the first embodiment.

FIG. 4 is a circuit diagram used to explain the operation of the first embodiment.

FIG. 5 is a diagram showing failure prevention information according to the present invention.

FIG. 6 is a diagram in which the failure prevention information shown in FIG. 5 is rearranged in descending order of the number of times failures are prevented.

FIG. 7 is a schematic diagram for explaining the gist of the second embodiment of the testability design method according to the present invention.

FIG. 8 is a flowchart showing a processing procedure according to the second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a design apparatus for implementing the testability design method according to the second embodiment;

FIG. 10 is a circuit diagram used to explain the operation of the second embodiment.

FIG. 11 is a diagram showing first and second failure prevention information obtained by the second embodiment.

FIG. 12 is a diagram in which first failure prevention information is rearranged in descending order of the number of times failures are prevented.

FIG. 13 is a diagram in which second failure prevention information is rearranged in descending order of the number of times failures are prevented.

FIG. 14 is a perspective view illustrating a configuration of a computer device.

FIG. 15 is a block diagram illustrating a configuration of a computer device.

FIG. 16 is a view for explaining scan design.

FIG. 17 is a diagram showing controllability and the propagation equation of observation in SCOAP.

FIG. 18 is a diagram illustrating a calculation example of controllability and observability.

FIG. 19 is a diagram showing a calculation example of controllability and observability.

FIG. 20 is a diagram illustrating insertion of a control test point.

FIG. 21 is a diagram illustrating insertion of observation test points.

FIG. 22 is a flowchart showing a procedure of a conventional test point insertion process.

FIG. 23 is a block diagram showing a general configuration of a BIST.

[Explanation of symbols]

 21 Design Description 22 Design Database Construction Unit 23 Design Database 24 Design Description Creation Unit 25 Design Description 28 Target Condition Input Unit 30 Test Point Insertion Processing Unit 31 Failure Simulation Unit 32 Test Point Candidate List 33 Failure Simulation Unit 34 Insertion Effect Evaluation Unit 35 Test Point insertion point list 36 Test point insertion unit 37 Test point type selection unit 38 Failure list reconstruction unit

Claims (8)

[Claims] 1. A failure simulation is performed by inputting a test pattern to a model circuit constructed on a computer having the same configuration as a circuit having a plurality of logic elements and a plurality of signal lines, and a failure detection rate and the plurality of signals are provided. Determining test failure insertion information associated with each of the lines; and determining a test point insertion point based on the failure detection rate and the failure prevention information. Method. 2. The failure prevention information has been propagated to first failure prevention information, that is, a corresponding signal line.
2. The signal L according to claim 1, wherein the signal line is a cumulative value of faults that are not propagated to an output of a logic element input thereto.
Design method for testability of SI circuit. 3. The step of determining the test point insertion point includes determining whether or not the obtained fault coverage is sufficient. If it is, the process is terminated. Extracting test point insertion candidates from the plurality of signal lines based on the failure prevention information; determining whether there are test point insertion candidates; extracting test point insertion candidates if there are no candidates Returning to the step of selecting, if there is a candidate, selecting at least one candidate, and virtually inserting a test point into the selected candidate; 3. The method according to claim 2, further comprising: inputting a test pattern and performing a second fault simulation to obtain a fault detection rate. Design method for testability of SI circuit. 4. The failure prevention information further includes second failure prevention information, that is, the corresponding signal line among the failures propagated to another input signal line of the logic element to which the corresponding signal line is input. The cumulative value of faults not propagated to the output of the logic element, wherein the step of virtually inserting the test point includes the step of controlling whether the test point to be virtually inserted into the selected candidate is an observation test point. 4. The method for designing a testable LSI circuit according to claim 3, further comprising the step of determining whether the test point is a test point for use based on the second failure prevention information. 5. The method for designing a testable LSI circuit according to claim 3, wherein the second fault simulation is performed for faults other than faults already detected. 6. A failure simulation by inputting a test pattern to a model circuit constructed on a computer having the same configuration as a circuit having a plurality of logic elements and a plurality of signal lines, performing a failure detection rate and the plurality of signals. A failure simulation unit for obtaining failure prevention information related to each of the lines; and a test point insertion point determination unit for determining a test point insertion point based on the failure detection rate and the failure prevention information. Design equipment for testability of LSI circuits. 7. A fault simulation is performed by inputting a test pattern to a model circuit constructed on a computer having the same configuration as a circuit having a plurality of logic elements and a plurality of signal lines, and performing a fault detection rate and said plurality of signals. A test facilitation design processing program for causing a computer to execute a procedure for obtaining failure prevention information related to each of the lines and a procedure for determining a test point insertion point based on the failure detection rate and the failure prevention information is recorded. Computer readable recording medium. 8. The procedure for deciding the test point insertion point is to judge whether the obtained fault coverage is sufficient or not, and to terminate the processing if it is sufficient, A procedure for extracting test point insertion candidates from a plurality of signal lines based on the failure prevention information, a procedure for determining whether there is a test point insertion candidate, and extracting a test point insertion candidate when there is no candidate Returning to the procedure, if there is a candidate, at least one candidate is selected, and a test point is virtually inserted into the selected candidate. The method according to claim 7, further comprising: a step of inputting a test pattern and performing a second fault simulation to obtain a fault detection rate. A computer-readable recording medium recording a design processing program.