JP4020731B2 - Fault diagnosis method for semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a fault diagnosis method for efficiently specifying a delay fault location of a semiconductor integrated circuit.
[0002]
[Prior art]
As LSI is highly integrated and multi-layered, analysis by a physical analysis device has become difficult. For this reason, there is a demand for a technique for identifying a fault location with high accuracy by software using test results. As a conventional method for diagnosing a delay fault in a semiconductor integrated circuit, for example, there is a method described in Japanese Patent Laid-Open No. 2000-304820. In this method, a logic circuit display of a diagnosis target range including a flip-flop circuit and a combinational circuit is performed, and a path having a relatively high possibility that a delay fault exists is extracted from each path of the combinational circuit on the logic circuit drawing. As pointed out above, the delay fault location is searched from the output side while comparing the expected logic value and the measured signal value.
[0003]
However, in conventional fault diagnosis, a path with a relatively high possibility of the presence of a delay fault is extracted and pointed out on the logic circuit drawing, and the delay fault location is compared from the output side while comparing the expected logic value and the measured signal. If there is a delay fault other than a critical path where there is a high possibility that a delay fault exists, only the path where the delay fault does not exist is measured. It was. In addition, since a delay fault location is searched from the output side of the path, there is a problem that it takes time to specify the delay fault location.
[0004]
[Problems to be solved by the invention]
In order to solve the above problems, the failure diagnosis of the semiconductor integrated circuit of the present invention Method Is efficient and aims to narrow down the delay fault location in a short time.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, failure diagnosis of a semiconductor integrated circuit according to claim 1 Method Is one or more sequential circuits or sets Only Together Wow In a fault diagnosis for specifying a delay fault location of a semiconductor integrated circuit having a delay circuit, a step of specifying a final stage flip-flop connected directly or via a combinational circuit to an output pin in which the delay fault is detected; Identifying an input flip-flop or input pin that inputs a signal directly to the flip-flop or via a combinational circuit; selecting any input flip-flop or input pin of the input flip-flop or input pin; and Of the combinational circuits on the signal propagation path where the selected input flip-flop or input pin inputs the signal The logic expected values of the inputs of the combinational circuit other than the signal propagation path are all values other than values that affect the output value of the combinational circuit. Detecting a combinational circuit; and was detected Specifying a signal propagation path including the combinational circuit as a delay fault location, and automatically specifying a delay fault location candidate.
[0006]
Failure diagnosis of a semiconductor integrated circuit according to claim 2 Method Is one or more sequential circuits or sets Only Together Wow In a fault diagnosis for specifying a delay fault location of a semiconductor integrated circuit having a delay circuit, a step of specifying a final stage flip-flop connected directly or via a combinational circuit to an output pin in which the delay fault is detected; Identifying an input flip-flop or input pin that inputs a signal directly to the flip-flop or via a combinational circuit; sequentially selecting all input flip-flops or input pins of the input flip-flop or input pin; Among the combinational circuits on the signal propagation path through which the selected input flip-flop or input pin inputs a signal The logic expected values of the inputs of the combinational circuit other than the signal propagation path are all values other than values that affect the output value of the combinational circuit. Detecting a combinational circuit; and was detected A signal propagation path including a combinational circuit and a step of registering an expected value of the signal propagation path as a delay fault location, and automatically identifying a signal propagation path that may be a delay fault location To do.
[0007]
Failure diagnosis of a semiconductor integrated circuit according to claim 3 Method Is one or more sequential circuits or sets Only Together Wow In a fault diagnosis for specifying a delay fault location of a semiconductor integrated circuit having a delay circuit, a step of specifying a final stage flip-flop connected directly or via a combinational circuit to the output pin in which the delay fault is detected; Identifying an input flip-flop or input pin that inputs a signal directly to the stage flip-flop or via a combinational circuit; sequentially selecting all input flip-flops or input pins of the input flip-flop or input pin; Among the combinational circuits on the signal propagation path through which the selected input flip-flop or input pin inputs a signal The logic expected values of the inputs of the combinational circuit other than the signal propagation path are all values other than values that affect the output value of the combinational circuit. Detecting a combinational circuit; and was detected A signal propagation path including a combinational circuit, a step of registering an expected value of the signal propagation path and a specific number of times of the signal propagation path as a delay fault location, and a signal propagation that may automatically become a delay fault location A path is specified, and the probability of each delay fault location is verified by the specified number of times.
[0008]
Failure diagnosis of a semiconductor integrated circuit according to claim 4 Method Is one or more sequential circuits or sets Only Together Wow In a fault diagnosis for specifying a delay fault location of a semiconductor integrated circuit having a delay circuit, a step of specifying a final stage flip-flop connected directly or via a combinational circuit to an output pin in which the delay fault is detected; Of all the combinational circuits from the step of selecting an arbitrary final stage flip-flop among the flip-flops to the input pin on the signal propagation path for inputting a signal to the selected final stage flip-flop The logic expected values of the inputs of the combinational circuit other than the signal propagation path are all values other than values that affect the output value of the combinational circuit. Detecting a combinational circuit; and was detected Specifying a signal propagation path including the combinational circuit as a delay fault location, and automatically specifying a delay fault location candidate.
[0009]
As described above, failure diagnosis of the semiconductor integrated circuit of the present invention Method By using, it is efficient and can narrow down a delay fault location in a short time.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Hereinafter, failure diagnosis of the semiconductor integrated circuit according to the first embodiment will be described with reference to the drawings. Method Will be described.
[0011]
FIG. 1 shows a semiconductor integrated circuit according to the first embodiment of the present invention. Road It is a flowchart which shows a failure diagnosis method. FIG. 2 is a circuit diagram of the semiconductor integrated circuit for explaining the failure diagnosis method according to the first embodiment of the present invention, and FIG. It is a figure which shows a trace.
[0012]
In FIG. 1, first, failure diagnosis of a fail location due to a delay failure is started by determining whether the semiconductor integrated circuit is good or bad by a logic tester (S301). Next, from an observation result of the tester, an FF (hereinafter referred to as an output FF) connected to an output pin or an output pin in which a value different from a normal value is observed due to the influence of a delay fault, directly or via a combinational circuit is specified. (S302). Next, an output pin or output on a path (hereinafter referred to as a signal propagation path) for propagating a signal to an output pin or output FF in which a delay fault is detected based on circuit connection information read as design data An input pin or FF (hereinafter referred to as input FF) connected to the FF directly or through a combinational circuit is specified (S303). Next, an arbitrary input pin or input FF is selected from the input FF or input pin specified in S303 (S304). Next, the transition pattern in which the input pin or the input FF selected in S304 detects a delay fault and the signal value of the initialization pattern one time ago are examined (S305). Next, it is determined whether the signal value of the input pin or the input FF examined in S305 has changed (L → H or H → L). If the signal value has not changed, the process returns to S304, and the signal value has changed. If so, the process proceeds to S307 (S306). Next, in each gate of the signal propagation path from the input pin or FF specified in S304 to the output pin or output FF in which the delay fault is detected, all normal values of inputs other than the signal propagation path of each gate are non-existent. A search is made comparing the control value (hereinafter referred to as the activation condition).
[0013]
Next, as a result of the search in S307, it is determined whether the output pin or the output FF where the delay fault is detected has been reached. If not reached, the process returns to S304 to search again, and if reached, the process proceeds to S309 (S308). Finally, the searched signal line is specified as a delay fault location (S309), and the fault diagnosis is terminated (S310).
[0014]
In FIG. 2, a clock signal is input to the clock terminal CLK, and a test mode control signal is input to the test mode control terminal SE. A clock terminal CLK is connected to clock terminals of the scan FF 105, scan FF 106, scan FF 107, scan FF 108, scan FF 109, and scan FF 110, and a test mode control terminal SE is connected to the test mode control terminal. Each scan FF takes in data from the scan input terminal SI when the test mode control signal input from the test mode control terminal SE is “H”, and receives data from the normal signal input terminal D when it is “L”. take in.
[0015]
The circuit as described above forms a scan path from the scan-in terminal SIN to the scan-out terminal SOUT via each scan FF.
The output terminal Q of the scan FF 107 is connected to the input terminal of the AND gate 120 via the net 130. The output terminal Q of the scan FF 108 is connected to the other input terminal of the AND gate 120 via the nets 134 and 135. The output terminal of the AND gate 120 is connected to the input terminal of the OR gate 121 via the net 131, and the net 132 is connected to the other input terminal. The output terminal of the OR gate 121 is connected to the normal input terminal D of the scan FF 110 via the net 133. The output terminal Q of the scan FF 109 is connected to the input terminal of the NAND gate 122 via the nets 137 and 138, and the net 136 is connected to the other input terminal. The output terminal of the NAND gate 122 is connected to the output pin OUT1 through the net 140. The output terminal Q of the scan FF 110 is connected to the scan-out terminal SOUT via the net 139.
[0016]
In FIG. 3, an input pattern 351 represents an input pattern at each time, an output pattern 352 represents an output value at each time, and an internal state 353 represents an output value of a scan FF at each time.
[0017]
As a result of testing the semiconductor integrated circuit of FIG. 2 using the test pattern of FIG. 3, it was determined that a delay fault exists in the semiconductor integrated circuit of FIG. 1 because a failure was observed at the scan-out terminal SOUT at time 9. Therefore, failure diagnosis is started (S301). First, the scan FF 110 in which the delay fault is detected is identified from the result of the scan test (S302). Next, input FFs (scan FF 107, scan FF 108, and scan FF 109 in FIG. 2) existing on the signal propagation path to the scan FF 110 are identified based on the circuit connection information read as design data (S303). Next, the scan FF 109 is selected from the scan FF 107, the scan FF 108, and the scan FF 109 specified in S303 (S304). Next, in the scan FF 109, the signal value in the transition pattern at time 8 for detecting the delay fault is 0, and the signal value in the initialization pattern at time 7 is also 0 (S305). Since the signal value does not change between the pattern and the initialization pattern at time 7, the process proceeds to S304 (S306). Next, the scan FF 107 is selected from the input FFs identified in S303. In the scan FF 107, the signal in the transition pattern at time 8 for detecting the delay fault is 0, the signal in the initialization pattern at time 7 is 1, and the signal value has changed, so the process proceeds to S307. Next, each gate (AND gate 120, OR gate 121) of the signal propagation path (net 130, net 131, net 133) from the scan FF 107 specified in S306 to the scan FF 110 in which the delay fault is detected is detected at time 8. It is checked whether the activation condition is satisfied in the transition pattern (S307). The signal of the net 135 that is an input other than the signal propagation path of the AND gate 120 in the transition pattern at time 8 is the non-control value 1 at the output from the output terminal Q of the scan FF 108. Since the activation condition of the AND gate is satisfied, the next OR gate 121 is examined according to the circuit connection information. In the transition pattern at time 8, the signal of the net 132 that is an input other than the signal propagation path of the OR gate 121 has a non-control value of 0. Since the activation condition of the OR gate is satisfied, the next gate is examined according to the circuit connection information. Since the next gate is the scan FF 110 that has detected the delay fault, the process proceeds to S309 (S308). Finally, the net 130, the net 131, and the net 133 that are connected to the signal propagation path from the scan FF 107 to the scan FF 110 are identified as delay fault locations (S309), and the diagnosis is terminated (S310).
[0018]
By performing the above diagnosis automatically using a program, when a failure is observed at the output pin or output FF, it is possible to efficiently and quickly use the tester's fail information, circuit connection information, and signal line values. The delay fault location can be narrowed down.
(Embodiment 2)
Hereinafter, failure diagnosis of the semiconductor integrated circuit according to the second embodiment will be described with reference to the drawings. Method Will be described.
[0019]
FIG. 4 is a circuit diagram of a semiconductor integrated circuit for explaining the failure diagnosis method according to the second embodiment of the present invention, and FIG. 5 shows the inside of the test pattern and scan FF for explaining the failure diagnosis method according to the second embodiment of the present invention. It is a figure which shows a trace. FIG. 6 shows a semiconductor integrated circuit according to the second embodiment of the present invention. Because of It is a flowchart which shows a failure diagnosis method.
[0020]
In FIG. 4, a clock signal is input to the clock input terminal CLK, and a test mode control signal is input to the test mode control terminal SE. The scan FF 605, scan FF 606, scan FF 607, scan FF 608, scan FF 609, scan FF 610, scan FF 611, scan FF 612, scan FF 613, scan FF 614 are input with the clock terminal CLK, and the test mode control terminal is in the test mode. The control terminal SE is input. Each scan FF takes data from the scan input terminal SI when the test mode control signal is “H”, and takes data from the normal signal input terminal D when the test mode control signal is “L”.
[0021]
The circuit as described above forms a scan path from the scan-in terminal SIN to the scan-out terminal SOUT via each scan FF.
The output terminal Q of the scan FF 607 is connected to the input terminal of the AND gate 620 via the net 630. The output terminal Q of the scan FF 608 is connected to the other input terminal of the AND gate 620 via the nets 636 and 637. The output terminal of the AND gate 620 is connected to the input terminal of the OR gate 621 via the net 631, and the net 632 is connected to the other input terminal. The output terminal of the OR gate 621 is connected to the normal input terminal D of the scan FF 614 via the net 633. The output terminal Q of the scan FF 609 is connected to the input terminal of the AND gate 622 via the nets 634 and 655, and the net 638 is connected to the other input. The output terminal of the AND gate 622 is connected to the net 635. The net 635 is connected to the net 632 and the net 648, and the net 648 is connected to the output pin OUT1. The output terminal Q of the scan FF 610 is connected to the input terminal of the NOR gate 623 via the nets 640 and 641, and the net 639 is connected to the other input terminal. The output terminal Q of the scan FF 611 is connected to the input terminal of the OR gate 624 via the nets 643 and 644. The output terminal Q of the scan FF 612 is connected to the other input terminal of the OR gate 624 via the nets 646 and 647. The output terminal of the NOR gate 623 is connected to the input terminal of the AND gate 625 via the net 642. The output terminal of the OR gate 624 is connected to the other input terminal of the AND gate 625 via the net 645. The output terminal of the AND gate 625 is connected to the normal input terminal D of the scan FF 613 via the net 649. The output terminal Q of the scan FF 614 is connected to the scan-out terminal SOUT via the nets 650 and 651. The output terminal Q of the scan FF 613 is connected to the input terminal of the AND gate 626 via the net 653, and the net 652 is connected to the other input terminal. The output terminal of the AND 626 gate is connected to the output pin OUT 2 via the net 654.
[0022]
In FIG. 5, an input pattern 701 represents an input pattern at each time, an output pattern 702 represents an output value at each time, and an internal state 703 represents an output value of a scan FF at each time.
[0023]
In FIG. 6, S301, S302, S303, S304, S305, S306, S307, and S310 perform the same processing as the flowchart of FIG.
[0024]
In the process of S801, it is investigated whether all the input pins or input FFs specified in S303 have been selected. If all are selected, the process proceeds to S803, and if not selected, the process proceeds to S304. In S308, as a result of the search in S307, it is determined whether the output pin or the output FF where the delay fault is detected has been reached. If not reached, the process returns to S801, and if reached, the process proceeds to S802. In S802, the searched signal line and signal line pair on the signal propagation path are registered as delay fault path information of the output pin or output FF selected in S302, and the process returns to S801 again. In S803, signal line pairs included in the delay fault path information of all the output pins or output FFs specified in S302 are specified as delay fault diagnosis locations, and the fault diagnosis is terminated (S310).
[0025]
As a result of testing the semiconductor integrated circuit of FIG. 4 using the test pattern of FIG. 5, a failure is observed at the output pin OUT1 at time 12 and the scan-out terminal SOUT at time 13, thereby delaying the semiconductor integrated circuit of FIG. Since it is determined that a failure exists, failure diagnosis is started (S301). First, OUT1 and scan FF 614 in which a delay fault is detected are identified from the result of the scan test (S302). Next, on the signal propagation path to the input FF (scan FF 608, scan FF 609 in FIG. 4) and the scan FF 614 existing on the signal propagation path to OUT1 based on the circuit connection information read as design data The input FFs (scan FF 607, scan FF 608, and scan FF 609 in FIG. 4) are identified (S303). Next, since all the input FFs identified in S303 have not yet been selected (S801), the scan FF 607 is selected from the scan FF 607, scan FF 608, and scan FF 609 identified in S303 (S304). Next, in the scan FF 607, the signal value of the transition pattern at time 12 for detecting the delay fault is 0, and the signal value of the initialization pattern at time 11 is also 0 (S305). Since the signal value does not change between the pattern and the initialization pattern at time 11, the process returns to S801 (S306). Since all the input FFs specified in S303 are not selected (S801), the scan FF 609 is selected from the scan FF 607, scan FF 608, and scan FF 609 specified in S303 (S304). Next, in the scan FF 609, the signal value of the transition pattern at time 12 for detecting a delay fault is 0, and the signal value of the initialization pattern at time 11 is 1 (S305). Since the signal value changes between the pattern and the initialization pattern at time 11, the process proceeds to S307 (S306). Each gate (AND gate 622) of the signal propagation path (net 634, net 635, net 648) from the scan FF 609 identified in S306 to OUT1 where the delay fault is detected and the signal propagation path (net 632, net) to the scan FF 614 633 and nets 634 and 635), it is checked whether the activation condition is satisfied in the transition pattern at time 12 (S307). The signal of the net 638 that is an input other than the signal propagation path of the AND gate 622 in the transition pattern at time 12 of the signal propagation path to OUT1 has a non-control value 1. Since the activation condition of the AND gate is satisfied, the next gate is checked according to the circuit connection information. Since the next gate is OUT1 where a delay fault is detected, a signal propagation path to the scan FF 614 is searched. The signal of the net 638 that is an input other than the signal propagation path of the AND gate 622 in the transition pattern at the time 12 of the signal propagation path to the scan FF 614 has a non-control value 1. Since the activation condition of the AND gate is satisfied, the next OR gate 621 is checked according to the circuit connection information. In the transition pattern, the signal of the net 631 that is an input other than the signal propagation path of the OR gate 621 has a non-control value 0. Since the activation condition of the OR gate is satisfied, the next gate is examined according to the circuit connection information. Since the next gate is the scan FF 114 that has detected the delay fault, it is determined that the output FF has been reached, and the process proceeds to S802 (S308). Next, the net obtained as a result of searching for the signal propagation path propagating to OUT1 and the value (net 634,1), (net 635,1), and (net 648,1) of the net in the normal operation are set to Registration as delay fault path information (S802). Similarly, a net obtained as a result of searching for a signal propagation path propagating to the scan FF 614 and values at the time of normal operation of the net (nets 634, 1), (nets 635, 1), (nets 632, 1), ( Net 633,1) is registered as delay fault path information of the scan FF 614 (S802). Since all the input FFs specified in S303 are not yet selected, the scan FF 608 is selected, and the process proceeds to S304 (S304). Next, in the scan FF 608, the signal value of the transition pattern at time 12 for detecting a delay fault is 1, the signal value of the initialization pattern at time 11 is also 1 (S305), and the input pin or input specified in S303 is used. Since all the FFs have been selected, the process proceeds to S803 (S801). Next, the signal line pair (net 634, 1) and (net 635, 1) included in common in the delay fault information of OUT1 and scan FF 614 in which the delay fault is detected are specified as the delay fault location (S803), The diagnosis is terminated (S310).
[0026]
By performing the above diagnosis automatically using a program, when a failure is observed at a plurality of output pins or output FFs, not all signal lines in the signal propagation path as delay faults, but more detailed Even signal lines can be specified, and delay fault locations can be narrowed down efficiently.
[0027]
In S803, the signal line that is most frequently included in the delay fault path information of the output pin or the output FF specified in S302 can be specified as a delay fault location.
(Embodiment 3)
Hereinafter, failure diagnosis of the semiconductor integrated circuit according to the third embodiment will be described with reference to the drawings. Method Will be described.
[0028]
FIG. 7 is a circuit diagram of a semiconductor integrated circuit for explaining the failure diagnosis method according to the third embodiment of the present invention. The difference from FIG. 4 is that the output terminal of the NOR gate 623 is connected to the net 656, and the net 656 is 657 is connected to the net 642, and the net 657 is connected to the input terminal of the OR gate 621. FIG. 8 is a diagram showing a test pattern and a scan FF internal trace for explaining the failure diagnosis method according to the third embodiment of the present invention, and FIG. 9 is a semiconductor integrated circuit according to the third embodiment of the present invention. Because of It is a flowchart which shows a failure diagnosis method.
[0029]
In FIG. 9, S301, S302, S303, S304, S305, S306, S307, and S310 perform the same processing as the flowchart of FIG.
[0030]
In S308, as a result of the search in S307, it is determined whether the output pin or the output FF where the delay fault is detected has been reached. If not reached, the process returns to S304, and if reached, the process proceeds to S1101. In step S1101, a net obtained as a result of searching for a signal propagation path to propagate and a value during normal operation of the net are registered as delay fault path information. In S1102, the appearance frequency of the delay fault path information registered in S1101 is updated. In S801, it is checked whether or not all the input pins or input FFs specified in S303 are selected. If not all are selected, the process proceeds to S304, and if all are selected, the process proceeds to S1103. In S1103, in the delay fault path information, the signal line having the highest appearance frequency is registered as a delay fault location, and the fault diagnosis is terminated (S310).
[0031]
As a result of testing the semiconductor integrated circuit of FIG. 7 using the test pattern of FIG. 8, a delay failure exists in the semiconductor integrated circuit of FIG. 7 because a failure was observed at the scan-out terminal SOUT at times 13, 26, and 38. Then, since it is determined, failure diagnosis is started (S301). First, the scan FF 613 and the scan FF 614 in which the delay fault is detected are specified (S302). Next, based on the circuit connection information read as design data, the input FFs (scan FF 608, scan FF 610, scan FF 611, scan FF 612 in FIG. 7) and the scan FF 614 that have signal propagation paths to the scan FF 613 exist. Input FFs (scan FF 607, scan FF 608, scan FF 609, scan FF 610 in FIG. 7) in which the signal propagation path exists are identified (S303). Next, it is determined that all the input FFs specified in S303 are not selected (S801), and the scan FF 607 is selected from the scan FF 607, scan FF 608, scan FF 609, scan FF 610, scan FF 611, and scan FF 612 specified in S 303. (S304). Next, the signal value of the transition pattern is compared with the signal value of the initialization pattern (S305). Since the signal value has not changed, the process proceeds to S801 (S306). Subsequently, since all the input FFs identified in S303 are not selected (S801), the scan FF 608 is selected from the scan FF 607, scan FF 608, scan FF 609, scan FF 610, scan FF 611, and scan FF 612 identified in S 303 ( S304). Next, when the signal value of the transition pattern is compared with the signal value of the initialization pattern (S305), the scan FF 608 has the signal value of the transition pattern at time 12 when the delay fault is detected as 0, and the initialization pattern at time 11 is detected. Since the signal value is 1, and the scan FF 608 changes the signal value between the transition pattern at time 12 and the initialization pattern at time 11, the process proceeds to S307 (S306). Next, a signal propagation path (net 636, net 637, net 631, net 635, net 632, net 633, net 639, net 638, net 656 from the scan FF 608 identified in S306 to the scan FF 614 in which the delay fault is detected. , Net 657), whether each gate (AND gate 620, OR gate 621, AND gate 622, NOR gate 623) satisfies the activation condition in the transition pattern at time 12 is examined. The signal of the net 630 that is an input other than the signal propagation path of the AND gate 620 connected to the net 637 that is the signal propagation path to the scan FF 614 in the transition pattern at time 12 is the control value 1, and the activation of the AND gate Since the condition is not satisfied, the route search is stopped, and then the net 638 is searched. The signal of the net 655 that is an input other than the signal propagation path of the AND gate 622 to which the net 638 is connected has a control value of 0, and does not satisfy the activation condition of the AND gate. Explore. Since the signal of the net 641 that is an input other than the signal propagation path of the NOR gate 623 to which the net 639 is connected is the non-control value 0, the NOR gate activation condition is satisfied. Check out. The above processing is repeated until the scan FF 614 as the output FF is reached (S307), the net obtained as a result of searching for the signal propagation path propagating to the scan FF 614 and the value at the time of normal operation of the net (net 636, 0) (Net 639,0) (Net 656,1) (Net 657,1) (Net 633, 1) are registered as delay fault path information (S1101). Here, since the appearance frequency of the registered signal line is 1, if the information on the appearance frequency is added to the delay fault path information, (net 636, 0, 1), (net 639, 0, 1) (net 655) , 1, 1) (net 656, 1, 1) (net 633, 1, 1) (S1102). Subsequently, since all the input FFs specified in S303 are not selected (S801), the same processing is performed for all the input FFs of the scan FF 609, the scan FF 610, the scan FF 611, and the scan FF 612. After processing for all the input FFs, the delay fault path information is (net 636, 0, 1) (net 639, 0, 1) (net 656, 1, 2) (net 657, 1, 1) ( Net 633,1,1) (net 640,0,1) (net 641,0,1), (net 642,1,1) (net 649,1,2) (net 643,1,1) (net 644, 1, 1) (nets 645, 1, 1). Finally, in the delay fault path information, the signal line (net 655, 1, 2) (net 649, 1, 2) having the highest appearance frequency is specified as the delay fault location (S1103), and the diagnosis is terminated ( S310).
[0032]
By performing the above diagnosis automatically using a program, if a delay fault occurs due to the sum of the delay values of multiple wirings and gates, the delay fault may occur even if the route does not pass through all the wirings and gates that cause the delay fault. It may become. For this reason, there may be no signal line that includes the delay fault path information of all the output pins or output FFs identified in S302. Even in such a case, by selecting a signal line according to the appearance frequency of the delay fault path information, the delay fault location can be specified, and the delay fault locations can be efficiently narrowed down.
(Embodiment 4)
Hereinafter, failure diagnosis of the semiconductor integrated circuit according to the fourth embodiment will be described with reference to the drawings. Method Will be described.
[0033]
FIG. 10 is a flowchart showing a fault diagnosis method for a semiconductor integrated circuit according to the fourth embodiment of the present invention.
10, S301, 302, and 310 perform the same processing as the flowchart of FIG. 1, and a description thereof is omitted.
[0034]
In S1201, the combinational circuit connected to the output pin or output FF in which the delay fault is detected is selected. In S1202, it is checked whether the input of the combinational circuit selected in S1201 is an input pin or an input FF. If it is an input pin or an input FF, the process proceeds to S309. Otherwise, the process proceeds to S1203. In S1203, the input terminal of the combinational circuit is selected. In S1204, the transition pattern of the input terminal selected in S1203 and the value of the initialization pattern one time before are checked. In S1205, it is determined whether the signal value of the input terminal selected in S1203 has changed. If the signal value has not changed, the process returns to S1203. If the signal value has changed, the process returns to S1201, and the input terminal selected in S1202 is selected. Select the combinational circuit to be the output terminal. The processes from S1201 to S1205 are repeated until the input pin or the input FF is reached. In S309, the path from the output pin or output FF selected in S302 to the input pin or input FF reached in S1202 is specified as a delay fault location, and the fault diagnosis is terminated (S310).
[0035]
As a result of testing the semiconductor integrated circuit of FIG. 2 using the test pattern of FIG. 3, it was determined that there was a delay fault in the semiconductor integrated circuit of FIG. 2 because a failure was observed at the scan-out terminal SOUT at time 9. Therefore, failure diagnosis is started (S301). First, the scan FF 110 in which the delay fault is detected is specified (S302). Next, the OR gate 121 connected to the scan FF 110 is selected based on the circuit connection information read as design data (S1201). Next, since the input FF or the input pin has not been reached, the process proceeds to S1203 (S1202), the net 132 of the OR gate 121 is selected (S1203), the signal value of the transition pattern of the net 132 and the initialization one time before The signal value of the pattern is checked (S1204). Since the transition pattern value of the net 132 is 0 and the value of the initialization pattern one time before is 0 and there is no signal change, the process proceeds to S1203 (S1205). Subsequently, the other net 131 of the OR gate 121 is selected (S1203), and the signal value of the transition pattern of the net 131 and the signal value of the initialization pattern one time before are investigated (S1204). Since the signal value of the transition pattern of the net 131 is 0 and the signal value of the initialization pattern one time before is 1, and there is a signal change, the process returns to S1201 (S1205). Next, the AND 120 that outputs the net 131 is selected (S1201). Since the input FF or the input pin is not reached, the process proceeds to S1203 (S1202), and the net 130 of the AND gate 120 is selected (S1203). Next, the signal value of the transition pattern of the net 130 and the signal value of the initialization pattern one time before are investigated (S1204), and the signal value of the initialization pattern one time before when the signal value of the transition pattern of the net 130 is 0. Is 1, and there is a signal change, the process returns to S1201 (S1205). Next, the scan FF 107 that outputs the net 130 is selected (S1201). Since the input FF is reached, the process proceeds to S309. Finally, the nets 130, 131, and 133 on the path where the signal has changed are specified as a delay fault location (S309), and the diagnosis is terminated (S310).
[0036]
By automatically performing the above diagnosis using a program, searching for a signal change of the net from the output pin or the output FF toward the input pin or the input FF makes it possible to narrow down the location of the delay fault efficiently.
[0037]
Further, S1201 to S1205 of FIG. 12 may be implemented instead of S303 to S308 of FIG. 8 which is the failure diagnosis method in the second embodiment of the present invention.
Further, S1201 to S1205 of FIG. 12 may be implemented instead of S303 to S308 of FIG. 11 which is the failure diagnosis method in the third embodiment of the present invention.
[0038]
【The invention's effect】
As described above, failure diagnosis of the semiconductor integrated circuit of the present invention Method If a failure is observed at the output pin or output FF, the tester's fail information, circuit connection information, and normal value of the signal line ,late Since any signal propagation path that may cause a failure can be diagnosed using the activation condition, the location of the delayed failure can be narrowed down efficiently in a short time.
[0039]
Also, when a failure is observed at multiple output pins or output FFs ,late Since all signal propagation paths that may cause a failure can be narrowed down using the activation conditions, it is possible to narrow down to a detailed partial path efficiently in a short time.
[0040]
Further, when a delay fault occurs due to the sum of delay values of a plurality of wirings and combinational circuits, the delay fault may be detected even if the route does not pass through all wirings and combinational circuits having a large delay value. Even in such a case, by obtaining the signal lines that are registered as delay fault path information most frequently, the delay fault location can be specified and the detailed partial path can be narrowed down efficiently.
[0041]
Further, by searching for a signal change of the net from the output pin or the output FF toward the input pin or the input FF, it is possible to efficiently narrow down the delay fault locations.
[Brief description of the drawings]
1 is a semiconductor integrated circuit according to a first embodiment of the present invention; Because of Flowchart showing failure diagnosis method
FIG. 2 is a circuit diagram of a semiconductor integrated circuit for explaining a failure diagnosis method according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a test pattern and an internal trace of a scan FF for explaining a failure diagnosis method according to the first embodiment of the present invention.
FIG. 4 is a circuit diagram of a semiconductor integrated circuit for explaining a failure diagnosis method according to a second embodiment of the present invention.
FIG. 5 is a diagram showing a test pattern and an internal trace of a scan FF for explaining a failure diagnosis method according to a second embodiment of the present invention.
FIG. 6 is a semiconductor integrated circuit according to a second embodiment of the present invention. Because of Flowchart showing failure diagnosis method
FIG. 7 is a circuit diagram of a semiconductor integrated circuit for explaining a failure diagnosis method according to a third embodiment of the present invention.
FIG. 8 is a diagram showing a test pattern and an internal trace of a scan FF for explaining a failure diagnosis method according to a third embodiment of the present invention.
FIG. 9 shows a semiconductor integrated circuit according to the third embodiment of the present invention. Road Flow chart showing failure diagnosis method
FIG. 10 is a semiconductor integrated circuit according to a fourth embodiment of the present invention. Because of Flowchart showing failure diagnosis method
[Explanation of symbols]
105 scan FF
106 Scan FF
107 scan FF
108 scan FF
109 scan FF
110 scan FF
111 scan FF
112 scan FF
113 scan FF
114 scan FF
120 AND gate
121 OR gate
122 NAND gate
130 net
131 Net
132 Net
133 net
134 Net
135 Net
136 net
137 net
138 Net
139 Net
140 net
351 input pattern
352 output pattern
353 Internal state
605 Scan FF
606 Scan FF
607 Scan FF
608 Scan FF
609 Scan FF
610 Scan FF
611 Scan FF
612 Scan FF
613 Scan FF
614 Scan FF
620 AND gate
621 OR gate
622 AND gate
623 NOR gate
624 OR gate
625 AND gate
626 AND gate
630 net
631 Net
632 Net
633 Net
634 Net
635 net
636 Net
637 Net
638 net
639 Net
640 net
641 net
642 Net
643 Net
644 Net
645 net
646 Net
647 net
648 net
649 Net
650 net
651 net
652 Net
653 net
654 net
655 net
656 net
657 net
701 Input pattern
702 Output pattern
703 Internal state

Claims (4)

In fault diagnosis for specifying a delay fault location of a semiconductor integrated circuit having one or more sequential circuit and set viewing if I were circuit,
Identifying a final stage flip-flop connected directly or via a combinational circuit to an output pin in which a delay fault is detected;
Identifying an input flip-flop or input pin that inputs a signal directly or through a combinational circuit to the final stage flip-flop;
Selecting any input flip-flop or input pin of the input flip-flops or input pins;
Of the combinational circuits on the signal propagation path through which the selected input flip-flop or input pin inputs a signal, all logical expected values of inputs of the combinational circuit other than the signal propagation path affect the output value of the combinational circuit. Detecting a combinational circuit having a value other than a given value ;
The detected and a step of specifying a signal propagation path as a delay fault site comprising a combination circuit, automatically fault diagnosis method for a semiconductor integrated circuit and identifies the candidate delay fault location. In fault diagnosis for specifying a delay fault location of a semiconductor integrated circuit having one or more sequential circuit and set viewing if I were circuit,
Identifying a final stage flip-flop connected directly or via a combinational circuit to an output pin in which a delay fault is detected;
Identifying an input flip-flop or input pin that inputs a signal directly or through a combinational circuit to the final stage flip-flop;
Sequentially selecting all input flip-flops or input pins of the input flip-flops or input pins;
Of the combinational circuits on the signal propagation path through which the selected input flip-flop or input pin inputs a signal, all logical expected values of inputs of the combinational circuit other than the signal propagation path affect the output value of the combinational circuit. Detecting a combinational circuit having a value other than a given value ;
A signal propagation path including the detected combinational circuit and a step of registering an expected value of the signal propagation path as a delay fault location, and automatically identifying a signal propagation path that may be a delay fault location A fault diagnosis method for a semiconductor integrated circuit. In fault diagnosis for specifying a delay fault location of a semiconductor integrated circuit having one or more sequential circuit and set viewing if I were circuit,
Identifying a final stage flip-flop connected directly or via a combinational circuit to the output pin where a delay fault is detected;
Identifying an input flip-flop or input pin that inputs a signal directly or through a combinational circuit to the final stage flip-flop;
Sequentially selecting all input flip-flops or input pins of the input flip-flops or input pins;
Of the combinational circuits on the signal propagation path through which the selected input flip-flop or input pin inputs a signal, all logical expected values of inputs of the combinational circuit other than the signal propagation path affect the output value of the combinational circuit. Detecting a combinational circuit having a value other than a given value ;
A signal propagation path including the detected combination circuit, an expected value of the signal propagation path, and a step of registering a specific number of times of the signal propagation path as a delay fault location, and the possibility of automatically becoming a delay fault location A fault diagnosis method for a semiconductor integrated circuit, wherein a certain signal propagation path is specified and the probability of each delay fault location is verified by the specified number of times. In fault diagnosis for specifying a delay fault location of a semiconductor integrated circuit having one or more sequential circuit and set viewing if I were circuit,
Identifying a final stage flip-flop connected directly or via a combinational circuit to an output pin in which a delay fault is detected;
Selecting any final stage flip-flop among the final stage flip-flops;
Of all the combination circuits up to the input pin on the signal propagation path for inputting a signal to the selected final stage flip-flop, all the logic expected values of the inputs of the combination circuits other than the signal propagation path are all the combination circuits. Detecting a combinational circuit that is a value other than a value that affects the output value of
The detected and a step of specifying a signal propagation path as a delay fault site comprising a combination circuit, automatically fault diagnosis method for a semiconductor integrated circuit and identifies the candidate delay fault location.

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