JPH09153297A - Test method of semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a test efficiency by changing a storing method of faulty data into a fail memory according to an improvement in yield of memory IC and an actual performance of the product when a redundancy judgment test is performed. SOLUTION: When a redundancy judgment is performed after a completion of a test 1, faulty data 8a are read in a redundancy computing unit 5 from an arbitrary block among plural fail memory blocks storing the faulty data 8a, to perform a redundancy judgment. If the test result is judged as a replacement is possible, a test 2 is performed. When the faulty data 8b in the test 2 are stored in a fail memory 6, faulty data 8b are individually and simultaneously stored in a first to a third stages of blocks of fail memories as many as the number of hold test items just as in the test 1. The redundancy judgment of the test 2 is performed as that of the test 1. Subsequently, in a similar way, it is rendered that a storing test to stored a faulty data position in a fail memory is rendered decreases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a semiconductor memory device, and more particularly to a test method for determining redundancy of a semiconductor memory device.

[0002]

2. Description of the Related Art Generally, a semiconductor memory device (hereinafter referred to as a memory I
The preliminary test (hereinafter referred to as the redundancy judgment test) in the wafer inspection process of C) detects the internal disconnection defect (open defect) and the internal short circuit defect (leak defect) of the memory IC, and also configures the memory IC. It is possible to detect a defective memory cell for each memory cell unit, replace the defective memory cell with a redundant memory cell prepared separately inside the memory IC, and replace with a limited number of redundant memory cells. Whether or not the memory IC is a good product /
This is a test for determining defective products.

An example of the test flow of this redundancy judgment test is shown in FIG. As shown in this figure, in this redundancy judgment test, after performing an open defect detection test in step S1 and a leak defect detection test in step S2, different functions are performed a plurality of times in steps S3, S5, S7, 49, and S11. Perform a test (test 1 to test 5) and perform step S
In S4, S6, S8, S10, and S12, redundancy judgment is performed for each of these functional tests or for each of a plurality of functional tests.
The category data was allocated in step S13.

The items of the function test performed at this time differ depending on the type of the memory under test IC1, but generally, the test (test 1) for confirming the basic operation of the memory under test IC1 in step S3 and the test memory in step S5. Test for detecting failure mode peculiar to IC (Test 2), Steps S7, 9,
11 tests (test 3 to test 5, hereinafter referred to as hold test) for detecting the memory retention capacity of the memory IC under test. Further, this hold test is made up of a plurality of tests having different hold times in order to select the grade of the memory IC standard, and the test flow includes a test with a low standard of step S7 and a short hold time (test 3). The test (test 4 test 5) having a high standard and a long hold time was carried out sequentially from step S9 to step S11.

Next, a redundancy judgment operation will be described. A block diagram for carrying out this test is shown in FIG. As shown in the figure, in the redundancy judgment test, first, a test pattern composed of an address signal 9, a control signal 10 and an input data signal 11 generated from the pattern generator 13 is supplied to the memory under test IC1 and the test pattern is supplied to the memory under test IC1. To memorize. Next, the pattern generator 1
3 is a test pattern composed of an address signal 9, a control signal 10 and an expected value data signal 12 generated from No. 3 while reading the above-mentioned stored contents from the memory under test IC1 and expecting the read stored contents (output data signal 2). The value data signal 12 and the value data signal 12 are compared and judged by the comparator 3, and if they do not match, the defective signal cell position storage device 6 (hereinafter, fail memory) is sequentially displayed as defective data 4 by the address signal 9 in synchronization with the test pattern. I said).

Next, when all the test patterns are completed, the defective data 4 stored in the fail memory 6 is read out to the redundancy computing unit 5, and whether or not the redundancy computing unit 5 can replace the redundant memory cell. Judge,
The defective / defective product of the memory under test IC1 is determined.

FIG. 6 is an explanatory diagram showing the configuration of the fail memory 6 of FIG. 5 and the method of storing the defective data 4. The fail memory having the total capacity bit n and the total number of data input bits m is divided into the capacity bit n / p and the number of data input bits m / p according to the number p of simultaneous measurements of the memory under test IC1, and is allocated to each memory IC1. . Since each of the divided fail memories 6 performs the same operation in parallel, only one divided memory will be described below.

In order to simplify the explanation, the memory under test I
The data output bit number of C1 is 1 bit. In this case, the defective data 4 is stored using any one of the data input bits 7 of the fail memory. When the number of data output bits of the memory under test IC1 is 4, the defective data is stored by using any 4 bits of the data input bits of the fail memory.

The method of storing the defective data 4 is first described in the test 1 in the test flow of the redundancy judgment test described above.
Then, the defective data 8a of the test 1 is stored in an arbitrary single fail memory block of the fail memory 6 based on the above-described operation of the redundancy judgment, and the redundancy judgment is performed. Here, the fail memory block means that the fail memory 6 is the number p of simultaneous measurements of the memory under test IC1.
And a memory block systematically divided according to measurement conditions such as the number of input / output data bits q of the memory under test IC1, and capacity bits {(n / p) / (m / p)} or {(n / p) / Q}. Here, n is the total capacity bit of the fail memory 6, and m is the total number of data input bits of the fail memory 6.

As a result of this redundancy judgment, if replacement with a redundant memory cell is possible, then test 2 is carried out.
At this time, the defective data 8b of the test 2 is the defective data 8 of the test 1.
It is overwritten on a and stored in the fail memory 6. After storing the defective data 8b of the test 2, the redundancy determination is further performed, and if the replacement with the redundant memory cell is further possible, then the test 3 is performed similarly to the test 2. Hereinafter, test 4,
Test 5 is also repeated in sequence. Here, in the test flow of the hold test (test 3 to test 5), since the defective data 4 is overwritten for each functional test and stored in the fail memory 6 as described above, a test with a low standard and a short hold time ( The tests were performed from the test 3), and the tests (test 4, test 5) having a higher standard and a long hold time were sequentially performed. However, as a result of the redundancy judgment, when the replacement with the redundant memory cell becomes impossible, the category data as the test result is allocated and the test ends.

[0011]

As described above, in the test flow of the redundancy judgment test of the memory IC 1, a plurality of different functional tests (test 1 to test 5) are performed, and each of these functional tests or a plurality of functional tests is performed. Redundancy judgment was performed for each functional test. The number of times that the function test and the redundancy judgment are performed in one test flow is the function test until the replacement with the redundant memory cell becomes impossible as a result of the redundancy judgment. And memory I for determining product grade of memory IC
The number of times increases as the product performance value (derived from hold) of C improves. As a result, the test time as a whole increases and the test cost increases.

Generally, the yield of the memory IC and the memory I
The product performance value (derived from hold) of C improves and stabilizes in about one year from the start of production due to the accumulation of failure mode data.

An object of the present invention is to change the method of storing defective data in the fail memory according to the yield of the memory IC and the improvement of the product ability value (deriving hold) of the memory IC when conducting the redundancy judgment test. Accordingly, it is an object of the present invention to provide a semiconductor memory test method in which a redundancy judgment test is efficiently performed and an increase in test time is reduced.

[0014]

According to the present invention, there is provided a semiconductor memory device testing method using a test device having a fail memory for storing defective cell position data of a semiconductor memory device, wherein the defective cell position data of the semiconductor memory device is included. In the fail memory, by storing the defective cell position data in any one of a plurality of different memory blocks for each functional test of the semiconductor memory device, in order of the functional test items. A test is conducted to reduce the number of storage tests of the defective cell position data in the fail memory.

In the present invention, it is also possible that the functional tests of the semiconductor memory device are carried out from the functional test having the higher standard grade, and the functional tests having the lower standard grade are successively carried out.

The fail memory block is a capacity bit {(n / p) / (m / p)} or {(n / p) /.
, m is the total number of data input bits of the fail memory, n is the total capacity bit of the fail memory, p is the total number of data input bits of the fail memory, and q is the memory under test I.
It is the number of input / output data bits of C.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a test flow chart of a redundancy judgment test for explaining an embodiment of the present invention. In the conventional configuration, the test flow of the hold test (test 3 to test 5) is performed from the test with the low standard grade and the short hold time (test 3), and sequentially when the redundancy function is determined by the redundancy determination after the test. Although a test with a high standard grade and a long hold time (test 4, test 5) was carried out, in the present embodiment, the test flow of the hold test (test 3 to test 5) is step 7A as shown in the figure. If the replacement is not possible by the redundancy judgment after the test, the test with the higher standard grade and longer hold time (test 5) is performed in steps 9 and 11A in order with the lower standard grade and the shorter hold time. (Test 4,
Test 3) is being conducted. In addition, in the hold test, a test with a high standard grade and a long hold time includes a test with a low standard grade and a short hold time. If the test is passed, it is not necessary to perform a hold test at a low level of standard grade.

A block diagram of FIG. 2 shows a method of storing the defective data 4 of the memory under test IC1 in the fail memory 6 for realizing the test flow of the redundancy judgment test of FIG. In this figure, first, the test 1 is performed in step S3, and the defective data 8a of the test 1 is stored in the same number of capacity bits as the number of hold test items (here, test 3, test 4, and test 5). 1 to 1 of the fail memory 6 represented by (n / p) / (m / p)} or {(n / p) / q}
The same defective data 8a is simultaneously and individually provided in the third stage block.
Is stored. Here, a method of simultaneously storing the same defective data in a plurality of fail memory blocks is disclosed in JP-A-3-15.
6799 publication.

In addition, after the completion of the test 1, when performing the redundancy judgment, the redundancy operation unit for the failure data 8a from any one of the plurality of fail memory blocks (three in this description) storing the failure data 8a. Read in 5 and judge redundancy. As a result of this redundancy determination, if it is determined that the replacement is possible, the following test 2 is performed. When the defective data 8b of the test 2 is stored in the fail memory 6, the defective data 8a of the test 1 is overwritten and the first to third blocks of the fail memory corresponding to the number of the hold test items are overwritten as in the test 1. In addition, the same defective data 8b is individually and simultaneously stored. The redundancy judgment of the test 2 is performed in the same manner as the redundancy judgment of the test 1.

When it is judged by this redundancy judgment that replacement is possible, when the test 5 is carried out next in step S7A, the defective data 8e of the test 5 is overwritten on the block of the third stage of any one fail memory. And remember. This test 5
The redundancy judgment is performed by reading the defective data 8a, 8b, 8e from the third block of the fail memory in which the defective data 8e was written in step 8 to the redundancy calculator 5 and making the redundancy judgment. If the result of the redundancy judgment is judged to be replaceable, the category data is allocated and the test ends. If it is determined that the replacement is impossible, the test 4 is performed in step 9. The defective data 8d of the test 4 is the defective data 8e of the test 5.
Other than the fail memory block in which is stored, it is overwritten and stored in the block of the second stage of any one fail memory. The redundancy determination of this test 4 is performed in step 10 in the same manner as the test 5. Next, when the test 3 is performed in step 11A, the same test is performed using the remaining fail memory blocks. In this way, the test flow of the redundancy judgment test shown in FIG. 1 can be realized.

FIG. 3 is a block diagram for explaining the second embodiment of the present invention. This embodiment also shows a method of storing the defective data 4 of the memory under test IC1 in the fail memory 6 and a method of redundancy determination for realizing the test flow of the redundancy determination test similar to the case of FIG. In the figure, first, the test 1 is performed in step S3,
The defective data 8a of the test 1 is set to the capacity bit {(n / p) /
The data is stored in the first block of the fail memory 6 represented by (m / p)} or {(n / p) / q}.

After the end of this test 1, in step S4, the redundancy judgment is performed by reading from the fail memory block storing the defective data 8a into the redundancy calculator 5. If it is determined that the replacement is possible as a result of the redundancy determination, the test 2 is performed in step S5. The defective data 8b of the test 2 is overwritten and stored in the first block of the fail memory 6 storing the defective data 8a of the test 1,
The redundancy determination in step S6 after the test 2 is performed is the same as the redundancy determination in the test 1.

In this redundancy judgment, it is judged that replacement is possible, and when the test 5 is carried out next in step 7A, the defective data 8e of the test 5 is the defective data 8 of the test 1 and the test 2.
The memory blocks a and 8b are stored in the fourth block of the fail memory 6 different from the first memory block of the fail memory 6.

The redundancy judgment in step 8 after the completion of this test 5 is performed by the first stage block of the fail memory storing the defective data 8e of the test 5 and the fail memory storing the defective data 8a, 8b of the test 1 and the test 2. Defective data 8a, 8b, 8 in parallel from the fourth block of
e is output to the redundancy computing unit 5 and read in to perform redundancy judgment. Here, the function of outputting the defective data from the plurality of fail memory blocks in parallel at the same time to the redundancy operation unit 5 and reading the defective data is a function already realized by the test apparatus (memory tester).

If the result of the redundancy determination is determined to be replaceable, the category data is assigned in step S13 to end the test. If it is determined that the replacement is not possible, the test 4 is performed next. .

The defective data 8d of the test 4 in the next step S9 is the defective data 8e of the test 5 and the test 1 and the test 2.
Other than the fail memory block storing the defective data 8a and 8b, the data is stored in the block of the third stage of any single fail memory. Step S10 after completion of this test 4
The redundancy judgment is performed in the same manner as in the test 5 from the fail memory block storing the bad data 8d of the test 4 and the fail memory block storing the bad data 8a, 8b of the test 1 and the test 2 in parallel at the same time.
b and 8d are output to the redundancy calculator 5 and read,
Redundancy makes a decision. If the result of the redundancy judgment (S10) after the completion of this test 4 is judged to be replaceable, the category data is assigned in step S13 and the test is ended. Do 3.

The defective data 8c of the test 3 in the next step S11A is the defective data 8e of the test 5, the defective data 8d of the test 4, and the defective data 8a of the test 1 and the test 2.
8b is stored in the second block of the fail memory other than the fail memory block storing 8b. The redundancy determination in step S12 after the end of the test 3 is the same as in the test 4, and the fail memory block storing the defect data 8c of the test 3 and the defect data 8a and 8b of the test 1 and the test 2 are determined.
Simultaneously and in parallel from the fail memory block storing therein, the defective data is output to the redundancy computing unit 5 and read, and the redundancy judgment is performed. In this way, the test flow of the redundancy judgment test shown in FIG. 1 can be realized.

[0028]

As described above, when the yield of the memory IC and the actual value of the product are improved, the number of executions of the function test and the redundancy determination is increased in the conventional redundancy determination test, so that the entire test is performed. However, by performing the redundancy judgment test of the present invention, it is possible to omit the test with a short hold time and the execution of the redundancy judgment in the memory IC that passes the test with a long hold time. , It is possible to reduce the increase of the test time as a whole test.

[Brief description of the drawings]

FIG. 1 is a test flow chart of a redundancy judgment test for explaining an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a method of storing defective data in the fail memory of FIG.

FIG. 3 is a block diagram illustrating a method of storing defective data in a fail memory according to another embodiment of the present invention.

FIG. 4 is a test flow diagram illustrating a redundancy determination test of a conventional example.

5 is a test block diagram illustrating the operation of the redundancy determination of FIG.

6 is a block diagram illustrating a method of storing defective data in the fail memory of FIG.

[Explanation of symbols]

 1 Memory IC 2 Output Data 3 Comparator 4 Bad Data 5 Redundancy Calculator 6 Fail Memory 7 Data Input Bits 8a to 8e Bad Data for Tests 1 to 5 9 Address Signal 10 Control Signal 11 Input Data Signal 12 Expected Value Data Signal 13 Pattern generator

Claims (3)

[Claims] 1. A method of testing a semiconductor memory device using a test device having a fail memory for storing defective cell position data of a semiconductor memory device, wherein the defective cell position data of the semiconductor memory device is stored in the fail memory,
By storing the defective cell position data in a single or a plurality of memory blocks that are different for each functional test of the semiconductor memory device, the defective cell position data is tested by performing an arbitrary functional test item order. The method for testing a semiconductor memory device is characterized in that the number of memory tests in the fail memory is reduced. 2. The method of testing a semiconductor memory device according to claim 1, wherein the functional test of the semiconductor memory device is performed from a functional test having a higher standard grade, and a functional test having a lower standard grade is sequentially performed. 3. The semiconductor memory device according to claim 1, wherein a functional test of the semiconductor memory device is carried out from a test having a long hold time for detecting its memory holding ability, and a test having a short hold time is carried out successively. Test method.