JP2735010B2 - Semiconductor device and test method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a test method therefor, and more particularly to a semiconductor device having test data stored in a ROM and a test method therefor.

[0002]

2. Description of the Related Art In order to test whether or not a semiconductor device having various functions such as a memory and a digital logic circuit integrated on a single semiconductor substrate has a desired function, the semiconductor device has to be tested. There is a method of connecting a tester, inputting predetermined data, comparing the output data with expected value data facilitated in the tester, and determining that the data is good if they match.

[0003] Apart from this method, test data, a test control function, expected value data, and the like are built in the same semiconductor substrate, and a test is performed using the test data and an external tester. There is a method of performing tests by greatly reducing the function of.

FIG. 4 shows an example of the latter test method .
It has also been described in una JP 58- 8 5545 JP
There is The semiconductor device of FIG.
On 0, an input terminal 47 for inputting the test data from the outside, and the semiconductor device main body 41 for outputting the processing result to the output terminal 53 by executing a predetermined signal processing by receiving the test data, the semiconductor To test the device body 41
A first memory 42 for storing the order of test data, the
Wherein in response to the test data input semiconductor device main body 4
And the expected value data expected to be output from
A second memory 57, when performing a test of the semiconductor device main body 41, a test control circuit 43 to provide a test data stored in the first memory 42 in the semiconductor device main body 41, the first When the test data stored in the memory 1 is input to the semiconductor device main body 41
The semiconductor device Bei Eteiru a comparing circuit 52 for outputting data <br/> and output from the main body portion 41 for comparing the expected value stored in the second memory 57 data.

Here, the first and second memories 42, 57
Is an address counter 5 that operates in response to a clock signal.
8, the data in the memory is read out under the address control. The read test pattern is input to the main body 41 via the multiplexer (MPX) 56. The output pattern read from the second memory 57 is given to the comparison circuit 52, and the flip-flop (F
F) Compared with the response pattern of the main body 41 given via 55. In this configuration, a clock signal is supplied from a terminal 49, a control signal is supplied from a terminal 48, and the test control circuit 43 supplies a predetermined control signal to each unit. For this reason, it is only necessary to prepare signals to be supplied to the input terminals 48 and 49 in the tester, and functions in the tester are simplified.

[0006]

However, such a structure of the semiconductor device seeks to find a defect in the semiconductor device body 41 itself, but the reliability of the determination is poor. This is the first and second memories 4 for performing inspection.
This is because the reliability of the stored data in the storage devices 2 and 57 is almost the same as that of the main body 1. For example, the first memory 4
2 has a defect, the output data of the main body 41 does not naturally match the data in the second memory 57 and is determined to be defective. In this case, the semiconductor device main body 41 has no defect. In some cases, it should be judged good. Further, also in the case where the second memory 57 has a defect, a part which should be determined as a non-defective product is determined as a defective product.

Therefore, the reliability of the judgment becomes extremely poor, and the test side, that is, the first and second memories 4
It is particularly problematic that there is no means for finding the defects of the 2,57 stored data, and the implementation is poor.

In view of the above problems, the present invention has the following problems. (1) The reliability of a test circuit formed on the same substrate is considerably higher than that of the main body. (2) To increase the number of external terminals (pins) dedicated to the test and improve the consistency with the terminals of the tester. (3) A circuit configuration that allows at least double testing using different test circuits.
(4) The determination signal should be an extremely simple output signal. (5) To prevent a meaningless decrease in the production yield of semiconductor devices. (6) To be able to test the semiconductor device body even if it is found that the test circuit is defective. (7) To shorten the test time. (8) To supply a highly reliable semiconductor device body. (9) When connecting to a tester,
The role of testing should be assigned to the semiconductor device in a well-balanced manner so that complicated interfaces are not required. (10) If it is desired to change a test item after manufacturing a semiconductor device, the test item should be configured to be input from the outside immediately.

[0009]

Means for Solving the Problems] To solve the above problems <br/> present invention includes a semiconductor device body portion to be tested, the half
Test data and the Tesutode give to the conductor system body
A memory storing data for checking data errors, and reading the test data to read the semiconductor device body.
A test control circuit for controlling to input the part, and the test data check circuit for checking whether the test data stored in the memory is stored by mistake is, the same semiconductor
A semiconductor characterized by being formed on an integrated circuit substrate
Body device .

[0010]Also,Semiconductor device body to be testedDepartment
And the saidSemiconductor deviceBodyDepartmentTest data andPrevious
Corresponding to the test dataSaidSemiconductor deviceBodyDepartmentFrom
BeExpectedA memory storing expected value data,
Read out the test data andSemiconductor deviceEnter the body
A test control circuit for controlling theIn the memory
Test data stored in semiconductor deviceBodyWhen given to the department
Output todataWhenExpectations stored in the memory
Value dataComparisonCollationThen inspectMatching circuitBut the same
Semiconductor integrated circuitCharacterized by being formed on a substrate
ToA semiconductor device, and each of the aforementioned semiconductor devices
AndFrom outsideThe input serial formattest data
ToFrom serial formatParallelFormatConvertSerial-parallel conversioncircuit
ToSaidSemiconductor integrated circuitForm on substrateAnd the serial-parallel conversion
Test data output from the circuit and storing the test data
The test data output from the memory
The selector controls and outputs the output by controlling the selector by the path.
To be given to the main body.

Further, there is any error in the test data by the test data check circuit is stored in the memory is detected
When the test data output from the serial-parallel conversion circuit
To test given to the semiconductor device body portion by selecting
A method for testing a semiconductor device, characterized in that:

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 which shows a block diagram of a first embodiment of the present invention, a semiconductor device of this embodiment includes a logic circuit for performing arithmetic processing, a temporary storage memory, a ROM, and the like. A semiconductor device main body 1 configured to have the functions described above, a test-dedicated ROM 2 storing test data necessary for testing the main body 1, and an inspection as to whether the stored data in the ROM 2 is defective. An inspection circuit 4;
A serial-to-parallel conversion circuit 5 for converting serial test data input from one of the plurality of input terminals 8 into parallel data; and one of the output of the conversion circuit 5 and the data stored in the test ROM 2 And a test control circuit 3 for outputting a control signal necessary for performing a series of tests to the selector 6, a selector 6, a serial / parallel conversion circuit 5, a test ROM 2, a main body 1, etc. Are provided on the semiconductor substrate 31.

Here, the semiconductor device body 1 to be tested is
It is desirable that all the circuits operating in the normal mode are included, but the circuits may be limited to circuits that need to be tested particularly heavily. The input terminal 7 is, for example, 12
When bit data is input, it is composed of 12 lines, and the output terminal 10 is also composed of 12 lines. The control signal generating circuit that causes the main body 1 to function is not shown in the case of the normal mode operation, and the test control circuit 3 is used in the case of the test mode operation. The test control circuit 3 is connected to a terminal 9 to which a clock signal is input and a plurality of terminals 8 to which a control signal or test data is input. Whether to input a control signal or test data is determined by a combination of input signals of a plurality of terminals 8. When test data is input, the test data is output to the serial-parallel conversion circuit 5. When test data is input from the input terminal 7 when performing a test (in a second test mode described later), test data is also input from the input terminal 8 to secure data required for the test more quickly. It is input as a serial signal, converted in parallel, and input to the main unit 1 via the selector 6. In the normal mode, since the test circuit described above is not necessary,
An interface is provided to cut the input / output relationship so as not to affect the operation, but is not shown. Conversely, when the test mode is set, the control signal from the test control circuit 3 and the test data from the selector 6 are selected so as to be applied to the main body 1.

Here, referring to FIG. 3 showing an example of the inspection circuit 4, this inspection circuit is, for example, an 8-bit data 20.
And a 1-bit parity bit 23 are dedicated test ROM
The exclusive OR (Exclusive O) of a 9-bit register 24 input from 2 and a total of 8 inputs of 2 inputs
R) It has a gate 21 and only one output terminal 22.
For example, when the sum of logical 1 of the 8-bit data 20 is an even number, the parity bit 23 is set to logical 1 and
When the sum of logic 1 of the 8-bit data 20 is odd,
The parity bit 23 is set to logic 0 and is stored in the test-only ROM 2 in advance. Therefore, the ROM 2 stores the logic 1 so that the total is always odd if it is normal. A logic 1 level is output to the output terminal 22 of the gate of the two-input EX / OR 21 if normal,
If one bit or the like is erroneously stored in the 8-bit data, a logical 0 level is output to the output terminal 22. This signal can be immediately identified by monitoring the output terminal 11. A series of eight
Since the bit data is continuously input to the inspection circuit 4 and the judgment result is output, the tester for inspecting the output terminal 11 stores a series of judgment results and compares them with the address data, thereby causing an erroneous storage. The memory cell in question can be specified, but if even one bit is erroneously stored, there is no need to specify if the test-only ROM 2 is determined to be defective.

The inspection circuit 4 may be a circuit as shown in FIG. 3. In addition, a defect is determined by counting logic 1 in 8 bits and determining whether the number is odd or even. You may.

[0016] The test-only ROM 2, the test data used for testing the semiconductor device main body 1, and test data for testing circuit 4 to check an error in test data rating
And supplies test data to the selector 6 in accordance with an address signal given from the test control circuit 3,
Also, supplying the check data for checking an error of the test data and test data to the test circuit 4. The test control circuit 3 receives an address signal of the test dedicated ROM 2, a serial signal of the serial-parallel conversion circuit 5, a control signal of the selector 6, a control signal input from the external terminal 8 and a clock signal input from the external terminal 9. And an operation mode of the semiconductor device body 1. Inspection circuit 4 is a dedicated test RO
Using the test data stored in M2, it examines the test data stored in the testing only ROM2 whether there is no error, and outputs the test result to the external terminal 11. Serial format test data input from external terminal 8
The data is transmitted to the serial / parallel conversion circuit 5 via the test control circuit 3.
Is converted to a signal in a parallel format,
It is entered into. The selector 6 is Ri by the control signal from the test control circuit 3, switching between the test data from the test data and serial-parallel conversion circuit 5 from the test dedicated ROM 2, are supplied to the semiconductor device main body 1.

The operation of the semiconductor device body 1 in the test mode is performed by operating the external terminal 8 and the external terminal 9 to operate the test control circuit 3 and setting the control signal of the semiconductor device body 1 to the test mode. The semiconductor device main body 1 is set to a test mode, signal processing is performed based on test data from the selector 6, and the result is output to the external terminal 10.

In the normal test mode, the selector 6 is set by the test control circuit 3 so that the test data from the test ROM 2 is input to the semiconductor device body 1.

As a test method of the semiconductor device of this embodiment,
A first test mode and a second test mode are provided. First, the first test mode will be described.
The test control circuit 3 sets an address signal of the dedicated test ROM 2 according to a clock signal input from the external terminal 9, inputs test data to the semiconductor device body 1, and outputs a signal based on the test data written in the dedicated test ROM 2. Processing is performed, and the result is output to the external terminal 10. At this time, the test of the semiconductor device main body 1 is determined based on whether or not the signal output from the external terminal 10 matches the expected value of the signal processing based on the test data given from the test ROM 2. The external terminal 1 to which the inspection result of the inspection circuit 4 is output together with the gap external terminal 10.
1 is also monitored to determine whether there is any error in the test data written in the test ROM 2. The test control circuit 3 updates the address signal of the test ROM 2 in response to the clock signal input from the external terminal 9 and supplies the test data to the semiconductor device body 1 to sequentially test the semiconductor device body 1.

If no error is found in the test data written in the dedicated test ROM 2 based on the test result of the test circuit 4 output to the external terminal 11, the main unit 1 obtained from the output terminal 10 after processing is processed. The data and the expected value data prepared in the tester are collated, and if both data match, the semiconductor device 31 is determined to be a non-defective product and is to be shipped. If there is, the semiconductor device main body 1 is regarded as a defective circuit, and the semiconductor device 31 is discarded. Thus, the test in the first test mode is completed.

Next, the following test is performed by setting a case where a defect is found in the test ROM 2 as a second test mode. If an error is found in the test data written in the dedicated test ROM 2 based on the inspection result of the inspection circuit 4 output to the external terminal 11, the test result of that item is invalidated, and a plurality of external terminals 8 The test control circuit 3 is set to the second test mode by a specific logical combination. In this case, the selector 6 is set so that the output of the serial-parallel conversion circuit 5 is input to the semiconductor device main body 1, and the second test mode for inputting test data from outside the semiconductor device is set. Next, normal test data is transferred from the external terminal 8 through the test control circuit 3 to the serial-parallel conversion circuit 5 as a serial signal, and is input to the semiconductor device main body 1 to perform a test using normal test data. If the data obtained from the output terminal 10 matches the expected value data in the tester, the main body 1 is regarded as a non-defective product,
This semiconductor device is determined to be good. If they do not match, it is determined to be defective.

In the second test mode, data necessary for the test is also inputted from the input terminal 7 and the terminal 8
The test time is shortened because the serial data from this is added to this.

Since there is an inspection circuit 4, a ROM dedicated for testing
2, the reliability of the data in the first test mode is improved.

If the repair is not performed in the first test mode, the serial-parallel conversion circuit 5 can be used so that the test can be performed in the second test mode.
Is extremely small, and the manufacturing yield is not reduced.

Further, data to be insufficient, have to be converted to parallel signals after the input as serial signals
Runode, the number of terminals of this portion requires only one.

Since the test control function and the storage function of test-specific data are assigned to the semiconductor device, the matching with the tester is good, and a complicated interface is not required.

It should be noted that a semiconductor device determined to be non-defective in the first test mode can be further tested in the second test mode. In this case, an extremely reliable semiconductor device body can be supplied.

Further, since test data can be given from outside the semiconductor device, there is an advantage that test items can be added after the semiconductor device is manufactured.

Referring to FIG. 2 which shows a block diagram of a second embodiment of the present invention, a semiconductor integrated circuit board 3 of this embodiment is shown.
2 is a ROM 2 dedicated to the provision of the matching circuit 12
Since the third embodiment is common to the first embodiment except that expected value data is also stored in the first embodiment, description of common configurations and effects will be omitted.

The inspection circuit 4 inspects not only test data in the test ROM 2 but also expected value data.

The coincidence circuit 12 compares the expected value data in the test ROM 2 with the data output from the main unit 1, and outputs a logical 1 or 0 to the output terminal 10 if they match. The matching circuit 2 takes, for example, the complement of one data and adds this to the other data,
This is achieved by a circuit in which the added value does not match a value other than logic 0.

According to this embodiment, there is no need to prepare expected value data on the tester side, and it is not necessary to provide a circuit for checking for coincidence / mismatch on the tester side, so that the matching property with the tester is better. Becomes

The means for checking the test data written in the dedicated test ROM 2 includes various means such as a checksum in addition to the parity check shown in FIG.

The arrows in FIGS. 1 and 2 indicate the flow of data by thick lines and the flow of control signals by thin lines.

[0035]

As described above, according to the present invention, a test circuit for testing data in a test ROM, a serial / parallel conversion circuit for converting a serial signal provided from a test control circuit into a parallel signal, and the like are incorporated. By doing so, it is possible to prevent an increase in the number of external terminals and an increase in test time, and in the case where a test-dedicated ROM built in the semiconductor device has a defect, by supplying test data from outside the semiconductor device to the semiconductor device. The main body is tested, and effects such as a decrease in the yield of the semiconductor device due to a defect in the test ROM are obtained, and the above-mentioned problems are all achieved.

[0036]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram of a test circuit used in FIG. 1 or FIG. 2;

FIG. 4 is a block diagram of a conventional semiconductor device.

[Explanation of symbols]

1,41 Semiconductor device main body 2 Test-only ROM 3,43 Test control circuit 4 Inspection circuit 5 Serial-parallel conversion circuit 6 Selector 7,8,9,10,11,13,22,47,48,4
9, 53, 50 Terminal 12 Matching circuit 20 8-bit data 21 2-input EX / OR gate 23 Parity bit 24 Register 30, 31, 32 Semiconductor integrated circuit board 42, 57 Memory 52 Comparison circuit 55 Flip-flop 56 Multiplexer (MPX) 58 Address counter

Claims (6)

(57) [Claims] And 1. A be tested semiconductor device body portion, and a memory storing the test data to be supplied to the semiconductor device body portion so as to enter by reading the test data in the semiconductor device <br/> body portion wherein a test control circuit for controlling, that the test circuit to check whether the test data stored in the memory is stored by mistake, are formed on the same semiconductor integrated circuit <br/> board Semiconductor device. 2. A serial-parallel converting the test data of a serial format input from the outside from the serial form to parallel form
A conversion circuit, and test data output from the serial / parallel conversion circuit.
Test data from the memory that stores the force and the test data.
A selector for selecting and outputting the data output from the semiconductor integrated circuit.
Test circuit formed on a circuit board and from the serial-parallel conversion circuit means.
From the memory that stores the test data output and the test data.
Is output by the test control circuit
Controlling the selector to selectively output the semiconductor device main body;
2. The semiconductor device according to claim 1, wherein said semiconductor device is provided. Wherein the data for checking an error of the test data to the memo <br/> re storing the test data
3. The semiconductor device according to claim 1, wherein the semiconductor device is stored . 4. A semiconductor device main body to be tested, the test data and the test applied to the semiconductor device body portion
Obtained from the semiconductor device main body so as to correspond to Todeta
Expectations and memory storing an expected value data, a test control circuit for controlling to read out the test data inputted to the semiconductor device main body and, serial to the memory
Give the test data憶 to the semiconductor device body portion
A coincidence circuit for comparing match to examine the data with the expected value data stored in the memory to be output, the test data and the expected value data stored in the memory is erroneous when the
The same test circuit is used to check whether the
A semiconductor device formed on a semiconductor integrated circuit substrate. 5. The serial-parallel converting the test <br/> Todeta serial format input from the outside from the serial form to parallel form
A conversion circuit, and test data output from the serial / parallel conversion circuit.
Test data from the memory that stores the force and the test data.
It said semiconductor integrated times and a selector to select the output of the over data output
Test circuit formed on a circuit board and from the serial-parallel conversion circuit means.
Memory storing the test data output and the test data
Test data output from the test control circuit.
Controlling the selector to selectively output the semiconductor device main body.
5. The semiconductor device according to claim 4, wherein the semiconductor device is provided to a part. 6. The semiconductor device according to claim 2 or 5.
Stored in the memory by the inspection circuit.
When any error in it has the test data have been detected, the
The test data output from the serial-parallel conversion circuit is output to the selector
Select by, be tested applied to said semiconductor device body portion
A method for testing a semiconductor device, comprising: