JP2604468B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application Field of the Invention Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment Explanation of the Principle of the Present Invention (FIGS. 1 to 5) The present invention First embodiment (FIGS. 6 and 7) Second embodiment of the present invention (FIGS. 8 and 9) Third embodiment of the present invention (FIG. 10) Effect of the invention [Overview] Random logic in the same chip Circuits and multiport RAM
The purpose of the present invention is to provide a semiconductor integrated circuit device capable of greatly reducing the number of test terminals required for testing a multi-port memory with respect to a semiconductor integrated circuit device equipped with a logic circuit and a logic circuit in a chip. Port memory is mixed,
In a semiconductor integrated circuit device in which a different address signal, a different data signal, and a different write enable signal are input for each port from the logic circuit to each port of the multi-port memory during normal operation, when testing the multi-port memory, A first selection circuit for inputting a common address signal and a data signal input from one external terminal to each port and inputting a different write enable signal for each port, and a predetermined selection signal during the test. A second selection circuit for outputting an output signal of one of the ports to an external terminal in response to the request.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a random logic circuit and a multi-port RAM mounted on the same chip, and more particularly to an improvement of a memory test circuit capable of reducing test terminals. About.

With the recent advance in semiconductor manufacturing technology, the circuit scale that can be mounted in one chip has increased dramatically, and tens of thousands to hundreds of thousands of gates can be mounted. When the number of gates reaches this level, it is required to configure a system with one semiconductor integrated circuit. For this reason, it is indispensable to mix logic and memory in one chip.
Also, the demand for multi-port RAM is increasing for the memory to be mounted.

However, it is generally difficult to test a multi-port RAM built in a chip, and in many cases, it is necessary to add some test circuit.

[Conventional technology]

There are roughly two types of conventional RAM testing methods for a composite LSI. One is a method for testing a RAM using a random logic circuit, and the other is a method for using a test circuit. In the former method, through a random logic circuit
It is difficult to consider the address and input of the RAM, and it is similarly difficult to determine the expected output value outside the LSI.
Therefore, the latter method is common.

In this method, all inputs and outputs of the RAM are directly controlled from external terminals of the LSI, and test patterns are sent to the RAM from these test terminals. Similarly, the output of the RAM is directly output to the external terminal of the LSI, so that the RAM test can be easily performed.

[Problems to be solved by the invention]

However, in order to realize a method for testing a RAM using such a conventional test circuit, many input / output terminals are required for the test. In particular, the number of terminals in a multi-port RAM is more than twice that of a single-port RAM. Therefore, it is not easy to secure test terminals. Therefore, when using RAM with many bits or RAM with many ports,
Insufficient number of test pins for RAM test or additional circuit by sharing with test pin requires additional load on shared pins, delay time increases, and I / O cell characteristics Has worsened.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device capable of greatly reducing the number of test terminals required for testing a multiport memory.

[Means for solving the problem]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention has a logic circuit and a multi-port memory mixedly mounted in a chip,
In a semiconductor integrated circuit device in which a different address signal, a different data signal, and a different write enable signal are input for each port from the logic circuit to each port of the multi-port memory during normal operation, when testing the multi-port memory, A first selection circuit for inputting a common address signal and a data signal input from one external terminal to each port and inputting a different write enable signal for each port, and a predetermined selection signal during the test. A second selection circuit for outputting an output signal of one of the ports to an external terminal in response to the request.

[Action]

According to the present invention, a test signal is commonly distributed to each port of the multi-port memory, and a test of the multi-port memory is performed based on the distributed test signal.

Therefore, the multi-port memory can be tested as a plurality of single-port memories, and the number of external terminals required for inputting and outputting test signals and test data is greatly reduced.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

Explanation of principle FIGS. 1 to 5 are diagrams for explaining the basic principle of the present invention. Although there are many types of multi-port memories, a dual-port RAM will be described here as an example. In FIG. 1, 1 is a random logic circuit 2 and a dual port RAM 3
Is a semiconductor integrated circuit (semiconductor integrated circuit device) mounted on the same chip. The semiconductor integrated circuit 1 is a random logic circuit 2, a dual-port RAM (multi-port memory) 3,
It is configured to include test input terminals 4 to 10, test output terminals 11, input selectors 12 to 19 (first selection circuit), inverter 20, and output port selectors 21 and 22 (second selection circuit). .

The test input terminals 4 to 10 have a test mode signal TM, a port selector signal PS, and a test input data signal, respectively.
TI (1a), test address signal TA (1b), test write enable signal TWE1 (1d), TWE2 (1d), test
The RAM enable signal TRE (1c) is input, and a test output data signal TO is output from the test output terminal 11.

The random logic circuit 2 exchanges data with the dual-port RAM 3 during normal operation, but is separated from the RAM 3 during the RAM3 test. Dual port RAM3 is A
It has two input / output ports, a port and a B port, an address, a write enable and a RAM enable terminal, and can be directly controlled from outside the LSI via a switch by a test mode signal TM from a test input terminal 4.
The input selectors 12 to 19 are selectors for selecting a normal operation and a test operation for the RAM input, and are controlled by the TM. Test inputs are connected in common to each port except for the write enable, thereby reducing the number of terminals. FIG. 2 is a circuit example of the input selectors 12 to 19. In FIG. 2, 31 indicates an inverter, 32 and 33 indicate AND gates, and 34 indicates an OR gate. On the other hand, the output port selectors 21 and 22 output the port selector signal PS
Is a selector for selecting one of the output ports of the dual port RAM 3 in accordance with the formula (1). By selecting one of the output ports, the number of terminals is reduced and the output result of the RAM is transmitted to the test output terminal 11. Figure 3 shows output port selector 2
These are circuit examples 1 and 22, in which 35 denotes a switching gate. The test input terminals 4 to 10 and the test output terminal 11 are input / output of the dual port RAM 3 during the RAM test, but are connected to the random logic circuit 2 in a normal state. Whether the terminals 4 to 11 are used as test terminals may be determined by the TM.

Dual port RAM3 test input data signal 1a, test address signal 1b, test RAM enable signal 1c
Are connected in parallel to all ports, and the test write enable signal 1d is provided independently for each port. Dual port
The output of each port of the RAM 3 is connected to the port selectors of the output port selectors 21 and 22.

FIG. 4 is a block diagram of the dual port RAM 3. In FIG. 4, the inside of the dual port RAM 3 is roughly divided into an A port section and a B port section, and the A port section includes a buffer 41, an address buffer 42, an address transition detection circuit (ATD) 43, a precharge circuit 44, and a row decoder 45. , Column decoder 4
6, sense amplifier 47, write amplifier 48, column select 4
9 and a memory cell array 50 in which storage cells are arranged in a matrix in a row and column direction with a predetermined capacity. Similarly, the B port portion includes a buffer 51, an address buffer 52,
Address transition detection circuit (ATD) 53, precharge circuit 5
4, row decoder 55, column decoder 56, sense amplifier 5
7, a write amplifier 58, a column select 59, and a memory cell array 50. Therefore, as a representative of the A port section, the buffer 41 buffers the write enable signal WEI for controlling the writing and reading of data from the control terminal (A port), and
5, column decoder 46, sense amplifier 47, write amplifier 4
8 and the address buffer 42 buffers the external address (IA00 to IA _(t-1) ) of the A port which is input by multiplexing the row address and the column address. The signals are output to the detection circuit 43, the row decoder 45, and the column decoder 46. The address transition detection circuit 43 detects and outputs the transition state based on the external address sent from the address buffer 42, and transmits this to the precharge circuit 44 and the sense amplifier 47. The precharge circuit 44 precharges the data lines of the memory cell array 50 according to the detection result. The row decoder 45 decodes the transmitted external address or internal address, and selects and activates one of a number of word lines of the memory cell array 50 according to the decoding result. Column decoder 46 decodes the transmitted external address and outputs it to column select 49. The write amplifier 48 buffers an external input decode (I00 to I _(b-1) ), outputs this decoder to the column select 49, and outputs a large number of bits of the memory cell array 50 according to the decode result from the column decoder 46. Select one of the lines. Sense amplifier 47 is column select 49
And amplifies the potential of the selected bit line via the data of the memory cell connected to this bit line (A00 _- D _(b-1) )
Is read. The above operation is exactly the same for the B port. The internal configuration of the dual-port RAM 3 shown in FIG.
The connection method of the test input / output terminal connected to RAM3 is different from the conventional one. That is, the IA00 to IA _(t-1) address (port A) and the JB00 to JB _(t-1) address (port B) are commonly connected, and the REIA (port A) and REJB
(A port) are connected in common, and write enable WE
The I (A port) and the write enable WEJ (B port) are independent.

Fig. 5 shows the input waveform from the external terminal and the dual port RA.
6 is a timing chart of test data showing an output waveform from M3. In FIG. 5, the common address is TA, the common input is TI, and the common addresses A1 to A4 are considered to be a combination of "0" and "1", and the same address is repeatedly changed by two patterns. “Undefined” among the common inputs TI means that any value is acceptable.

Port A is written by TWE1, and port A is written twice in FIG. The port B also writes at another time by TWE2.

For example, when the input D1 is input from the A port side and the write enable TWE1 returns to "H", reading is performed. However, as shown in FIG.
The LSI output comes out of the port via the output terminal 11 as TO. Change the address and data D2 from the B port.
Is written, the address is not changed, so that the address is read out with the address as it is, and D2 is output from the A port to the outside. Since the A port is selected by the port selection signal PS, the output is output from the A port in the above example,
If the PS is inverted, the output of the B port will be selected. Table 1 shows which port is selected for the input of PS, TWE1, and TWE2.

Hereinafter, the test method will be described.

(1) Test mode setting The internal RAM 3 is disconnected from the random logic circuit 2 by setting the externally applied test mode signal TM to “L”.
Put the common test terminal in the test state.

(2) Selection of port to be tested A read port is selected by a selection signal PS given from outside. The write port is selected by the test write enable signal TWEn. Table 1 shows the combinations of ports to be tested.

(3) Execution of test Since the multi-port RAM 3 can be regarded as a single-port RAM by performing (1) and (2), a test is performed using a test pattern for the single-port RAM. When the test is completed for one combination of ports, the test is performed similarly by changing the combination of ports in the procedure of (2). A test may be performed for all possible port combinations in this way.

By providing the test circuit and the enable terminal of the RAM as shown in Table 1, one dual-port RAM3 is provided.
Can be regarded as four single-port RAMs and a test can be performed.

Hereinafter, embodiments will be described based on the above basic principle. 6 and 7 show a first embodiment of a semiconductor integrated circuit device according to the present invention.
This is an example applied to a case where one dual port RAM (A) of words × 4 bits and one dual port RAM (B) of 32 words × 2 bits are included. In the description of this embodiment, the same components as those in the principle explanatory diagrams shown in FIGS. 1 to 4 are denoted by the same reference numerals and symbols.

In FIG. 6, reference numeral 61 denotes a 16-word × 4-bit dual-port RAM (A), 62 denotes a 32-word × 2-bit dual-port RAM (B), and the dual-port RAMs 61 and 62 are connected to a random logic circuit (not shown). Have been. Although the results other than the test circuit and the MM terminal are omitted for easy understanding of the connection state of the test circuit, they are connected in the same manner as in the principle explanation shown in FIG. In the figure, 8 to 10 and
63 to 68 are external input terminals, 69 to 71 are external output terminals,
External input terminals 63 to 65 have input data signals TI0 to T for testing.
I3 is connected to the external output terminals 66 to 68 by the test address signal TA.
0 to TA4 are input, respectively, and the test inputs TI0 to TI3 and the test addresses TA0 to TA4 are connected in parallel to all ports (in this embodiment, the A and B ports of the dual port RAMs 61 and 62). You. The test input terminals 8 to 10 have test write enable signals.
TWE1 to TWE2 and a test RAM enable signal TRE are input, respectively, and these TWE1, TWE2 and TRE are connected in parallel to the respective dual port RAMs 61 and 62. On the other hand, with each bit A ₀ to A ₃ of the A port of the dual port RAM61 are connected to each via a port selector 72-74 69-71, each bit B ₀ .about.B ₃ of the B port Port Selector
The respective bits A ₀ and A ₁ of the A port (port 1) and the respective bits B ₀ and B of the A port (port 1) of the dual port RAM 61 are connected to the external output terminals 69 to 71 via 75 to 77, respectively. _{1 is} also connected to external output terminals 69 to 70 via port selectors 78 to 81, respectively. Therefore, the test inputs TI0 to TI3, the test addresses TA0 to TA4, and the test RAM enable TRE of the dual-port RAMs 61 and 62 are shared and provided to all the ports of the dual-port RAMs 61 and 62. Dual port RAM6
The output of each port of 1 and 62 is output from the external output terminals 69 to 71 via the port selectors 72 to 81 to the test output data signal TD0.
Output to the outside as ~ TD3. The test write enable TWE1 and TWE2 are provided independently for each of the dual port RAMs 61 and 62. Above port selector
Control signal S ₀ to S ₃ applied to 72-81 are created by the decoder shown in FIG. 7 based on the output port control signals PS1, PS2. FIG. 7 is a circuit diagram of a decoder 82 to create a S ₀ to S ₃ from the output port control signals PS1, PS2, in the figure, 83 and 84 inverters, 85 to 88 denotes a NAND gate.

Table 2 is a table showing the relationship between the combination of the output port control signals PS1 and PS2 and the test random enable signals TWE1 and TWE2 and the corresponding ports. In the table, the RAM to be tested refers to the dual port RAMs 61 and 62. Show. Therefore, the second
Dual port RAMs 61 and 62 according to the combinations shown in the table
Test signals PS1, PS2, TWE1, TWE2
And a test is performed for all port combinations, a 16-word × 4-bit dual-port RA
M61 and 32 words x 2 bits dual port RAM62, 16 words x 4 bits single port RAM and 32 words x 2
The test can be performed assuming a combination of two bit single port RAMs. The test pattern that needs to be prepared in this case is 16 words x 4 bits and
Since only 32 words × 2 bits of data for a single port RAM are required, the number of test terminals can be significantly reduced. Here, since the test write enable signal must be provided independently for each port, if the number of ports increases, the number of ports increases accordingly, but other test external terminals are dual port RA.
By performing the test by regarding M as a single-port RAM, it is possible to reduce the number by approximately half. In particular, even if the number of built-in memories increases, the number of external test terminals of the entire chip hardly increases, which is very advantageous when a plurality of memories exist in the chip.

8 and 9 show a second embodiment of the semiconductor integrated circuit device according to the present invention.
FIG. 3 is a diagram showing an embodiment, and this embodiment is configured as a multi-port RAM having 1
This is an example applied to a case where one 3-port RAM (C) of 6 words × 4 bits is included. In describing the present embodiment, the first
The same components as those of the embodiment are denoted by the same reference numerals and symbols, and the description of the overlapping portions will be omitted.

In FIG. 8, 91 is a 3-port of 16 words × 4 bits.
This is a RAM (multi-port memory), and the three-port RAM 91 is connected to a random logic circuit (not shown). The test input data signals TI0 to TI3 are connected to a 3-port RAM 91,
The test address signals TA0 to TA3 are connected in parallel to all ports (A port, B port and C port in this embodiment) of the three-port RAM 91. The test write enable signal TWE is directly connected to the 3-port RAM 91,
The test write enable signal TRE is independently connected for every port. On the other hand, each bit A _{0 to} A _{3 of the} A port
Sets the port selectors 72 to 74 to the B port bits B _{0 to} B ₃
Sets the port selectors 75 to 77 to the respective bits C _{0 to} C ₃ of the C port.
Are connected in parallel to external output terminals 69 to 71 via port selectors 92 to 94, respectively. The port selector 72 ~
Control signal S ₀ to S ₂ given to 77,92～94 is created by the decoder 95 shown in FIG. 9. In FIG. 9, reference numerals 96 and 97 indicate inverters, and reference numerals 98 to 100 indicate NAND gates.

In this embodiment, the test write enable signal TWE is 1
Table 3 shows the relationship of the corresponding ports when combined with the output port control signals PS1 and PS2. Therefore, a 16-word × 4-bit 3-port RAM can be tested as a 16-word × 4-bit single-port RAM, and the number of external test terminals can be greatly reduced.

FIG. 10 is a diagram showing a second embodiment of the semiconductor integrated circuit device according to the present invention. This embodiment is a dual port RAM (D) of 16 words × 4 bits and a ROM of 32 words × 4 bits.
This is an example in which (E) is included.

The same components as those of the first embodiment are denoted by the same reference numerals and symbols, and the description of the overlapping portions will be omitted.

In FIG. 10, reference numeral 101 denotes a 16-word × 4-bit dual-port RAM (multi-port memory), and reference numeral 102 denotes a 32-word × 4-bit ROM.
Are connected to a random logic circuit (not shown).
In this embodiment, only the test address signals TA0 to TA3 and the test RAM enable signal TRE are connected to the ROM 102,
From M102 each bit D ₀ to D ₃ are connected in parallel via the port selector 103 to the external output terminal 69, 71.

Therefore, in this embodiment, one PS and one TWE are required, and the relationship of the corresponding ports is shown in Table 4. As described above, even if a memory other than the multi-port RAM exists, the test can be performed using the same circuit.

[Effects of the Invention] According to the present invention, the number of test external terminals used when testing a multiport memory can be significantly reduced.

[Brief description of the drawings]

1 to 5 are diagrams for explaining the principle of the present invention, FIG. 1 is an overall configuration diagram, FIG. 2 is a circuit diagram of an input selector thereof, and FIG. 3 is a circuit diagram of an output port selector thereof. 4 is a block diagram of the dual port RAM, FIG. 5 is a timing chart of the test decoder, FIGS. 6 and 7 are diagrams showing a first embodiment of the semiconductor integrated circuit device according to the present invention, FIG. 6 is an overall configuration diagram, FIG. 7 is a circuit diagram of the decoder, FIGS. 8 and 9 are diagrams showing a second embodiment of the semiconductor integrated circuit device according to the present invention, and FIG. FIG. 9 is a circuit diagram of the decoder, and FIG. 10 is an overall configuration diagram showing a third embodiment of the semiconductor integrated circuit device according to the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit (semiconductor integrated circuit device), 2 ... Random logic circuit, 3, 61, 62, 101 ... Dual port RAM (multiport memory), 4-10 ... Test input terminal, 10 ... ... Test output terminals, 12 to 19 ... Input selector (first selection circuit), 20, 31, 83, 84, 96, 97 ... Inverter, 21, 22 ... Output port selector (second selection circuit) ), 32, 33 ... AND gate, 34 ... OR gate, 35 ... Switching gate, 41, 51 ... Buffer, 42, 52 ... Address buffer, 43, 53 ... Address transition circuit, 44, 54 ... … Precharge circuit, 45, 55… Row decoder, 46, 56… Column decoder, 47, 57… Sense amplifier, 48, 58… Write amplifier, 49, 59… Column selector, 50… Memory cell array , 63-68… external input terminal, 69-71… external output terminal, 72-81, 92-94 , 103, 104: Port selector, 82, 95: Decoder, 85-88, 98-100: NAND gate, 91: 3-port RAM (multi-port memory), 102: ROM, TM: Write mode Signals, PS, PS1, PS2: Port selector signal, TI, TI1 to TI3: Input data signal for test, TA, TA1 to TA4: Test address signal, TWE, TWE1, TWE2: Write enable signal for test, TRE: Test RAM enable signal.

Claims (1)

(57) [Claims] 1. A logic circuit and a multi-port memory are mixedly mounted in a chip, and in a normal operation, different address signals, different data signals, and different write enable signals from the logic circuit to each port of the multi-port memory for each port. In the semiconductor integrated circuit device to which is input, when testing the multi-port memory, a common address signal and a data signal input from one external terminal are input to each port, and a different write enable signal is provided for each port. And a second selection circuit for outputting an output signal of any one of the ports to an external terminal according to a predetermined selection signal during the test. Integrated circuit device.