JP2001014842A - Semiconductor memory and logical lsi mixingly equipped with memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the operation of a row/column simultaneous access function with a small number of pins like at a time when addresses are multiplexed. SOLUTION: Whether an address signal is to be outputted to a row decoding circuit 12 or not is selected by a selector 14 and whether the address signal is to be outputted to a column decoding circuit 13 or not is selected by a selector 17. The address signal to be inputted to an external terminal is stored in a latch circuit 15 and, moreover, either the address signal to be inputted to the external terminal or the address signal stored in the latch circuit 15 is selected by a multiplexer 16 to be outputted to either the selector 14 or the selector 7. Then, when a command for simultaneously inputting the address signal to the row decoding circuit 12 and the column decoding circuit 13 is inputted to a command generating circuit 18, the signal stored in the latch 15 is selected in the multiplexer 16 to be outputted and also the sectectors 12, 17 are set to output states.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a simultaneous row / column access function and a logic LSI with embedded memory.

[0002]

2. Description of the Related Art A bank interleave function of a semiconductor memory device is to activate a word line in two or more different banks.
This function executes a series of operations such as read / write operation and precharge operation with a certain time difference. At this time, a row operation may be performed in another bank at the same time as a column operation is performed in a certain bank. For example, after activating the word line of the row address specified in a certain bank,
A write operation or a read operation (column operation) is performed on a memory cell at an intersection between a bit line of a column address specified in the same bank and the word line, and a word of a different row address specified in another bank is simultaneously executed. This is the case where the line is activated (row operation).

A conventional technique for realizing the simultaneous row / column access function will be described. FIG. 9 is a block diagram showing a configuration of a conventional semiconductor memory device for realizing simultaneous access.

The memory cell array 101 is configured by arranging regular memory cells MC having a predetermined capacity in a matrix of rows and columns. In this memory cell array 101,
A two-dimensional address space represented by a row address of Nra bits and a column address of Nca bits is allocated. The size of the row address and column address is
It is determined according to the storage capacity of the memory cell array 101.

A row decode circuit 102 decodes a row address and selects a row of the memory cell array 101. The row decode circuit 102 decodes a word line W based on the row address.
Select L. The column decode circuit 103 decodes a column address to select a column of the memory cell array 101, and selects a bit line BL based on the column address.

The command generation circuit 104 decodes an Ncm-bit coded command and activates a word line WL (row-related command) or a command (column command) for executing a read or write operation. Command).

In an operation such as reading or writing, a memory cell MC at an intersection between a word line WL and a bit line BL selected by a row decode circuit 102 and a column decode circuit 103 is accessed, and an operation based on a command is performed. Operations such as data reading and writing are performed on the memory cells MC by instructions. However, during a write operation, Nd-bit write data input from the outside is written to the memory cell.

The simultaneous row / column access function at the time of bank interleaving is a function of executing a column operation in one bank and executing a row operation in another bank at the same time. Therefore, it may be necessary to simultaneously issue a column address and data for a column operation and a row address for a row operation. Further, it is necessary to issue a row command and a column command. Accordingly, as input pins, a column address line 105 for transmitting a column address of Nca bits, a data line 106 for transmitting data of Nd bits, a row address line 107 for transmitting a row address of Nra bits,
And N (Ni = Nca + Nd + Nra + Ncm) of the command lines 108 for transmitting the Ncm-bit command.

Here, the bit number Ncm of the command line 108
Is calculated from the number of commands = 2 ^Ncm . For example, if the number of commands is 16, the number of bits Ncm is 4 bits. As described above, the LS in which the input pins can be prepared independently
If it is I, there is no problem, but there is a practical limit to the number of pins.

In order to avoid the limitation of the number of pins, a configuration as shown in FIG. 10 is practical. 9 is different from the column address line 105 and the data line 106 in FIG.
And the pin used for the row address line 107 are shared. The Nmx-bit address and data line 110 after the sharing is connected to the column address line 105
By comparing the sum (Nca + Nd) of the number of bits of the data line 106 with the number of bits (Nra) of the row address line 107, if the larger number of bits (pins) is obtained, they can be shared.

For example, the sum of the bit numbers of the column address line 105 and the data line 106 is 12, and the row address line 107
If the number of bits is 13, the larger of the 13 bits allows input of address and data. In this case,
The common address and data line 110 is Nmx = 13
The signal line for transmitting the bit and row address is Nra =
A signal line for transmitting 13 bits, a column address and data has Nca + Nd + 1 = 13 bits. One extra bit of the signal line for transmitting the column address and data is Don't Care.

If the input to the shared Nmx-bit address and data line 110 is a row address, a row-related command is also input to the command line 111 for transmitting a command. Address and data line 11
If what is input to 0 is a column address, a column command is also input to the command line 111. Therefore, when a row address is input, a signal for validating the output is output from the command generation circuit 104 to the selector 105, and the row address is input to the row decode circuit 102. When a column address and data are input, a signal for validating the output is output from the command generation circuit 104 to the selector 106, the column address is input to the column decode circuit 103, and data writing is enabled. This technique is generally called address multiplex.

[0013]

However, in the case of address multiplexing, since row-related operations and column-related operations cannot be performed simultaneously, the operation of the simultaneous row / column access function is performed seamlessly (in a seamless state). It is impossible.

In the test of the row / column simultaneous access function of the semiconductor memory device when the address multiplexing is performed, it is necessary to minimize the number of test pins. It is not possible to perform and test the operation seamlessly.

As described above, in a semiconductor memory device or a memory embedded logic LSI having a simultaneous row / column access function, when there is only a limited number of pins as in the case of address multiplexing, the simultaneous row / column access function The operation cannot be performed seamlessly (seamless state), and furthermore, it becomes impossible to execute the operation of the simultaneous row / column access function even in a test that requires a reduction in the number of pins. I have.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a necessary address or data is latched in a previous operation cycle in advance, and the latched address or data is used simultaneously with an address or data used in a current operation cycle. Alternatively, it is an object of the present invention to provide a semiconductor memory device and a memory-embedded logic LSI capable of realizing an operation of a simultaneous row / column access function with a small number of pins as in the case of address multiplexing by issuing data.

[0017]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a memory cell array in which memory cells are arranged in a matrix, and an external terminal to which an address signal is inputted from outside. A row decode circuit for decoding the address signal to select a row of the memory cell array; a column decode circuit for decoding the address signal to select a column of the memory cell array; A first selector that is provided between the external terminal and the column decode circuit, the first selector that is provided between the external terminal and the column decode circuit and that selects whether to output the address signal to the row decode circuit; A second signal for selecting whether or not to output a signal to the column decode circuit;
Selector, a latch circuit for storing an address corresponding to the address signal input to the external terminal, and one of the address signal input to the external terminal or the address signal stored in the latch circuit And a command for inputting different address signals to the row decode circuit and the column decode circuit simultaneously from the first multiplexer that outputs the selected signal to one of the first selector and the second selector. A control circuit that, when input, causes the multiplexer to select and output a signal stored in the latch circuit, and set the first selector and the second selector to an output state. I do.

Further, the semiconductor memory device according to the present invention comprises a memory cell array in which memory cells are arranged in a matrix, an external terminal to which an address signal is inputted from outside, and a plurality of memory cells based on a command inputted from outside. A control circuit for generating a control signal of the following, a first selector for selecting whether to output the address signal input to the external terminal in response to a first control signal generated by the control circuit, A row decode circuit for decoding the address signal output from the first selector to select a row of the memory cell array; and a second control signal generated by the control circuit. A latch circuit for storing an address corresponding to the input address signal; and a first and a second input terminal, wherein the latch circuit is input from the external terminal to the first input terminal. A first multiplexer that selects and outputs one of a dress signal and the address signal input from the latch circuit to the second input terminal in response to a third control signal generated by the control circuit; A second selector for selecting whether or not to output the address signal output from the first multiplexer to the column decode circuit in response to a fourth control signal generated by the control circuit; A column decoding circuit for decoding the address signal output from the selector to select a column of the memory cell array; and a command for simultaneously inputting the different address signals to the row decoding circuit and the column decoding circuit. Is input to the control circuit, the control circuit stores the data stored in the latch circuit with respect to the first multiplexer. And outputting the third control signal for selecting and outputting the address signal, and outputting the first control signal and the fourth control signal for setting the first selector and the second selector to the output state. It is characterized by the following.

A semiconductor memory device according to the present invention has a memory cell array in which memory cells are arranged in a matrix, an external terminal to which an address signal and data are inputted from the outside,
A row decode circuit for decoding the address signal to select a row of the memory cell array; a column decode circuit for decoding the address signal to select a column of the memory cell array; the row decode circuit and the column A data line for writing the data input together with the address signal to a memory cell at an intersection of a row and a column selected by a decode circuit is provided between the external terminal and the row decode circuit. A first selector for selecting whether to output the address signal to the row decode circuit, and a first selector provided between the external terminal and the column decode circuit, wherein the address signal is provided to the column decode circuit, and A second selector for selecting whether to output the data input together with the address signal to the data line, and A latch circuit provided between the external terminal and the second selector for storing the address signal and data input to the external terminal; and the address signal and data input to the external terminal or the latch A multiplexer for selecting one of the address signal and data stored in the circuit and outputting the selected address signal and data to the second selector; When a command for simultaneous input to the decode circuit is externally input, the first selector is set to an output state, and the multiplexer selects and outputs a signal stored in the latch circuit; and And a control circuit for setting the second selector to the output state.

Further, the semiconductor memory device according to the present invention has a memory cell array in which memory cells are arranged in a matrix, an external terminal to which an address signal and data are inputted from the outside,
A row decode circuit for decoding the address signal to select a row of the memory cell array; a column decode circuit for decoding the address signal to select a column of the memory cell array; the row decode circuit and the column A data line for writing the data input together with the address signal to a memory cell at an intersection of a row and a column selected by a decode circuit is provided between the external terminal and the row decode circuit. A first selector for selecting whether to output the address signal to the row decode circuit, and a first selector provided between the external terminal and the column decode circuit, wherein the address signal is provided to the column decode circuit, and A second selector for selecting whether to output the data input together with the address signal to the data line, and A latch circuit provided between an external terminal and the first selector for storing an address corresponding to the address signal input to the external terminal; and the address signal input to the external terminal or the latch A multiplexer for selecting one of the address signals stored in the circuit and outputting the selected address signal to the first selector; a column decoding circuit for transmitting the address signal to the row decoding circuit; and a column decoding circuit for transmitting an address signal and data different from the address signal to the column decoding circuit. When a command for simultaneously inputting the signals is input from the outside, the multiplexer selects and outputs the signal stored in the latch circuit, sets the first selector to the output state, and sets the second selector to the output state. And a control circuit for setting the output state to the output state.

Further, the memory embedded logic L according to the present invention
SI is a memory cell array in which memory cells are arranged in a matrix, an external terminal to which an address signal is input from the outside, a row decode circuit for decoding the address signal and selecting a row of the memory cell array, A column decoding circuit for decoding the address signal to select a column of the memory cell array; and a column decoding circuit provided between the external terminal and the row decoding circuit for outputting the address signal to the row decoding circuit. A first selector for selecting whether or not to output the address signal to the column decode circuit, the second selector being provided between the external terminal and the column decode circuit; A latch circuit that stores an address corresponding to the address signal input to the terminal, and the address signal input to the external terminal or A first multiplexer that selects one of the address signals stored in the latch circuit and outputs the selected address signal to one of the first selector and the second selector; And when a command for simultaneous input to the column decode circuit is externally input, the multiplexer selects and outputs the signal stored in the latch circuit, and outputs the first selector and the second selector. And a control circuit for setting the state.

According to the present invention, there is provided a semiconductor memory device or a memory-embedded logic LSI having an interface with a small number of pins, as in the case of address multiplexing.
In order to perform row and column operations at the same time, it is possible to latch necessary addresses or data in a previous operation cycle and issue the addresses or data latched simultaneously with addresses or data used in a current operation cycle. I have. Thereby, the operation of the row / column simultaneous access function can be realized, and the test in this state can be realized.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings by taking a semiconductor memory device having a memory cell array in which a two-dimensional address space of rows and columns is allocated as an example.

[First Embodiment] FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

This semiconductor memory device has a memory cell array 11 in which memory cells MC are arranged in a matrix of rows and columns, a row decode circuit 12 for selecting a word line WL from an input row address, and an input column. A column decode circuit 13 for selecting a bit line BL from an address;
Receiving the row address input to the input terminal IN1,
And a selector 14 for selecting whether or not to output the row address to the row decode circuit 12.

Further, in this semiconductor memory device, a latch circuit 15 for latching a column address and data input to an input terminal IN1, and a column address and data input to an input terminal IN1 and output from the latch circuit 15 A multiplexer 16 for receiving a column address and data and selecting and outputting one of the column address and data;
And a selector 17 for selecting whether or not to output the data to the output terminal 3.

Further, the semiconductor memory device has an input terminal IN
2, a command generation circuit 18 for generating various commands, and an AND operation of a simultaneously issued command and a row command issued when a row operation and a column operation are simultaneously started. An AND circuit 19 and an AND circuit 20 that performs an AND operation using the simultaneous command and the column command are provided.

The memory cell array 11 includes a word line W
A regular memory cell MC of a predetermined capacity is arranged at the intersection of L and the bit line BL in a matrix of rows and columns. The memory cell array 11 is assigned a two-dimensional address space represented by a row address of Nra bits and a column address of Nca bits. The number of bits of the row address and the column address is determined according to the storage capacity of the memory cell array 11. Input terminal IN
1 is input with a row address of Nra bits, a column address of Nca bits and data of Nd bits. The input terminal IN1 has Nra bits or (Nca + N
d) Of the bits, it has a pin number capable of transmitting the larger bit number (Nmx).

The selector 14 selects whether or not to output a row address to the row decode circuit 12 in response to a control signal CL1 from the AND circuit 19. The row decode circuit 12 is for decoding a row address and selecting a row of the memory cell array 11, and selects a word line WL based on the row address.

An Ncm-bit command is input to the input terminal IN2. The command generation circuit 18 decodes the Ncm-bit coded command, and causes the latch circuit 15 to latch a column address and data by using a / LOAD signal and a row / column simultaneous access to execute a row / column simultaneous access. A COLUMN signal, a / ACTIVE signal (row command) for activating the word line WL, and a signal (column command) for executing a read or write operation are generated. Here, taking the write operation as an example
Describe only the / WRITE signal. / Represents a bar, indicating that it is an inverted signal. The latch circuit 15 sets whether or not to latch the input column address and data in response to / LOAD.

In response to / ROW WITH COLUMN, the multiplexer 16 having the first terminal and the second terminal inputs the signal input to the first terminal and the latch circuit 1 input to the second terminal.
5 (column address and data) and outputs it to the selector 17. In other words, the multiplexer 16 processes the column address and data input from the outside as a normal operation (operation not simultaneously issued), and processes the column address and data previously latched by the latch circuit 15 as an simultaneous operation. In some cases, the output is switched.

The selector 17 responds to the control signal CL2 from the AND circuit 20 to convert the column address and data output from the multiplexer 16 into the column decode circuit 1
3 and data lines DL. The column decode circuit 13 decodes a column address and selects a column of the memory cell array 11, and selects a bit line BL based on the column address.

The AND circuit 19 performs an AND operation on / ROW WITH COLUMN and / ACTIVE output from the command generation circuit 18, and outputs a control signal CL1 based on the operation result. The AND circuit 20 includes a command generation circuit 18
AND operation is performed with / ROW WITH COLUMN and / WRITE output from the controller, and a control signal CL2 is output from the operation result.

Next, an operation example of the simultaneous row / column access function of the semiconductor memory device of the first embodiment will be described.

In operations such as reading and writing, the memory cell MC at the intersection of the word line WL and the bit line BL selected by the row decode circuit 12 and the column decode circuit 13 is accessed. Then, operations such as data reading and writing are performed on the memory cells by an operation command based on the command. However, at the time of a write operation, externally input write data is input via a data line.

The simultaneous row / column access function at the time of bank interleaving is a function of executing a column operation in one bank and executing a row operation in another bank at the same time. Therefore, it is necessary to simultaneously issue a column address and data for a column operation and a row address for a row operation. The operation of such a row / column simultaneous access function is as follows, taking a write page operation as an example.

FIGS. 2A and 2B are timing charts showing the operation of the simultaneous row / column access function.
In FIG. 2A, BANK # 0 and BANK # 1 indicate two banks included in the semiconductor memory device. / ACTIVE, / PRECHAG
E, / WRITE, and / LOAD indicate commands output from the command generation circuit 18 based on the command CM input to the input terminal IN2. / Represents a bar, indicating that it is an inverted signal. The row bank selection signal is supplied by some bits of the row address input to the input terminal IN1. The column bank selection signal is supplied by a column address and some bits of data input to the input terminal IN1. The row address, column address, and data in FIG. 2A indicate signals input to the input terminal IN1.

The column address and data in FIG. 2B indicate signals which are latched by the latch circuit 15 and further selected and output by the multiplexer 16. / ROW WIT
H COLUMN indicates a command output from the command generation circuit 18 based on a command input to the input terminal IN2.

First, the outline of the operation will be described. FIG. 2 (a),
According to the timing chart shown in (b), there are two cycles T9 and T15 in which the row operation and the column operation are simultaneously executed in different banks. In cycle T9,
The operation of writing (Wt) is performed by BANK # 0, and the operation of activation (Act) is performed by BANK # 1. At this time, row
The address on the side is selected by RBa, the address on the column side is selected by CAe, and the write data is Ae. In cycle T15, an activation (Act) operation is performed in BANK # 0, and a write (Wt) operation is performed in BANK # 1. At this time, the row (row) side address is selected by RAb, the column (column) side address is selected by CBc, and the write data is Bc.

As shown in FIG. 2A, a / LOAD signal is generated from the command generation circuit 18 in cycle T4, and the column address CAe and data Ae are latched in the latch circuit 15. Then, in a cycle T9, the command generation circuit 18 generates a / ROW WITH COLUMN signal for simultaneously issuing a row address / column address and data. As a result, the row address RBa input to the input terminal IN1 is issued, and at the same time, the latch circuit 15
Column address CAe and data Ae latched in
Is issued.

In the cycle T12, the command generating circuit 18 generates a / LOAD signal, and the latch circuit 15 latches the column address CBc and the data Bc. Then, in a cycle T15, the command generation circuit 18 generates a / ROW WITH COLUMN signal for simultaneously issuing a row address / column address and data. As a result, the row address RAb input to the input terminal IN1 is issued, and at the same time, the column address CBc and data Bc latched in advance by the latch circuit 15 are issued.

Next, the operation for realizing the row / column simultaneous access function will be described in detail. As shown in FIG. 2A, in a cycle T1, the row address RAa is input to the input terminal IN1. At the same time, the "L" level of the / ACTIVE signal instructing activation from the command generation circuit 18 is given.
Is output to the AND circuit 19. From the AND circuit 19, “L” of the control signal CL 1 that makes the output valid is output to the selector 14. As a result, the selector 14 outputs the row address RAa to the row decode circuit 12. At this time, since the row bank selection signal is "L", BANK
# 0 is activated (Act). The selector 14
When "L" is input, the output is valid, and when "H" is input, the output is invalid. When the row bank selection signal is "L", BANK # 0 is selected.
NK # 1 is selected.

The row address RAa is also input to the first terminal of the multiplexer 16 and the latch circuit 15.
The “H” of the / ROW WITH COLUMN signal is supplied to the multiplexer 16.
Is input, the multiplexer 16 outputs the row address RAa input to the first terminal to the selector 17. However, from the command generation circuit 18 to the AND circuit 2
Since “H” of the / WRITE signal and “H” of the / ROW WITH COLUMN signal are input to 0, the “H” of the control signal CL 2 is input from the AND circuit 20 to the selector 17.
Therefore, the selector 17 becomes invalid and the row address RA
a is not output. The selector 17 makes the output valid when “L” is input, and makes the output invalid when “H” is input. Subsequently, in cycles T2 and T3, BA
NK # 0 enters a non-operation state.

Next, in cycle T4, the input terminal I
The column address CAe and the data Ae are input to N1. At the same time, “L” of the / LOAD signal is output from the command generation circuit 18 to the latch circuit 15 based on the command input to the input terminal IN2. As a result, the column address CAe and the data Ae are latched by the latch circuit 15. At this time, the column address CAe and the data Ae are also input to the selector 14, but the / ACTIV output from the command generation circuit 18 to the AND circuit 19 is output.
Since the E signal and the / ROW WITH COLUMN signal are both “H”, the AND circuit 19 sends the control signal C
"H" of L1 is input. Therefore, the selector 14 becomes invalid, and the column address CAe and the data Ae are not output.

Next, in cycles T5 to T8, the column address CAa and data Aa, CAb and Ab, CAc and Ac, CAd and Ad input to the input terminal IN1 are sequentially input to the multiplexer 16. At the same time, "H" of / ROW WITH COLUMN is output from the command generation circuit 18, and the multiplexer 16, the AND circuit 2
0 is input to the first terminal. In the multiplexer 16,
Because "H" of / ROW WITH COLUMN is input, the first
The column address and data input to the terminal are selected and output to the selector 17.

At this time, the first terminal of the AND circuit 20
“H” of / ROW WITH COLUMN is input and AND circuit 20
Of the / WRITE signal from the command generation circuit 18 is input to the second terminal of the. For this reason, “L” of the control signal CL2 that makes the output valid is output from the AND circuit 20 to the selector 17. As a result, the selector 17 outputs the column address CAa and the data Aa, CAb and Ab,
CAc and Ac and CAd and Ad are sequentially output to the column decoding circuit 13. At this time, since the column bank selection signal is "L", BANK # 0 is in a write (Wt) state. With the column bank selection signal, BANK # when "L"
0 is selected, and when "H", BANK # 1 is selected.

Next, in the cycle T9 in which row / column simultaneous issuance is performed, the following is performed. As shown in FIG. 2A, in cycle T9, the row address RBa is input to the input terminal IN1. At the same time, the “L” of the / ACTIVE signal is output from the command generation circuit 18 to the AND circuit 19.
Is output to From the AND circuit 19, “L” of the control signal CL 1 that makes the output valid is output to the selector 14. As a result, the selector 14 sets the row address RBa
Is output to the row decode circuit 12. At this time, since the row bank selection signal is “H”, BANK # 1 is activated (Ac
t).

At the same time, the command generation circuit 18
“L” of / ROW WITH COLUMN is output and input to the multiplexer 16 and the first terminal of the AND circuit 20. Since the multiplexer 16 receives “L” of / ROW WITH COLUMN, the output from the latch circuit 15 input to the second terminal thereof, that is, the column address CAe and the data A
e is selected and output to the selector 17. At this time, the first terminal of the AND circuit 20 is connected to the command generation circuit 1
8, “L” of / ROW WITH COLUMN is input, and the second terminal of the AND circuit 20 receives / WRITE from the command generation circuit 18.
"L" is input. For this reason, “L” of the control signal CL2 that makes the output valid is output from the AND circuit 20 to the selector 17. Thus, the selector 17 converts the column address CAe and the data Ae into the column decode circuit 1
Output to 3. At this time, since the column bank selection signal is "L", BANK # 0 is in a write (Wt) state.

Thereafter, in cycle T10, as in cycles T5 to T8, the column address CAf and data Af are input to the input terminal IN1, and the bank # 0 is in a write (Wt) state. Further, in cycle T11, BANK # 0 is in a precharge (Prec) state.

Next, in cycle T12, similarly to cycle T4, the column address CBc is input to the input terminal IN1.
And data Bc. At the same time, “L” of the / LOAD signal is output from the command generation circuit 18 to the latch circuit 15 based on the command input to the input terminal IN2. As a result, the column address CBc and the data Bc are latched by the latch circuit 15. At this time, the column address CBc and the data Bc are also input to the selector 14.
The / ACTIVE signal output to the circuit 19 and / ROW WITH COLUMN
Since the signals are both “H”, “H” of the control signal CL 1 is input from the AND circuit 19 to the selector 14. Therefore, the selector 14 becomes invalid, and the column address CBc and the data Bc are not output.

Next, in cycles T13 and T14, the column address CBa input to the input terminal IN1 is set.
And the data Ba, CBb and Bb are supplied to the multiplexer 16.
Are sequentially input. At the same time, the command generation circuit 1
8, “H” of / ROW WITH COLUMN is output and input to the multiplexer 16 and the first terminal of the AND circuit 20.
Since “H” of / ROW WITH COLUMN is input to the multiplexer 16, the column address and data input to the first terminal are selected and output to the selector 17.

At this time, the "H" of / ROW WITH COLUMN is input from the command generation circuit 18 to the first terminal of the AND circuit 20, and the / WRITE signal of the command generation circuit 18 is input to the second terminal of the AND circuit 20. “L” is input. For this reason, “L” of the control signal CL2 that makes the output valid is output from the AND circuit 20 to the selector 17. As a result, the selector 17 sequentially outputs the column address CBa and the data Ba, CBb and Bb to the column decode circuit 13. At this time, since the column bank selection signal is "H", BANK # 1 is in a write (Wt) state.

Next, the cycle T15 in which row / column simultaneous issuance is performed is as follows. As shown in FIG. 2A, in cycle T15, the row address RAb is input to the input terminal IN1. At the same time, “L” of the / ACTIVE signal is output from the command generation circuit 18 to the AND circuit 19. From the AND circuit 19, the selector 1
4 outputs "L" of the control signal CL1 for validating the output. As a result, the selector 14 sets the row address RA
b is output to the row decode circuit 12. At this time, since the row bank selection signal is "L", BANK # 0 is activated (Act).

At the same time, the command generation circuit 18
“L” of / ROW WITH COLUMN is output and input to the multiplexer 16 and the first terminal of the AND circuit 20. Since the multiplexer 16 receives “L” of / ROW WITH COLUMN, the output from the latch circuit 15 input to the second terminal thereof, that is, the column address CBc and the data B
c is selected and output to the selector 17. At this time, the first terminal of the AND circuit 20 is connected to the command generation circuit 1
8, “L” of / ROW WITH COLUMN is input, and the second terminal of the AND circuit 20 receives / WRITE from the command generation circuit 18.
"L" is input. Therefore, the control signal “L” of enabling the output is output from the AND circuit 20 to the selector 17.
Is output. As a result, the selector 17 outputs the column address CBc and the data Bc to the column decoding circuit 13. At this time, since the column bank selection signal is "H", BANK # 1 is in a write (Wt) state.

Thereafter, in cycles T16 and T17, as in cycles T13 and T14, the input terminal IN1
, A column address CBd and data Bd,... Are input, and BANK # 1 enters a write (Wt) state.

By the above-described operation, even in the semiconductor memory device having only a small number of pins as shown in FIG. 1, the operation of the simultaneous row / column access function for simultaneously issuing a row address / column address and data can be realized. .

As described above, according to the first embodiment, necessary column addresses and data are previously latched in the previous operation cycle, and latched simultaneously with the row address input in the current operation cycle. By issuing the column address and data, the operation of the simultaneous row / column access function can be realized with a small number of pins as in the case of address multiplexing.

[Second Embodiment] Next, a semiconductor memory device according to a second embodiment of the present invention will be described.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention. In the first embodiment, the column address and the data are latched in advance and are simultaneously issued. In the second embodiment, the row address is latched in advance, and then is issued simultaneously.

This semiconductor memory device has a memory cell array 11 in which memory cells MC are arranged in a matrix of rows and columns, a row decode circuit 12 for selecting a word line WL from an input row address, and an input column. A column decode circuit 13 for selecting a bit line BL from an address;
A latch circuit 21 for latching a row address input to the input terminal IN1, a multiplexer for receiving the row address input to the input terminal IN1 and the row address output from the latch circuit 21, and selecting and outputting one of the row address And a selector 14 for selecting whether or not to output the signal received from the multiplexer 22 to the row decode circuit 12.

Further, the semiconductor memory device has a selector 17 for selecting whether or not to output the column address and data inputted to the input terminal IN 1 to the column decoding circuit 13.
And

Further, the semiconductor memory device has an input terminal IN
2, a command generation circuit 18 for generating various commands, and an AND operation of a simultaneously issued command and a row command issued when a row operation and a column operation are simultaneously started. An AND circuit 19 and an AND circuit 20 that performs an AND operation using the simultaneous command and the column command are provided.

The memory cell array 11 has a word line W
A regular memory cell MC of a predetermined capacity is arranged at the intersection of L and the bit line BL in a matrix of rows and columns. The memory cell array 11 is assigned a two-dimensional address space represented by a row address of Nra bits and a column address of Nca bits. The number of bits of the row address and the column address is determined according to the storage capacity of the memory cell array 11. Input terminal IN
1 is input with a row address of Nra bits, a column address of Nca bits and data of Nd bits. The input terminal IN1 has Nra bits or (Nca + N
d) Of the bits, it has a pin number capable of transmitting the larger bit number (Nmx).

The selector 17 selects whether or not to output a column address and data to the column decode circuit 13 and the data line DL, respectively, in response to the control signal CL1 from the AND circuit 20. The column decode circuit 13 decodes a column address and selects a column of the memory cell array 11, and selects a bit line BL based on the column address.

An Ncm-bit command is input to the input terminal IN2. The command generation circuit 18 decodes an Ncm-bit coded command, and causes a latch circuit 21 to latch a row address and a / LOAD signal and a / COL signal to execute row / column simultaneous access.
UMN WITH ROW signal, / A for activating word line WL
It generates a CTIVE signal (row-related command) and a signal (column-related command) for executing a read or write operation. Here, only the / WRITE signal will be described using a write operation as an example. The latch circuit 21 responds to / LOAD
Sets whether to latch the input row address.

In response to / COLUMN WITH ROW, the multiplexer 22 having the first terminal and the second terminal inputs the signal input to the first terminal and the latch circuit 2 input to the second terminal.
One of the outputs (row addresses) is selected and output to the selector 14. In other words, the multiplexer 22
Is a case where a row address input from the outside is processed as a normal operation (an operation not simultaneously issued).
The output is switched between the case where it is processed as an operation of simultaneously issuing a previously latched row address according to 1.

The selector 14 selects whether or not to output the row address output from the multiplexer 22 to the row decode circuit 12 in response to the control signal CL1 from the AND circuit 19. The row decode circuit 12 is for decoding a row address and selecting a row of the memory cell array 11, and selects a word line WL based on the row address.

The AND circuit 19 performs an AND operation on / COLUMN WITH ROW output from the command generation circuit 18 and / ACTIVE, and outputs a control signal CL1 based on the operation result. The AND circuit 20 includes a command generation circuit 18
AND operation is performed on / COLUMN WITHROW and / WRITE output from, and a control signal CL2 is output from the operation result.

Next, an operation example of the simultaneous row / column access function of the semiconductor memory device of the second embodiment will be described.

As in the first embodiment, the row / column simultaneous access function at the time of bank interleaving is a function of executing a column operation in one bank and executing a row operation in another bank at the same time. . Therefore, it is necessary to simultaneously issue a column address and data for a column operation and a row address for a row operation. The operation of such a row / column simultaneous access function is as follows, taking a write page operation as an example.

FIGS. 4A and 4B are timing charts showing the operation of the simultaneous row / column access function.
As in the first embodiment, FIG.
BANK # 0 and BANK # 1 indicate two banks included in the semiconductor memory device. / ACTIVE, / PRECHAGE, / WRITE, / LOAD
Based on the command CM input to the input terminal IN2,
The command output from the command generation circuit 18 is shown.
/ Represents a bar, indicating that it is an inverted signal. The row bank selection signal is supplied by some bits of the row address input to the input terminal IN1. The column bank selection signal is supplied by a column address and some bits of data input to the input terminal IN1. The row address, column address, and data in FIG. 4A indicate signals input to the input terminal IN1.

The row address shown in FIG. 4B indicates a signal which is latched by the latch circuit 21 and further selected and output by the multiplexer 22. / COLUMN WITH ROW
Is based on a command input to the input terminal IN2,
The command output from the command generation circuit 18 is shown.

The description of the parts operating in the same manner as in the first embodiment will be omitted, and only the operations of the different parts will be described below. According to the timing charts shown in FIGS. 4A and 4B, there are two cycles T9 and T15 in which the row operation and the column operation are simultaneously executed in different banks. In cycle T9, the operation of writing (Wt) is performed by BANK # 0, and the operation of activation (Act) is performed by BANK # 1. At this time, the row (row) side address is RBa
And the address on the column side is selected by CAe, and the write data is Ae. In cycle T15, an activation (Act) operation is performed in BANK # 0, and a write (Wt) operation is performed in BANK # 1. At this time, the row (row) side address is selected by RAb, and the column (column) is selected.
Side address is selected by CBc, write data is Bc
It is.

As shown in FIG. 4A, the / LOAD signal is generated from the command generation circuit 18 in cycle T4, and the row address RBa is latched in the latch circuit 21. Then, in a cycle T9, the command generation circuit 18 generates a / COLUMN WITH ROW signal for simultaneously issuing a row address / column address and data. This allows
At the same time that the column address CAe and the data Ae input to the input terminal IN1 are issued, the latch circuit 21
Issues the latched row address RBa.

In the cycle T12, the command generating circuit 18 generates a / LOAD signal, and the latch circuit 21 latches the row address RAb. And the cycle T
At 15, / COLUMN WI for simultaneously issuing a row address / column address and data from the command generation circuit 18.
Generate TH ROW signal. Thereby, the input terminal IN1
At the same time as the input column address CBc and data Bc, and at the same time, the latch circuit 21 issues the row address RAb latched in advance.

By the above-described operation, a row address / column address and data are simultaneously issued even in a semiconductor memory device having only a small number of pins as shown in FIG. 3 and configured to latch a row address. The operation of the row / column simultaneous access function can be realized.

As described above, according to the second embodiment, the necessary row address is latched in the previous operation cycle, and is latched simultaneously with the column address and data input in the current operation cycle. By issuing the row address, the operation of the simultaneous row / column access function can be realized with a small number of pins as in the case of address multiplexing.

[Third Embodiment] Next, a semiconductor memory device according to a third embodiment of the present invention will be described.

FIG. 5 is a circuit diagram showing a configuration of the semiconductor memory device according to the third embodiment of the present invention. The semiconductor memory device according to the third embodiment has a configuration aimed at testing the operation of the simultaneous row / column access function.

This semiconductor memory device has a memory cell array 11 in which memory cells MC are arranged in a matrix of rows and columns, a row decode circuit 12 for selecting a word line WL from an input row address, and an input column. A column decode circuit 13 for selecting a bit line BL from an address;
Row test address (test path) input to input terminal IN1 and normal row address (normal path 31a)
And a selector 14 which receives and outputs a row address output from the multiplexer 31 and selects whether or not to output the row address to the row decode circuit 12. are doing.

Further, the semiconductor memory device has a latch circuit 15 for latching a column test address and test data input to an input terminal IN1, a column test address and test data input to an input terminal IN1 and the latch circuit 15. And a multiplexer 16 for receiving the column test address and the test data output from the multiplexer 16 and selecting and outputting one of them.
A multiplexer 32 which receives the column test address (test path) and the normal column address (normal path 32 a) output from, and selects and outputs one of them.
And test data (test path) output from the multiplexer 16 and normal data (normal path 33).
a) to select and output one of them, whether or not to output the column address received from the multiplexer 32 to the column decode circuit 13, and to output the data received from the multiplexer 33 to the data line DL. Selector 1 to select whether to output to
7 are provided.

Further, the semiconductor memory device has an input terminal IN
2, a command generation circuit 18 for generating various commands, and an AND operation of a simultaneously issued command and a row command issued when a row operation and a column operation are simultaneously started. An AND circuit 19 and an AND circuit 20 that performs an AND operation using the simultaneous command and the column command are provided.

The memory cell array 11 has a word line W
A regular memory cell MC of a predetermined capacity is arranged at the intersection of L and the bit line BL in a matrix of rows and columns. The memory cell array 11 is assigned a two-dimensional address space represented by a row address of Nra bits and a column address of Nca bits. The number of bits of the row address and the column address is determined according to the storage capacity of the memory cell array 11. Input terminal IN
1 is an Nra bit row test address or Nca
A bit column test address and Nd bit test data are input. The input terminal IN1 has Nra bits,
Alternatively, it has a pin number capable of transmitting the larger bit number (Nmx) of Nca + Nd bits.

The multiplexer 31 having the first terminal and the second terminal responds to the test mode control signal / TM (TM bar). One of the input (row address) of the normal path 31 a that is input is selected and output to the selector 14. The selector 14 selects whether to output a row test address or a row address output from the multiplexer 31 to the row decode circuit 12 in response to the control signal CL1 from the AND circuit 19. The row decode circuit 12 decodes a row test address or a row address to select a row of the memory cell array 11, and selects a word line WL based on the row test address or the row address.

A command of Ncm bits is input to the input terminal IN2. The command generation circuit 18 decodes the coded command of Ncm bits, and causes the latch circuit 15 to latch the column test address and the test data by using the / LOAD signal, and to execute the row / column simultaneous access. A ROW WITH COLUMN signal, a / ACTIVE signal for activating the word line WL (row command), and a signal (column command) for executing a read or write operation are generated. Here, only the / WRITE signal will be described using a write operation as an example. The latch circuit 15 sets whether to latch the input column test address and test data in response to / LOAD.

In response to / ROW WITH COLUMN, the multiplexer 16 having the first terminal and the second terminal supplies the column test address and test data input to the first terminal and the latch circuit 15 input to the second terminal. (The column test address and the test data) are output to the multiplexers 32 and 33. In other words, the multiplexer 16 simultaneously issues the column test address and test data latched by the latch circuit 15 when processing the column test address and test data input from the outside as a normal operation (operation not simultaneously issuing). The output is switched between when processing is performed as an operation.

The multiplexer 32 having the first terminal and the second terminal responds to the test mode control signal / TM (TM bar), and outputs the column test address inputted to the first terminal and the second terminal to the second terminal. Select one of the input (column address) of the input normal path 32a and select the selector 1
7 is output. The multiplexer 33 having the first terminal and the second terminal outputs the control signal / TM (TM bar) for the test mode.
In response to this, one of the test data input to the first terminal and the output (data) of the normal path 33a input to the second terminal is selected and output to the selector 17.

Selector 17 responds to control signal CL2 from AND circuit 20 to select whether to output signals output from multiplexers 32 and 33 to column decode circuit 13 and data line DL, respectively. . The column decode circuit 13 decodes a column test address or a column address to select a column of the memory cell array 11, and selects a bit line BL based on the column test address or the column address.

The AND circuit 19 performs an AND operation on / ROW WITH COLUMN and / ACTIVE output from the command generation circuit 18, and outputs a control signal CL1 based on the operation result. The AND circuit 20 includes a command generation circuit 18
AND operation is performed with / ROW WITH COLUMN and / WRITE output from the controller, and a control signal CL2 is output from the operation result.

Next, an operation example of the simultaneous row / column access function of the semiconductor memory device of the third embodiment will be described.

As in the first embodiment, the row / column simultaneous access function at the time of bank interleaving is a function of executing a column operation in one bank and executing a row operation in another bank at the same time. . Therefore, it is necessary to simultaneously issue a column address and data for a column operation and a row address for a row operation. The operation of such a row / column simultaneous access function is as follows, taking a write page operation as an example.

FIGS. 6A and 6B are timing charts showing the operation of the simultaneous row / column access function.
As in the first embodiment, FIG.
BANK # 0 and BANK # 1 indicate two banks included in the semiconductor memory device. / TM, / ACTIVE, / PRECHAGE, / WRITE, / LOAD
Indicates a command output from the command generation circuit 18 based on the command CM input to the input terminal IN2. / Represents a bar, indicating that it is an inverted signal. The row bank selection signal is supplied by some bits of the row address input to the input terminal IN1. The column bank selection signal is supplied by a column address and some bits of data input to the input terminal IN1. FIG.
The row test address, column test address, and test data in (a) indicate signals input to the input terminal IN1.

The column test address in FIG. 6B indicates a signal which is latched by the latch circuit 15 and further selected and output by the multiplexer 16. / ROW WITH
COLUMN indicates a command output from the command generation circuit 18 based on a command input to the input terminal IN2.

According to the timing charts shown in FIGS. 6A and 6B, there are two cycles T9 and T15 in which the row operation and the column operation are simultaneously executed in different banks. In cycle T9, the operation of writing (Wt) is performed by BANK # 0, and the operation of activation (Act) is performed by BANK # 1. At this time, the row (row) side address is selected by RBa, the column (column) side address is selected by CAe, and the write data is Ae. In cycle T15, BA
Activation (Act) operation with NK # 0, writing with BANK # 1 (W
The operation of t) is performed. At this time, the row (row) side address is selected by RAb, the column (column) side address is selected by CBc, and the write data is Bc.

Description of parts operating in the same manner as in the first embodiment will be omitted, and only different parts will be described below.

As shown in FIG. 6A, in cycle T1, the test mode control signal / TM becomes "L", and the operation enters the test mode state. In the cycle T4, the command generation circuit 18 generates the / LOAD signal, and the latch circuit 15
, The column test address CAe and the test data Ae are latched. Then, in the cycle T9, the command generation circuit 18 issues a / ROW WITH for simultaneously issuing a row test address / column test address and test data.
Generate a COLUMN signal. Thereby, the input terminal IN1
At the same time as the input row test address RBa, as shown in FIG.
Issue the latched column test address CAe and test data Ae.

In the cycle T12, the command generating circuit 18 generates the / LOAD signal, and the latch circuit 15 latches the column test address CBc and the test data Bc. Then, in the cycle T15, the command generation circuit 18 issues a / ROW WITH COLU for simultaneously issuing a row test address / column test address and test data.
Generate MN signal. As a result, the row test address RAb input to the input terminal IN1 is issued, and at the same time, as shown in FIG. 6B, the column test address CBc and the test data Bc latched in advance by the latch circuit 15 are issued.

With the above-described configuration, the operation of the simultaneous row / column access function for simultaneously issuing a row address / column address and data can be realized even in a memory-embedded logic LSI that requires a reduction in the number of test pins.

As described above, according to the third embodiment, necessary column addresses and data are latched in advance in the previous operation cycle, and latched simultaneously with the row address input in the current operation cycle. By issuing the column address and data, the operation of the simultaneous row / column access function can be realized with a small number of pins as in the case of address multiplexing.

[Fourth Embodiment] Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described.

FIG. 7 is a circuit diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention. The semiconductor memory device according to the fourth embodiment has a configuration aimed at testing the operation of the simultaneous row / column access function, similarly to the third embodiment.

This semiconductor memory device has a memory cell array 11 in which memory cells MC are arranged in a matrix of rows and columns, a row decode circuit 12 for selecting a word line WL from an input row address, and an input column. A column decode circuit 13 for selecting a bit line BL from an address;
A latch circuit 21 for latching a row test address input to the input terminal IN1, a row test address input to the input terminal IN1 and a row test address output from the latch circuit 21 are received, and one of them is selected. A multiplexer 22 for outputting, a row test address and a (test path) and a normal row address (normal path 31 a) output from the multiplexer 22, and a multiplexer 31 for selecting and outputting one of the row test address and the multiplexer 31. And a selector 14 for receiving whether the row address is output from the row decoder 12 and selecting whether to output the row address to the row decode circuit 12.

Further, the semiconductor memory device receives a column test address (test path) and a normal column address (normal path 32a) input to the input terminal IN1, and selects and outputs one of them. , Test data (test path) input to the input terminal IN1 and normal data (normal path 33a)
And a multiplexer 33 that selects and outputs one of them, and whether or not to output the column address received from the multiplexer 32 to the column decoding circuit 13.
And a selector 17 for selecting whether to output the data received from the multiplexer 33 to the data line DL.

Further, the semiconductor memory device has an input terminal IN
2, a command generation circuit 18 for generating various commands, and an AND operation of a simultaneously issued command and a row command issued when a row operation and a column operation are simultaneously started. An AND circuit 19 and an AND circuit 20 that performs an AND operation using the simultaneous command and the column command are provided.

The memory cell array 11 has a word line W
A regular memory cell MC of a predetermined capacity is arranged at the intersection of L and the bit line BL in a matrix of rows and columns. The memory cell array 11 is assigned a two-dimensional address space represented by a row address of Nra bits and a column address of Nca bits. The number of bits of the row address and the column address is determined according to the storage capacity of the memory cell array 11. Input terminal IN
1 is an Nra bit row test address or Nca
A bit column test address and Nd bit test data are input. The input terminal IN1 has the number of pins capable of transmitting the larger number (Nmx) of Nra bits or Nca + Nd bits.

The multiplexer 32 having the first terminal and the second terminal responds to the test mode control signal / TM (TM bar), and outputs the column test address input to the first terminal and the second terminal to the second terminal. Select one of the input (column address) of the input normal path 32a and select the selector 1
7 is output. The multiplexer 33 having the first terminal and the second terminal outputs the control signal / TM (TM bar) for the test mode.
In response to this, one of the test data input to the first terminal and the output (data) of the normal path 33a input to the second terminal is selected and output to the selector 17.

In response to the control signal CL2 from the AND circuit 20, the selector 17 selects whether to output the signals output from the multiplexers 32 and 33 to the column decode circuit 13 and the data lines DL, respectively. . The column decode circuit 13 decodes a column test address or a column address to select a column of the memory cell array 11, and selects a bit line BL based on the column test address or the column address.

An Ncm-bit command is input to the input terminal IN2. The command generation circuit 18 decodes the Ncm-bit coded command and causes the latch circuit 21 to latch a row test address.
D signal, / COLUMN WITH ROW signal for executing simultaneous row / column access, / ACTIVE signal (row command) for activating word line WL, and signal (column for executing read / write operation) Command). Here, the write operation is taken as an example and / WRITE
Describe only the signal. The latch circuit 21 sets whether to latch the input row test address in response to / LOAD.

In response to / COLUMN WITH ROW, the multiplexer 22 having the first terminal and the second terminal outputs the row test address input to the first terminal and the output of the latch circuit 21 input to the second terminal. (Row test address) and outputs it to the multiplexer 31. In other words, the multiplexer 22 operates the row test address input from the outside in the normal operation (operation not simultaneously issuing).
The output is switched between the case where the processing is performed as the operation and the case where the processing is performed as the operation of simultaneously issuing the row test address previously latched by the latch circuit 21.

The multiplexer 31 having the first terminal and the second terminal responds to the control signal / TM (TM bar) for the test mode, and outputs the row test address input to the first terminal and the input to the second terminal. The selected output (row address) of the normal path 31a is selected and output to the selector 14. The selector 14 selects whether to output a row test address or a row address output from the multiplexer 31 to the row decode circuit 12 in response to the control signal CL1 from the AND circuit 19. The row decode circuit 12 decodes a row test address or a row address to select a row of the memory cell array 11, and selects a word line WL based on the row test address or the row address.

The AND circuit 19 performs an AND operation on / COLUMN WITH ROW and / ACTIVE output from the command generation circuit 18, and outputs a control signal CL1 based on the operation result. The AND circuit 20 includes a command generation circuit 18
AND operation is performed on / COLUMN WITHROW and / WRITE output from, and a control signal CL2 is output from the operation result.

Next, an operation example of the simultaneous row / column access function of the semiconductor memory device of the fourth embodiment will be described.

As in the second embodiment, the row / column simultaneous access function at the time of bank interleaving is a function of executing a column operation in one bank and executing a row operation in another bank at the same time. . Therefore, it is necessary to simultaneously issue a column address and data for a column operation and a row address for a row operation. The operation of such a row / column simultaneous access function is as follows, taking a write page operation as an example.

FIGS. 8A and 8B are timing charts showing the operation of the simultaneous row / column access function.
As in the second embodiment, FIG.
BANK # 0 and BANK # 1 indicate two banks included in the semiconductor memory device. / TM, / ACTIVE, / PRECHAGE, / WRITE, / LOAD
Indicates a command output from the command generation circuit 18 based on the command CM input to the input terminal IN2. / Represents a bar, indicating that it is an inverted signal. The row bank selection signal is supplied by some bits of the row address input to the input terminal IN1. The column bank selection signal is supplied by a column address and some bits of data input to the input terminal IN1. FIG.
The row test address, column test address, and test data in (a) indicate signals input to the input terminal IN1.

The row test address in FIG. 8B indicates a signal which is latched by the latch circuit 21 and further selected and output by the multiplexer 22. / COLUMN WI
TH ROW indicates a command output from the command generation circuit 18 based on a command input to the input terminal IN2.

According to the timing charts shown in FIGS. 8A and 8B, there are two cycles T9 and T15 in which the row-related operation and the column-related operation are simultaneously executed in different banks. In cycle T9, the operation of writing (Wt) is performed by BANK # 0, and the operation of activation (Act) is performed by BANK # 1. At this time, the row (row) side address is selected by RBa, the column (column) side address is selected by CAe, and the write data is Ae. In cycle T15, BA
Activation (Act) operation with NK # 0, writing with BANK # 1 (W
The operation of t) is performed. At this time, the row (row) side address is selected by RAb, the column (column) side address is selected by CBc, and the write data is Bc.

Description of parts operating in the same manner as in the second embodiment will be omitted, and only different parts will be described below.

As shown in FIG. 8A, in cycle T1, the test mode control signal / TM becomes "L", and the operation enters the test mode state. In a cycle T4, a / LOAD signal “L” is generated from the command generation circuit 18 and the row test address RBa is latched in the latch circuit 21.
Then, in a cycle T9, the command generation circuit 18 generates a / COLUMN WITH ROW signal for simultaneously issuing a row test address / column test address and test data. As a result, the column test address CAe and the test data Ae input to the input terminal IN1 are issued, and at the same time, the row test address RBa latched by the latch circuit 21 is issued, as shown in FIG. 8B.

In the cycle T12, a / LOAD signal is generated from the command generation circuit 18, and the row test address RAb is latched in the latch circuit 21. Then, in a cycle T15, the command generation circuit 18 generates a / COLUMN WITH ROW signal for simultaneously issuing a row test address / column test address and test data. As a result, the column test address CBc and the test data Bc input to the input terminal IN1 are issued, and at the same time, the row test address RAb latched by the latch circuit 21 is issued as shown in FIG. 8B.

With the above-described configuration, the operation of the simultaneous row / column access function for simultaneously issuing a row address / column address and data can be realized even in a memory-embedded logic LSI that requires a reduction in the number of test pins.

As described above, according to the fourth embodiment, the necessary row address is latched in the previous operation cycle in advance, and is latched simultaneously with the column address and data input in the current operation cycle. By issuing the row address, the operation of the simultaneous row / column access function can be realized with a small number of pins as in the case of address multiplexing.

[0122]

As described above, according to the present invention, necessary addresses or data are latched in the previous operation cycle in advance, and the latched address or data is used simultaneously with the address or data used in the current operation cycle. By issuing this, it is possible to provide a semiconductor memory device and a memory-embedded logic LSI that can realize the operation of the simultaneous row / column access function with a small number of pins as in the case of address multiplexing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of a simultaneous row / column access function in the semiconductor memory device.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of a simultaneous row / column access function in the semiconductor memory device.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing an operation of a simultaneous row / column access function in the semiconductor memory device.

FIG. 7 is a circuit diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart showing an operation of a simultaneous row / column access function in the semiconductor memory device.

FIG. 9 is a block diagram showing a first configuration example of a conventional semiconductor memory device.

FIG. 10 is a block diagram showing a second configuration example of a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Memory cell array 12 ... Row decode circuit 13 ... Column decode circuit 14 ... Selector 15 ... Latch circuit 16 ... Multiplexer 17 ... Selector 18 ... Command generation circuit 19 ... AND circuit 20 ... AND circuit 21 ... Latch circuit 22 ... Multiplexer 31 ... Multiplexer 31a: Normal path 32: Multiplexer 32a: Normal path 33: Multiplexer 33a: Normal path BL: Bit line DL: Data line IN1: Input terminal IN2: Input terminal MC: Memory cell WL: Word line

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Katsuhiko Sato 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in Toshiba Microelectronics Center Co., Ltd. 5F038 BE02 DF05 DF11 DT02 DT05 DT07 DT15 EZ20

Claims (8)

[Claims] A memory cell array in which memory cells are arranged in a matrix; an external terminal to which an address signal is input from the outside; and a row decode circuit for decoding the address signal and selecting a row of the memory cell array. A column decode circuit for decoding the address signal and selecting a column of the memory cell array; and a column decode circuit provided between the external terminal and the row decode circuit.
A first selector for selecting whether to output the address signal to the row decode circuit, and a first selector provided between the external terminal and the column decode circuit;
A second selector for selecting whether or not to output the address signal to the column decoding circuit; a latch circuit for storing an address corresponding to the address signal input to the external terminal; A first multiplexer for selecting one of the address signal and the address signal stored in the latch circuit and outputting the selected signal to one of the first selector and the second selector; When a command for simultaneously inputting to the row decode circuit and the column decode circuit is externally input, the multiplexer selects and outputs the signal stored in the latch circuit, and the first selector and the second And a control circuit for setting the second selector to the output state. 2. A memory cell array in which memory cells are arranged in a matrix, an external terminal to which an address signal is inputted from the outside, and a control circuit for generating a plurality of control signals based on a command inputted from the outside. A first selector for selecting whether to output the address signal input to the external terminal in response to a first control signal generated by the control circuit; and A row decode circuit for decoding the address signal to select a row of the memory cell array; and responding to a second control signal generated by the control circuit, in response to the address signal input to the external terminal. A latch circuit for storing an address; first and second input terminals;
A third circuit in which the control circuit generates one of the address signal input to the input terminal or the address signal input to the second input terminal from the latch circuit;
A first multiplexer that selects and outputs the address signal in response to a control signal; and outputs the address signal output from the first multiplexer to the column decode circuit in response to a fourth control signal generated by the control circuit. Second to choose whether to do
And a column decode circuit for decoding the address signal output from the second selector to select a column of the memory cell array, wherein the row decode circuit and the column decode the different address signals. When a command for simultaneously inputting to the circuit is input to the control circuit, the control circuit causes the first multiplexer to select and output the address signal stored in the latch circuit. And the first control signal and the fourth control signal for setting the first selector and the second selector to the output state.
A semiconductor memory device which outputs a control signal. 3. A memory cell array in which memory cells are arranged in a matrix, an external terminal to which an address signal and data are inputted from outside, and a row for decoding the address signal and selecting a row of the memory cell array. A decode circuit, a column decode circuit for decoding the address signal to select a column of the memory cell array, and a memory cell at an intersection of a row and a column selected by the row decode circuit and the column decode circuit. A data line for writing the data input together with the address signal; and a data line provided between the external terminal and the row decode circuit;
A first selector for selecting whether to output the address signal to the row decode circuit, and a first selector provided between the external terminal and the column decode circuit;
A second selector for selecting whether to output the address signal to the column decode circuit and the data input together with the address signal to the data line, and a second selector for selecting whether to output the external terminal and the second selector. Provided in between,
A latch circuit that stores the address signal and data input to the external terminal; and one of the address signal and data input to the external terminal or the address signal and data stored in the latch circuit. A multiplexer for selecting and outputting the selected address to the second selector; and a command for simultaneously inputting the address signal to the row decode circuit and an address signal and data different from the address signal to the column decode circuit are externally input. A control circuit that sets the first selector to an output state, causes the multiplexer to select and output a signal stored in the latch circuit, and sets a second selector to an output state. A semiconductor memory device. 4. A memory cell array in which memory cells are arranged in a matrix, an external terminal to which an address signal and data are inputted from outside, and a row for decoding the address signal and selecting a row of the memory cell array A decode circuit, a column decode circuit for decoding the address signal to select a column of the memory cell array, and a memory cell at an intersection of a row and a column selected by the row decode circuit and the column decode circuit. A data line for writing the data input together with the address signal; and a data line provided between the external terminal and the row decode circuit;
A first selector for selecting whether to output the address signal to the row decode circuit, and a first selector provided between the external terminal and the column decode circuit;
A second selector for selecting whether to output the address signal to the column decode circuit and the data input together with the address signal to the data line, and a second selector for selecting whether or not the external terminal is connected to the first selector. Provided in between,
A latch circuit for storing an address corresponding to the address signal input to the external terminal; and selecting one of the address signal input to the external terminal or the address signal stored in the latch circuit. A multiplexer for outputting to the first selector, a command for simultaneously inputting the address signal to the row decode circuit, and an address signal and data different from the address signal to the column decode circuit, and A control circuit that causes the multiplexer to select and output a signal stored in the latch circuit, and sets a first selector to an output state and sets a second selector to an output state. A semiconductor memory device characterized by the following. 5. The method according to claim 1, wherein the address signal input to the external terminal is a test address signal used in a test operation, and a command input from the outside is a test command used in a test operation. A second selector having first and second input terminals with the first selector;
A third multiplexer having first and second input terminals between the first multiplexer and the second selector, wherein the second multiplexer indicates that a test operation is being performed. In response to the control signal, one of the test address signal input to the first input terminal and the normally used address signal input to the second input terminal is selected and output to the first selector. The third multiplexer is configured to receive the test address signal output from the first multiplexer input to a first input terminal in response to the control signal, or a commonly used address signal input to a second input terminal. 3. The semiconductor memory device according to claim 1, wherein one of the two is selected and output to the second selector. 6. The address signal input to the external terminal is a test address signal used in a test.
The command input from the outside is a test command used at the time of a test, and a second multiplexer having first and second input terminals between the external terminal and the second selector is connected to the first multiplexer. And a third multiplexer having first and second input terminals between the second multiplexer and the first selector, wherein the second multiplexer responds to a control signal indicating that a test operation is being performed. One of the test address signal input to the first input terminal and the commonly used address signal input to the second input terminal is selected and output to the second selector, and the third multiplexer is The test address signal output from the first multiplexer input to a first input terminal in response to a control signal, or input to a second input terminal The semiconductor memory device according to claim 1 or 2, characterized in that output to the first selector selects either conventional There are address signals. 7. A memory cell array in which memory cells are arranged in a matrix, an external terminal to which an address signal is inputted from outside, and a row decode circuit for decoding the address signal and selecting a row of the memory cell array. A column decode circuit for decoding the address signal and selecting a column of the memory cell array; and a column decode circuit provided between the external terminal and the row decode circuit.
A first selector for selecting whether to output the address signal to the row decode circuit, and a first selector provided between the external terminal and the column decode circuit;
A second selector for selecting whether or not to output the address signal to the column decoding circuit; a latch circuit for storing an address corresponding to the address signal input to the external terminal; A first multiplexer for selecting one of the address signal and the address signal stored in the latch circuit and outputting the selected signal to one of the first selector and the second selector; When a command for simultaneously inputting to the row decode circuit and the column decode circuit is externally input, the multiplexer selects and outputs the signal stored in the latch circuit, and the first selector and the second And a control circuit for setting the second selector to the output state.
I. 8. The address signal input to the external terminal is a test address signal used at the time of a test operation, and the command input from the outside is a test command used at the time of a test operation. A second selector having first and second input terminals with the first selector;
A third multiplexer having first and second input terminals between the first multiplexer and the second selector, wherein the second multiplexer indicates that a test operation is being performed. In response to the control signal, one of the test address signal input to the first input terminal and the normally used address signal input to the second input terminal is selected and output to the first selector. The third multiplexer is configured to receive the test address signal output from the first multiplexer input to a first input terminal in response to the control signal, or a commonly used address signal input to a second input terminal. 8. The memory-embedded logic L according to claim 7, wherein one of the logics is selected and output to the second selector.
SI.