JP3031581B2 - Random access memory and information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access memory configured as an integrated circuit, and more particularly to a serial access memory.
Bits can be preset / reset simultaneously
Random access memory, plus any
Any bit in address can be preset / reset at high speed
The present invention relates to an enabled random access memory, and further relates to an information processing apparatus including the random access memory as a main storage memory or a buffer memory.

[0002]

2. Description of the Related Art Conventionally, random access memories in general have been described in "Logic Design by LSI" (by S. Okukawa,
As described on pages 140 to 144 of Kyoritsu Shuppan, 1987, for a random access memory, a write / read mode is designated by a write enable signal and an access address is input. , Write data to the access address,
The access address or La Defense over data are read out.

[0003]

By the way, various kinds of processing are generally performed in an information processing apparatus. However, when a random access memory is used as a main memory of a computer, an arbitrary connection is required depending on the type of processing. It has become one process for presetting / reset a specific bit data of the data in the preset / reset or or specific address, with all addresses in the space over the connection address space is frequently performed. For example, image processing is often performed as such processing is frequently performed. However, it is desirable that such processing be performed as quickly as possible in terms of processing performance. However, in the conventional random access memory, data of each address or specific bit data is usually updated only in address units by program processing. That is, in order to preset / reset the data at a certain address, the data is updated at the address for the first time by writing all "1" / "0" as the write data to the address. It is. Therefore, when it is necessary to preset / reset all the data in any continuous address space <br/> is, in the past, while updating the write address, write to the write address Access was required. There is no particular problem when the number of write addresses is small, but as the number of addresses increases, the time required for the write process increases. For example, assuming a random access memory of addresses 0 to 1023 as a memory address space, and when resetting data at all addresses, assuming that a write cycle per address is 500 ns, 512 μs (= 1024 × 500 n)
s) It takes much time. For this reason, when real-time processing is required, it is not possible to cope with it.

[0004] A first object of the present invention is to update all data in an arbitrary continuous address space to all "1" / "0" promptly without using a normal write process. The purpose is to provide a random access memory that can be used. A second object of the present invention, according to the switching request from the outside, the updating of the specific bit data in any address
As also acceptable, in providing random access memory update to all the data of all "1" / "0" at arbitrary continuous address space it was allowed to occur rapidly without by conventional write process. A third object of the present invention, <br/> the least, all data in arbitrary successive address spaces all "1"
An object of the present invention is to provide an information processing apparatus that enables updating to / 0 to be performed quickly without performing a normal writing process.

[0005]

Means for Solving the Problems The upper SL first object, a random access memory integrated circuit structure, the memory cell each preset friendly, as the reset accepted, the start address and to be preset / reset from the outside This is achieved by incorporating a control circuit for simultaneously generating a preset / reset signal for all memory cells from the start address to the end address based on the end address. Further, the second object is that, in a random access memory having an integrated circuit configuration, each memory cell can be preset and resettable, and based on a bit address at an arbitrary address to be preset / reset from the outside, A first control circuit for generating a preset / reset signal for a memory cell corresponding to a bit address by an address; and a start address and an end address based on a start address and an end address to be preset / reset from outside. And a second control circuit for simultaneously generating a preset / reset signal for all of the memory cells up to and including a switching mode signal from an external device. This is achieved by selectively operating according to Furthermore , on
The third object is to provide a random access memory having an integrated circuit structure with at least a start address to be preset / reset from the outside and an end address based on at least all memory cells from the start address to the end address. , Simultaneously generate preset / reset signals
After having allowed built that control circuit is achieved by allowed to including the same as a main storage memory or a buffer memory.

[0006]

The point is that the control circuit for presetting / resetting each memory cell as desired is incorporated in the random access memory having the integrated circuit structure. That is, when a bit address at an arbitrary address to be preset / reset is specified from the outside,
By generating a preset / reset signal from the control circuit for the memory cell corresponding to the bit address at the arbitrary address, the memory cell corresponding to the bit address at the arbitrary address is preset / reset as desired. Further, based on the start address and end address to be externally preset / reset, when the control circuit simultaneously generates a preset / reset signal for all the memory cells from the start address to the end address, those memory cells are It can be preset / reset as desired. Furthermore, the former is the first
And the latter as a second control circuit, both of which are built-in, and when either of them is selectively operated by designation from the outside, the memory cell may be mounted in any form as necessary. It can be preset / reset.

By the way, the first random access memory is
When both the control circuit and the second control circuit are built in, it is desirable that these control circuits are specifically configured as a microprocessor. In any case, if a random access memory in which at least one of the control circuits is incorporated is provided in the information processing device as a main memory or a buffer memory, the information processing device performs special processing. in performing, are those possible to improve the processing efficiency.

[0008]

EXAMPLES Hereinafter, the present invention based on various embodiments will be described with reference to FIG. 10 from FIG. Embodiment: Part 1 FIG. 1 shows a configuration of a random access memory as an example in which all memory cells at each of a plurality of continuous addresses can be preset / reset simultaneously. In this example, the memory address space is set to addresses 0 to 3 and 1 to 1 address.
When a memory cell is allocated, that is, when the number of addresses is 4,
It is assumed that the data width of one address is 1 bit. Flip-flops (hereinafter, referred to as FFs) 11 to 14 as memory cells have addresses 0 to 0, respectively.
3 are provided, but as shown in FIG.
An external 1-bit data input 1 is write-enabled for each of 11 to 14, and a preset / reset signal S × / corresponding to FFs 11 to 14 from the control block 10.
R × (× = 0 to 3) is input. In normal times, external 1-bit data input 1 is selectively enabled for writing in each of FFs 11 to 14,
The 1-bit data written in each of F11 to F14 is read out to the outside by the read address 9 from outside.
Each of 1 to 14 is forcibly preset / reset by a preset / reset signal S × / R × from the control block 10.

First, the write / read operation in a normal state will be described as follows. That is, writing in a normal state is performed by decoding the external write address 3 by the address decoder 2 in a state where the external data input 1 is commonly input to each of the FFs 11 to 14. It has become. In normal writing, a decoding operation in the address decoder 2 is permitted by a write enable signal 4 from the outside, but a decoding output from the address decoder 2 is selectively supplied to one of the FFs 11 to 14 as a clock. As a result, the data is written into the FF corresponding to the write address 3. On the other hand, in reading, an external read address 9 is supplied to selector 15 as a selection output control signal, so that FF 1
From the selector 15 to which the Q output from each of 1 to 14 is input, the Q output of the FF corresponding to the read address 9 is output to the outside as a data output.

On the other hand, when data at successive addresses is preset / reset, the control block 10 presets / resets the FFs 11 to 14 as desired. As shown, control block 1
0 is externally input with SA (start address) 5, STA (end address) 6, reset mode signal 7, (pre) set mode signal 8 and EN (operation enable signal) 16, but operation enable signal Only when 16 permits the operation, the control block 10
A (start address) 5, STA (end address) 6, based on the reset mode signal 7 and the set mode signal 8, which is intended to predetermined preset / reset signal S × / R × is generated. FIG. 2 shows the control block 10
2 shows a specific configuration in one example. As shown in the figure, SA (SA ₁ SA ₀ ) 5 and STA (S
TA ₁ STA ₀ ) 6 is decoded by the decoder 10-1 so that the address range to be preset / reset is identified. Usually S
As A <STA , SA and STA are designated from the outside. In this example, address 3 and address 0 are assumed to be continuous, and the case where SA ≧ STA is allowed. That is, in the case of SA = STA is to preset / reset control is performed on only a start address one address. If STA <SA,
For example, when SA = address 2 and STA = address 0 , preset / reset control is performed for three addresses of addresses 2, 3 , and 0. As shown in the figure, only when the operation enable signal 16 permits the operation , the decoder 10-1 sets SA and ST.
All combinations of A are identified and decoded outputs to that effect are output. These decoded outputs are output from the multi-input OR gates 10-6 to 10-1 provided for the addresses 0 to 3.
0-9, the AND gates 10-10, 10-11, 10-1210,
10-13, 10-14, 10-15, 10-16, 1
One or more pairs 0-17 are in the activated state. On the other hand, the reset mode signal 7 and the set mode signal 8 are input simultaneously to the inverters 10-2 and 10-2.
-3 and the AND gates 10-4 and 10-5 are mutually inhibited, and only one of the paired AND gates is set in an activated state. After all, multi-input OR gate 10-6-1
0-9 and AND gates finally activated by AND gates 10-4 and 10-5, all FFs in the address range defined by SA and STA.
Are preset / reset. For example, when SA = address 2 and STA = address 0 and a preset operation is designated from the outside, AND gates 10-14, 10-16, and 10-10
Are simultaneously activated, and preset signals S2 and S are output from AND gates 10-14, 10-16 and 10-10, respectively.
By generating 3, S0, the FFs 12, 14, and 11 can be preset at the same time. In this example, the number of memory cells at one address is one, but the present invention is applicable to the case of two or more. Control block 10
The preset / reset signal S.times./R.times. May be applied to those memory cells in common.

Embodiment 2 FIG. 3 shows an example in which when the number of addresses is two and one address consists of two bits, all memory cells at an address arbitrarily designated from the outside can be preset / reset. 1 shows the configuration of the random access memory in FIG.
As already described in the first embodiment, SA = STA is allowed in the first embodiment. Therefore, the configuration of the random access memory in the first embodiment is more general, but especially only in one address unit. The configuration in the case where the preset / reset is permitted is shown daringly. In this case, in normal writing, the lower one bit of the external 2-bit data input 1 is applied to each of the FFs 11-1 and 12-1, and the upper one bit is applied to the FFs 11-2 and 12-2. In the state in which the address is commonly input to the
Are performed by being decoded by the address decoder 2. In normal writing, the decoding operation in the address decoder 2 is allowed by the external write enable signal 4, but the decoding output from the address decoder 2 is used as a clock for the FFs 11-1 and 11-1.
The data input is simultaneously written to two FFs corresponding to the write address 3 by being selectively applied to 11-2 or the FFs 12-1 and 12-2. On the other hand, in reading, an external read address 9 is supplied to the selectors 15-1 and 15-2 as a selection output control signal, so that each of the FFs 11-1, 11-2, 12-1 and 12-2 outputs the selected address. Each of the selectors 15-1 and 15-2 to which the Q output is input outputs a data output corresponding to the read address 9 to the outside.

On the other hand, when data at an arbitrary address from the outside is preset / reset, the control block 17 controls the FFs 11-1, 11-2, 12-1 and 12-1.
-2 is preset / reset as desired. As shown in the figure, an address 18 as a preset / reset target, a set / reset mode signal 19 and an EN (operation enable signal) 16 are externally input to the control block 17. only if acceptable, from the control block 17 based on the address 18 and a set / reset mode signal 19, a predetermined preset / reset signal S00～S11, it has become what R00~S11 is generated. FIG. 4 shows a specific configuration of an example of the control block 17. As shown, address 1
8 can be decoded by each of the decoders 17-1 and 17-2.
And the set / reset mode signal 19. The decoder 17-1 and 17-2 both allow the decoding operation to be permitted by the operation enable signal 16 input together with the address 18, but the decoding operation at that time also includes the set / reset mode signal 19
It is also controlled by After all, set /
When the reset mode signal 19 is in the reset mode, the decoding operation in the decoder 17-1 is allowed, and when it is in the set mode, the decoding operation in the decoder 17-2 is allowed. . As a result, for example, when it is specified that the data at the address 1 should be preset, the decoder 17-2
Generates preset signals S10 and S11.
The FFs 12-1 and 12-2 are both preset.

Embodiment 3 FIG. 5 shows an example in which when the number of addresses is 2 and the address consists of 2 bits, an arbitrary memory cell at an address arbitrarily designated from the outside can be preset / reset. 2 shows a configuration of a random access memory. In this case, the writing / reading operation in the normal state is the same as that in the second embodiment, so that further description is not required. Here, an operation in a case where an arbitrary memory cell at an address arbitrarily designated from the outside is preset / reset by the control block 20 will be described.
Based on the external write address 3, bit address 21, set / reset mode signal 22 and operation enable signal 16 from the control block 20, the memory cell corresponding to the bit address 21 in the write address 3 is preset. / Reset signal is generated. FIG. 6 shows a specific configuration of an example of the control block 20. In this case, the bit address 18 is decoded by each of the decoders 20-1 and 20-2, but whether or not decoding is possible depends on the operation enable signal 16 and the set / reset mode signal 22. Both the decoders 20-1 and 20-2 are allowed to perform the decoding operation by the operation enable signal 16 input together with the bit address 21, but the decoding operation at that time is also controlled by the set / reset mode signal 22. Is what is being done. As a result, when the set / reset mode signal 22 is in the reset mode, the decoding operation in the decoder 20-1 is allowed, and when it is in the set mode, the decoding operation in the decoder 20-2 is allowed. Is what it is. Decoder 20-1 1,20 decoded output from over 2 R0, R1, S0, S1 each further demultiplexers 20-1 3 the write address 3 as allocation control signal
It is sorted from 20-6. As a result, for example, when it is specified that the bit address 1 in the address 1 is to be preset, the preset signal S1 corresponding to the bit address 1 is generated from the decoder 20-2. Since S1 is further obtained as a preset signal S11 from the demultiplexer 20-6 by the write address 3, FF
12-2 is to be preset. Embodiment: Part 4 FIG. 7 shows that, when the number of addresses is 2 and each address is composed of 2 bits, and when all memory cells at each of a plurality of consecutive addresses are simultaneously preset / reset, an arbitrary designation is externally made. This shows a configuration of a random access memory as an example in which any of cases where an arbitrary memory cell at an address is preset / reset can be selected. Since the writing / reading operation in the normal state can be easily understood from the above description, no further description is required. Here, control block 2 in the present example
In the third case, the control block 23 is configured to have substantially the same function as the control blocks 10 and 23 described above. FIG. 8 shows a schematic configuration of the control block 23. As can be seen from the figure, the control block 23-1 is the control block 20 described above, and the control block 23-2 is the control block 23 described above. 10, and the output from each of the control blocks 23-1, 23-2 is either
Under the control of the switching mode signal 24 from the outside, the selector 23-3 selectively outputs.

Embodiment 5 FIG. 9 shows a configuration in which most of the control blocks in the embodiment 4 are replaced with a microprocessor. As shown, the control block 25 in this example includes an external address bus 26 and a bidirectional data bus 2.
7 and the control bus 28, necessary information is taken in, and an address operation is performed in a predetermined manner.
A preset / reset signal is generated for each of the FFs 11-1, 11-2, 12-1, 12-2. FIG. 10 shows a schematic configuration of the control block 25. As shown in the figure, the control block 25 is mainly composed of a microprocessor 25-1, and a 3-bit address operation result from the microprocessor 25-1 is decoded by a decoder 25-2 provided on a data bus 27. Thus, a preset / reset signal for each of the FFs 11-1, 11-2, 12-1, 12-2 is generated.

The random access memory having an integrated circuit structure according to the present invention has been described above. However, when the information processing device for performing special processing is provided as a main memory or a buffer memory, the special processing is efficiently performed. In order to improve the processing performance.

[0016]

As described above, according to the first aspect , all data in an arbitrary continuous address space is all
In updating the "1" / "0", a random access memory was allowed to occur rapidly without the update by conventional write process is also the case of claim 2, 3, switching from external According to the request, the special
Arbitrary continuous addresses, allowing constant bit data to be updated
A random access memory which enables updating of all data in a space to all "1" / "0" quickly without performing a normal writing process . According to 6
If at least
Information processing enabling data to be updated to all "1" / "0" promptly without normal write processing
Devices that have become a thing obtained, respectively.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a random access memory in which all memory cells at a plurality of consecutive addresses are simultaneously preset / resetable;

FIG. 2 is a diagram showing a specific configuration of an example of a control block as a main part thereof;

FIG. 3 is a diagram showing a configuration of a random access memory in an example in which all memory cells at an address arbitrarily designated from the outside are preset / resetable;

FIG. 4 is a diagram showing a specific configuration of an example of a control block as a main part thereof;

FIG. 5 is a diagram showing a configuration of a random access memory in an example in which an arbitrary memory cell at an address arbitrarily designated from the outside is preset / resettable;

FIG. 6 is a diagram showing a specific configuration of an example of a control block as a main part thereof;

FIG. 7 illustrates a case where all memory cells at a plurality of consecutive addresses are simultaneously preset / reset, and a case where an arbitrary memory cell at an address arbitrarily designated from the outside is preset / reset. The figure which shows the structure of the random access memory in the example in which the selection was possible.

FIG. 8 is a diagram showing a schematic configuration of an example of a control block as a main part thereof;

FIG. 9 illustrates a case where all memory cells at each of a plurality of consecutive addresses are simultaneously preset / reset, and a case where an arbitrary memory cell at an address arbitrarily designated from the outside is preset / reset. The figure which shows the structure of the random access memory in the example in which the selection was possible.

FIG. 10 is a diagram showing a schematic configuration of a control block as a main part thereof;

[Explanation of symbols]

2 ... decoder, 10, 17, 20, 23, 25 ... control block, 11 to 14, 11-1, 11-2, 12-1,
12-2: flip-flop (memory cell), 15, 1
5-1、15-2 ... selector

Claims (6)

(57) [Claims] An N (N: 1) corresponding to an address based on an external access address and a write / read mode.
While N bit data can be simultaneously written into the above integers, the same applies hereinafter) memory cells, N bit data can be simultaneously read from the N memory cells simultaneously. , M (M: an integer of 1 or more;
A random access memory integrated circuit configuration of) × N bit capacity like, the memory cell each preset friendly, as a reset-friendly, based on the start address and end address to be preset / reset from the outside, the start address A random access memory including a control circuit for simultaneously generating a preset / reset signal for all the memory cells from the end address to the end address. 2. A method according to claim 1, wherein N bit data is simultaneously written into N memory cells corresponding to the address based on an external access address and a write / read mode. Is a random access memory having an M × N-bit capacity integrated circuit in which N bit data can be read simultaneously at the same time, wherein each memory cell is presettable and resettable, and externally preset. A first control circuit for generating a preset / reset signal for a memory cell corresponding to a bit address at an arbitrary address based on a bit address at the arbitrary address to be reset / reset from an external preset / reset All memos from the start address to the end address are calculated based on the start address and the end address. A second control circuit for simultaneously generating a preset / reset signal for the cell is provided, and either the first control circuit or the second control circuit responds to a switching mode signal from the outside. A random access memory with a structure that can be selectively operated. 3. A method according to claim 1, wherein N bit data is simultaneously written into N memory cells corresponding to the address based on an external access address and a write / read mode. Is a random access memory having an M × N-bit capacity integrated circuit in which N bit data can be read simultaneously at the same time, wherein each memory cell is presettable and resettable, and externally preset. A first control circuit for generating a preset / reset signal for a memory cell corresponding to a bit address at an arbitrary address based on a bit address at the arbitrary address to be reset / reset from an external preset / reset All memos from the start address to the end address are calculated based on the start address and the end address. When the cell is provided with a second control circuit for simultaneously generating a preset / reset signal, the first control circuit and the second control circuit are controlled by various control signals from the outside, A random access memory configured as a single microprocessor that generates a preset / reset signal for a desired memory cell by calculating various address signals. 4. A method according to claim 1, wherein N bit data is simultaneously written into N memory cells corresponding to the address based on an external access address and a write / read mode. Is a random access memory having an M × N-bit capacity integrated circuit in which N bit data can be read simultaneously at the same time, wherein each memory cell is presettable and resettable, and externally preset. A random access memory provided with a control circuit for simultaneously generating a preset / reset signal for all memory cells from the start address to the end address based on a start address and an end address to be reset; Or an information processing apparatus provided as a buffer memory. 5. A method according to claim 1, wherein N bit data is simultaneously written into N memory cells corresponding to the address based on an external access address and a write / read mode. Is a random access memory having an M × N-bit capacity integrated circuit in which N bit data can be read simultaneously at the same time, wherein each memory cell is presettable and resettable, and externally preset. A first control circuit for generating a preset / reset signal for a memory cell corresponding to a bit address at an arbitrary address based on a bit address at the arbitrary address to be reset / reset from an external preset / reset All memos from the start address to the end address are calculated based on the start address and the end address. A second control circuit for simultaneously generating a preset / reset signal for the cell is provided, and either the first control circuit or the second control circuit responds to a switching mode signal from the outside. An information processing device including a random access memory having a structure which is selectively operated as a main memory or a buffer memory. 6. A method according to claim 1, wherein N bit data can be simultaneously written into N memory cells corresponding to the address based on an external access address and a write / read mode. Is a random access memory having an M × N-bit capacity integrated circuit in which N bit data can be read simultaneously at the same time, wherein each memory cell is presettable and resettable, and externally preset. A first control circuit for generating a preset / reset signal for a memory cell corresponding to a bit address at an arbitrary address based on a bit address at the arbitrary address to be reset / reset from an external preset / reset All memos from the start address to the end address are calculated based on the start address and the end address. When the cell is provided with a second control circuit for simultaneously generating a preset / reset signal, the first control circuit and the second control circuit are controlled by various control signals from the outside, Random access memory configured as a single microprocessor that generates a preset / reset signal for a desired memory cell by calculating various address signals of Processing equipment.