JPH0540698A - Main storage page managing system - Google Patents

Abstract

PURPOSE:To perform the switching of a page based on frequency in use and elapsed time after rewrite. CONSTITUTION:This system is provided with a frequency in use counter representing the frequency in use of the page shown in a page address generation circuit 3 by fetching an R bit outputted from an R/C bit generation circuit 2, a counter for time lapse that is counted up by inputting a clock signal outputted from a clock distribution circuit and with plural bits not overflowing between a page management request signal and a next page management request signal, and a reset control circuit which resets all the frequency in use counters and counters for time lapse in a block corresponding to the number of pages in main storage in one to one when receiving the page management request signal, and capable of performing the reset of only the counter for time lapse of the block corresponding to the page of the main storage on which the rewrite is performed when it is rewritten.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a main memory page management system,

2. Description of the Related Art Conventionally, this type of page management system has one R bit and one C bit for each page, and when the page is accessed by a read command, only the R bit becomes "1" and a write operation is performed. When the page is accessed by the instruction, both the R bit and the C bit are set to "1" and the state is held. Which page is referred by referring to these 2 bits, and which page is rewritten. I was just deciding.

FIG. 5 shows one of conventional examples, and FIG. 6 shows a system configuration diagram.

[0003]

In the conventional main memory page management method described above, the bit remains "1" once a page which is a read command or a write command is accessed, so that page is retained. Although it can be determined whether or not the file has been referred to, there is a drawback in that it cannot be transferred in page units to the external storage because the frequency of use and the passage of time cannot be known.

[0004]

An R / C bit generation circuit for generating an R bit indicating whether or not a page is referenced and a C bit indicating whether or not a page is rewritten by a main memory read signal or a main memory write signal. , A page address generation circuit that takes in an address signal output from another processor and generates a page address, and a page address signal from the page address generation circuit that outputs the R bit and the C bit output from the R / C bit generation circuit. And an RC memory for writing each page by fetching the RC memory write timing signal, and the RC memory capable of temporarily holding the data, and for each block in the time from the page management request signal to the next page management request signal. By fetching the R bit output from the R / C bit generation circuit, the page address A use frequency counter that indicates how much the page indicated by the generation circuit has been used and a clock signal output by the clock distribution circuit counts up and does not overflow between the page management request signal and the next page management request signal. When a time passage counter having a plurality of bits and a page management request signal output from the arithmetic processor at regular intervals are received, the number of pages in the main memory and the usage frequency counters and time of all blocks corresponding to one to one A reset control circuit for resetting the elapsed counter and resetting only the time elapsed counter of the block corresponding to the page when the page with main memory is rewritten, and the page management request signal from the arithmetic processor By receiving the usage frequency counter and time lapse And a RC circuit for receiving the data of the frequency counter and rearranging the data of the usage frequency counter in ascending order first, and then rearranging the data of the time lapse counter in the descending order of the portion having the smallest value. An R / C bit output circuit for outputting the R bit and C bit output by fetching the page address signal and the RC memory read timing signal from the processor to the R / C bit information request signal from the processor And a main memory page management method characterized by including.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which is an example relating to a main memory 1 having n pages. FIG. 3 is a block diagram of a system to which the present invention is applied and shows a state in which an internal block 31, an arithmetic processor 32 and a processor 33 are connected. 2 shows the details of the counter control unit 6 in FIG.

The command signal output from the processor 32 to the command signal line 28 is decoded by the command decoder 29 to become a read signal or a write signal, and the main memory read signal line 10 or the main memory write signal line 11 respectively causes the main memory. It is output to 1.

At the same time, one page of the main memory 1 is accessed by the address signal output from the arithmetic processor 32 to the address signal line 12. The R / C bit generation circuit 2 takes in the signals of the main memory read signal line 10 or the main memory write signal line 11, generates R bits and C bits, and outputs R bits to the R bit signal line 16 and the C bit signal line 17, respectively. It outputs a bit signal and a C bit signal.

Further, the page address generation circuit 3 fetches the address signal output to the address signal line 12,
A page address is generated and output to the RC memory 4 and the count controller 6 via the page address signal line 19.

The R bit signal and the C bit signal generated by the R / C bit generation circuit 2 are supplied to the RC memory write timing signal line 14 by the selector signal 30 of the selector 9.
Is selected and written at the page address indicated by the page address signal output from the page address generation circuit 3 to the page address signal line 19 at the timing of the timing signal output to the timing signal line 18.

The time lapse counter 42 of the counter holding unit 37 shown in FIG.
Thus, "1" is added each time a clock signal distributed to all blocks is input via the clock signal line 40.

The R bit signal and the C bit signal are R
At the same time as being written in the C memory 4, it is also output to the counter control unit 6. By the R bit signal fetched by the counter control unit 6, the usage frequency counter 4 of the block corresponding to the accessed page of the main memory of the counter holding unit 37.
"1" is added to the data of 1, while the counter control unit 6
The C-bit signal taken into the reset control circuit 38 is input from the reset control circuit 38 to the reset signal line 39-.
The counter signal of the time lapse counter 42 of the block selected by the page address signal line 19 is reset by the reset signal output to 2. When the value of the usage frequency counter of a certain block reaches the maximum value, the counter does not count up and holds the value as it is.

Arithmetic processor 32 or processor 3
The above operation is performed each time the memory 3 accesses the main memory 1 and issues a write or read command.

When a request signal is output from the arithmetic processor 32 to the page management request signal line 26, the above operation is completed. When the operation is completed, the operation is temporarily stopped and stored in the counter holding unit 37. The usage frequency count data for each page and the information data of the elapsed time counter data are respectively used in the usage frequency counter data line 2
It is transferred to the sorting circuit 7 through 0 and the counter data line 21 for the passage of time.

The information data transferred to the sort circuit 7 is
The data of the frequency counter 41 is first sorted in ascending order so that a page with a low frequency of use and a long time after access can be easily searched, and then the data of the time lapse counter 42 for the portion with the smallest value. Are sorted in ascending order, and the sorted page management information is output to the page sort result output signal line 25 and transferred to the processor 32.

When a request signal is issued from the arithmetic processor 32 to the page management request signal line 26, the reset control circuit 38 sends a request after the data of the usage frequency counter 41 and the elapsed time counter 42 is transferred to the sort circuit 7. Receiving signals, reset signal line 39-1, reset signal line 3
The reset signal is distributed via 9-2 to the usage frequency counters 41 and the elapsed time counters 42 of all the blocks of the counter holding unit 37 to clear all the data of the counters. After that, the arithmetic processor 32 or the processor 33
Accesses the main memory 1 and issues a write command or a read command.

R / C of page with arithmetic processor 32
When only the bit information is desired, the arithmetic processor 32 outputs a request signal to the R / C bit information request signal line 15,
It is taken into the R / C bit output circuit 8.

The page address generation circuit 3 generates a page address that the arithmetic processor wants to know, the RC memory read timing signal line 13 is selected by the page address signal and the select signal 30 of the selector 9, and the timing signal line 18 is selected by the selector 9. The R / C memory 4 outputs the R bit and C bit signals to the R bit signal line 22 and the C bit signal line 23, respectively, by the output timing signal,
It is output to the R / C bit output signal line 24 by the R / C bit output circuit 8 and transferred to the arithmetic processor 32.

FIG. 4 shows the page management request signal 26 and the next page management request signal 2 output from the arithmetic processor 32.
The above operation up to 6 is described in a time chart.

In FIG. 4A, when the page management request signal 26 is received, B is written to page 0 of the main memory 1, C is read from page n of the main memory 1, When D is written to page 1 of main memory 1,
E is for writing to page n of main memory 1, F is for reading from page 0 of main memory 1, G is for writing to page 1 of main memory 1, and H is for The states of the use frequency counter 41 and the elapsed time counter 42 of each block when the next page management request signal is received are shown.

In FIG. 4, page history information such that page 0 is ejected when the relationship of n ₀ , k ₀ , l ₀ is n ₀ = k ₀ <l ₀ and n ₁ > 5. Output at the time of H.

[0022]

According to the present invention, by adopting the configuration described above, it is possible to know the frequency of use for each page and how much time has elapsed since the page was accessed, so that more accurate page management can be performed and the frequency of use can be reduced. This has the effect of finding the page with the lowest time and the longest elapsed time since rewriting, and transferring that page and external storage in page units.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a counter control unit in FIG.

FIG. 3 is a system block diagram to which the present invention is applied.

FIG. 4 is a time chart of the embodiment shown in FIG.

FIG. 5 is a block diagram of the prior art.

FIG. 6 is a block diagram of a system to which a conventional example is applied.

[Explanation of symbols]

 1 main memory 2 R / C bit generation circuit 3 page address generation circuit 4 R / C memory 5 register 6 count control unit 7 sort circuit 8 R / C bit output circuit 9 selector 27 clock distribution circuit 29 command data 31, 34 internal block 32 arithmetic processor 33 processor 37 counter holding unit 38 reset control circuit 41 usage frequency counter 42 time elapsed counter

Claims (1)

[Claims] 1. An R / C that generates an R bit indicating whether or not a page is referenced and a C bit indicating whether or not a page is rewritten by a main memory read signal or a main memory write signal.
Takes in the address signal output from the bit generation circuit and other processors,
A page address generation circuit for generating a page address, and R bit and C output from the R / C bit generation circuit
Bits are fetched from the page address signal from the page address generation circuit and the RC memory write timing signal to perform writing for each page, and the RC memory capable of temporarily holding the data and the page management request signal A usage frequency counter that indicates how much the page indicated by the page address generation circuit has been used by fetching the R bit output from the R / C bit generation circuit for each block in the time until the page management request signal. , A time lapse counter with multiple bits that counts up when the clock signal output from the clock distribution circuit enters and does not overflow between the page management request signal and the next page management request signal, and is output at regular intervals from the arithmetic processor When a page management request signal is received The number of pages with the memory and the one-to-one
Reset control that resets the above-mentioned usage frequency counters and time lapse counters of all blocks corresponding to the above, and resets only the time lapse counters of the blocks corresponding to that page when rewriting to a page with main memory By receiving the page management request signal from the circuit and the arithmetic processor, the data of the frequency-of-use counter and the time-lapse counter are received, and the data of the frequency-of-use counter is first sorted in ascending order, and then the smallest value is obtained. A sort circuit capable of rearranging the data of the counter for passage of time in descending order with respect to a portion, and R and C bits output by fetching a page address signal and an RC memory read timing signal from the RC memory from an arithmetic processor. R / C bit information request signal of Main memory page management method which comprises the R / C bits output circuit for outputting the arithmetic processor by taking.