JPH0729378A - Memory and its control circuit - Google Patents

Abstract

PURPOSE:To accelerate an I/O group enabling access time at the time of a transition from the write state of a group to the read state of the other group in a memory constitution in which plural I/O group are divided into groups and access is performed at every group selectively. CONSTITUTION:I/O group are divided into two groups of an upper byte group and a lower byte group and memory cells are divided into two parts 3, 4 according to groups. At this time, for example, during a write is being performed to memory cells 4 of the upper byte, the sense-amplifier 5 of the side of the lower byte being non-selected is made to be in an active state to be in a readable state. Thus, the I/O group enabling access is accelerated by making a byte enabling access time equal to an output enabling access time with respect to even the transition of any kind of state of the read/write to I/O groups.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a plurality of I / O groups, memory cells are divided corresponding to the I / O groups, and the I / O groups are designated and accessed by a common address signal. And a control circuit for the memory.

[0002]

2. Description of the Related Art As a conventional memory of this kind, 1-bit write (write) 1-bit read (read), 4-bit write 4-bit read, or 8
I / O such as bit writing and 8-bit reading
The group was one, and the memory cells were also one block. However, in recent years, as the bit length of the CPU has expanded from 8 bits to 16 bits, 32 bits, or 64 bits, the bit width and function of the memory are required to correspond to it.

[0003]

As one of the memories corresponding to the above requirements, for example, an I / O group divided into a high-order byte group and a low-order byte group having a total of 16 bits, and two corresponding I / O groups are provided. A memory having divided memory cells and a control circuit for each group of I / O groups and capable of selecting and accessing the upper byte or the lower byte is conceivable.

However, in such a memory, since the address signal, the chip enable signal, the output enable signal, and the write enable signal are common regardless of the I / O group, one byte group is selected and written. Immediately after that, if the other byte group is selected and read, the I state is disabled in the write state.
The I / O group sense amplifier does not operate in the non-active state, and when the I / O group transitions to the enable state and the I / O group transitions to the enable state at the same time, the sense amplifier enters the active state and starts sensing.
/ O group enable access time T _BO becomes longer,
Output enable access time is longer than T _oe and T _BO
However, there is a problem in that it is lacking in speedup.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a group of a plurality of I / O groups and to selectively access each group. It is an object of the present invention to provide a memory and its control circuit for speeding up the I / O group enable access time when the write state is changed to the read state of another group.

[0006]

To achieve the above object, in the memory of the present invention, an I / O group formed into a plurality of groups and a memory divided corresponding to the I / O group. The cell has a cell and the I /
A group of O groups is selected to write / read to / from each divided portion of the memory cell, and when accessing the memory portion with the same address signal, write to any one of the divided portions of the memory cell. And a memory control circuit having means for keeping the other divided portions in a readable state.

In the above structure, the means for making the other divided portions of the memory control circuit readable can be realized by means for activating the sense amplifiers of the other divided portions.

The memory control circuit has a chip select signal and a write enable signal in a memory having a plurality of I / O groups for a common address signal and memory cells divided corresponding to the I / O groups. When a signal is input, the active signal is stopped in the sense amplifier of the memory cell corresponding to the specified I / O group, and the non-specified I / O
It can be realized by a configuration including means for outputting an active signal to the sense amplifier of the memory cell corresponding to the O group.

[0009]

In the memory and the control circuit thereof according to the present invention, a sense amplifier is applied to an unselected disabled I / O group while writing (writing) to a certain I / O group. By setting a read (read) state such as an active state, the output enable access time T for any read / write state transition to the I / O group
_oe = I / O group enable access time T _BO is satisfied and T _BO is speeded up.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a memory according to an embodiment of the present invention. In the present embodiment, an example will be described in which the overall configuration of the memory is 16 bits and the I / O group is divided into two groups of upper byte and lower byte.

In FIG. 1, 1 is an address input section, 2 is a row / column decoder which decodes an address signal from the address input section into rows and columns, and 3 and 4 correspond to the above two groups, lower byte and upper byte. Memory cells divided into bytes,
Numerals 5 and 6 are sense amplifiers for reading data from the memory cells 3 and 4, 7, 8 are write drivers for writing data to the memory cells 3 and 4, and 9 and 10 are provided corresponding to I / O groups. I / O buffer circuit, 11 is an I / O group of lower bytes (hereinafter, LB
Side) I / O terminal, 12 is an I / O terminal of an upper byte I / O group (hereinafter, UB side), and 13 is a memory control circuit.

The memory control circuit 13 in this embodiment is
Chip enable signal CE- common to each I / O group
(Hereinafter, "-" after the signal name indicates that it is a bar signal), write enable signal WE-, output enable signal OE-, and selection signal UB for each I / O group.
-(Upper byte selection), LB- (lower byte selection) input terminals are provided.
Control signals 16 and 17 are sent to the 6 and write drivers 7 and 8 to control their active / non-active, read / write corresponding to a designated I / O group, and an I / O buffer circuit. I for 9 and 10
It has a function of transmitting the / O buffer enable signals 14 and 15 to output the stored data to the I / O terminals 11 and 12.

FIG. 2 is a block diagram of a logic circuit inside the memory control circuit 13 for performing active / non-active control of the sense amplifiers 5 and 6 in this embodiment. Further, FIG. 3 is a diagram showing a truth table of the logic circuit. The chip enable signal CE-, the write enable signal WE-, the upper byte selection signal UB- and the lower byte selection signal LB- correspond to the signals from the input terminals shown in FIG. First, these signals are inverted by inverters 21, 22, 23 and 24, respectively, and CE, WE,
It becomes the UB and LB signals. Both signals WE and UB are input to the 2-input NAND gate 25, both signals WE and LB are input to the NAND gate 26, and the outputs of these NAND gates 25 and 26 are respectively 2-input AND gate 2
7 and 28 are input. Further, AND gates 27, 2
The CE signal is input to each of the eight, and the output of the AND gate 27 becomes the control signal of the sense amplifier on the upper byte side, and the output of the AND gate 28 becomes the control signal of the sense amplifier on the lower byte side. When this control signal is at H (high) level, the sense amplifier is active, and when it is at L (low) level, it is inactive.

In the present embodiment, as shown in the truth table of FIG. 3, the sense amplifier becomes active when the chip enable signal CE- is enabled (L level) and the write enable signal WE- is disabled. (H level) and when the chip enable signal CE- and the write enable signal WE- are enabled (L level), the I / O group selection signals UB-, LB-
Is disabled (H level).

The operation and action of one embodiment configured as described above will be described. 4 (a), (b), (c) and FIG. 5 are time charts for explaining the operation.

First, the normal operation will be described with reference to FIG.
When the address is determined by the address input from the address input unit 1, the row / column decoder 2 selects the memory cells 3 and 4 of the lower byte and the upper byte, respectively, and outputs the signals output from the memory cells 3 and 4. The I / O buffer circuit 9 is formed by the sense amplifiers 5 and 6 of the lower byte and the upper byte, respectively.
The amplified signal is transmitted to 10 and output from the I / O terminals 11 and 12.

Here, the output enable access time T _oe
Consider a case where a specification of = byte enable access time T _BO is set. FIG. 4A shows a timing chart of output enable access. In this case, the sense amplifiers 5 and 6 are activated by the control signals 16 and 17 when the address is determined, and the read data is stored in the I / O buffer circuits 7 and 8.
In this state, when the OE- signal is enabled and the I / O buffer enable signals 14 and 15 are enabled, the I / O buffer circuits 9 and 10 to the I / O terminal 11 and
The data is transmitted through 12. The access time during this period is _Toe . On the other hand, FIG. 4B shows a timing chart of byte enable access. In the byte enable access, since the WE- signal is in the read state, even when the UB- and LB- signals are in the disabled state, when the address is determined, the sense amplifier 5 and the sense amplifier 5, as in FIG. 6 becomes active. For this reason,
The access time T _BO1 from the time when the UB- and LB- signals are enabled and the I / O buffer enable signals 14 and 15 are enabled until the data is output is the access time T _oe of FIG. Becomes the same as
The specification of T _oe = T _BO can be satisfied.

However, in the case of FIG. 4C (when the LB side is byte-enable access from the state of writing the UB side), when the WE- signal is in the writing state, writing to the UB side in the enabled state, Writing is not performed on the LB side in the disabled state, and since the WE- signal is common to the UB and LB sides, the LB side sense amplifier 5 is also in the inactive state. Therefore, since the sensing by the sense amplifier 5 starts when the LB- signal is enabled, the byte enable access time T _BO2 becomes longer and becomes like a chip enable access time, and T _oe <T _BO2. I cannot _meet the specification of T _oe = T _BO .

Therefore, in the present embodiment, the circuit configuration of FIG. 2 makes the relationship of signals between WE−, UB−, and LB− as shown in FIG. That is, as shown in the truth table of FIG. 3, even if the WE- signal is in the write state, the sense amplifiers of the disabled byte group (I / O group, LB side in the example) are set to the active state. It is to make it possible to lead immediately. As a result, for example, when the write state is released and the select signal LB- signal is changed to perform the byte enable access as in the case of FIG. Since it is active, the byte enable access time T _BO3 becomes equal to T _oe as shown in FIG. 5, the specification of T _oe = T _BO can be satisfied, and the speed of T _OB can be increased.

Although not shown in the above embodiment, a memory having a standby mode may be provided with gate circuits before and after the sense amplifier and controlled by the CE- signal. Further, in the above embodiment, I /
The case where the O group is divided into the upper byte and the lower byte has been described, but the present invention has a plurality of I / Os.
The chip enable signal, the output enable signal, the write enable signal, and the address signal of the control signal are common regardless of the I / O, and the I / O is grouped into an arbitrary number of groups to select this I / O group. This is applicable to a memory that is individually provided and can be selectively controlled for each I / O group.

[0022]

As is apparent from the above description, according to the memory and its control circuit of the present invention, there are a plurality of I / O groups, and the address signal and the write enable signal are common.
In a memory capable of controlling the selection of I / O groups, the output enable access time = I / O enable access time is used to speed up the I / O enable access time even when the write enable signal and the I / O select signal have a special relationship. Can be planned.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a memory according to an embodiment of the present invention.

FIG. 2 is a logic circuit diagram inside a memory control circuit in the above embodiment.

FIG. 3 is a diagram showing a truth table of the logic circuit.

4A, 4B, and 4C are timing charts for explaining the operation of the above embodiment (part 1).

FIG. 5 is a timing chart (No. 2) for explaining the operation of the above embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Address input section 2 ... Row / column decoder 3, 4 ... Memory cell 5, 6 ... Sense amplifier 9, 10 ... I / O buffer circuit 11, 12 ... I / O terminal 13 ... Memory control circuit 21-24 ... Inverter 26, 27 ... NAND gate 28, 29 ... AND gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 11/34 362 H

Claims (3)

[Claims] 1. An I / O group that is grouped into a plurality, and the I / O group
A memory unit which has memory cells divided corresponding to groups of I / O groups and selects a group of the I / O group for a common address signal, and which can be written or read for each divided portion of the memory cells. A memory control circuit having means for keeping the other divided portion in a readable state while writing to one arbitrary divided portion of the memory cell when the memory portion is accessed by the same address signal. A memory provided with. 2. The memory according to claim 1, wherein the means for keeping the other divided portion of the memory control circuit in the readable state is means for activating the sense amplifier of the other divided portion. Memory. 3. A plurality of I / Os for a common address signal
When a chip select signal and a write enable signal are input to a memory having a group and memory cells divided corresponding to the I / O group, the sense amplifier of the memory cell corresponding to the designated I / O group is active. A control circuit for a memory, comprising means for stopping a signal and outputting an active signal to a sense amplifier of a memory cell corresponding to a non-designated I / O group.