JP2937203B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A semiconductor memory device, in particular, a memory in which a memory cell array is divided into a plurality of blocks and operated, relates to a write / read failure at the first memory access after power-on. A memory cell array divided into a plurality of blocks and a block provided corresponding to the plurality of blocks and corresponding to each of the plurality of blocks for the purpose of eliminating the possibility and thereby increasing the operation reliability. And a block selection circuit for sequentially supplying the selection signal to the plurality of block activation circuits in response to application of a power supply voltage, wherein the plurality of blocks are activated when power is turned on. Are activated at least once each.

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly, to a memory that operates by dividing a memory cell array into a plurality of blocks.

In recent years, as semiconductor memories have become faster and more highly integrated,
Since the current consumption tends to increase, it is required to reduce the current consumption.

[Conventional technology]

In a semiconductor memory in which a memory cell array is divided into a plurality of blocks, in order to suppress an increase in current consumption due to high speed and high integration, the cells of all blocks are not activated within one cycle without being activated. The selection is performed for each block based on the address designation from, and only the selected block is activated. One example of the configuration is shown in FIG.

In the drawing, reference numerals 40a to 40d denote a cell array divided into quarters, a reference numeral 41 denotes a starter which outputs an "L" level signal φs in response to power-on (power supply voltage Vcc), and a reference numeral 42 denotes a signal φs and an active low signal. NOR gate that responds to the row address strobe signal RASX, 43 is a refresh counter that responds to the output of the NOR gate 42, 44 is an inverter that responds to the active low column address strobe signal CASX, and 45 is the output of the refresh counter 43 And inverter
An address buffer that buffers the address signal ADD in response to the output of 44, and 46a to 46d are address buffers
The NAND gates 47a to 47d and 48a to 48d output the block selection signal in response to two different bits of the 4-bit block selection address signal ADD1 from 45, respectively. The output of the NOR gate 42, the output of the inverter 44 and the NAND gate 46a to A clock generator that generates a clock for memory access in response to a block selection signal from 46d, 49a to 4
9d and 50a to 50d are clock generators 47a to 47d and 48a, respectively, based on the address information ADD2 from the address buffer 45.
Row decoders and column decoders for selecting cells in response to clocks from .about.48d, and 51a to 51d multiplexers and sense circuits (MPX) for inputting and outputting data (D _IN / D _OUT ) with the outside, respectively.・ S / A).

[Problem to be Solved by the Invention] According to the conventional configuration described above, the power supply voltage Vc
If the external address ADD is fixed when c is applied (when the power is turned on), if block selection is performed based on the external address ADD,
The blocks (cell groups) to be selected and the peripheral circuits corresponding thereto are limited.

Therefore, even if a dummy cycle is added when the power is turned on, there is a cell group in which the block is not selected (that is, the cell is never activated). Therefore, if a cell in the inactivated block is selected and written / read after completion of the dummy cycle, 1
A malfunction may occur only the second time, that is, the first memory access. This is not preferable from the viewpoint of operation reliability.

The present invention has been made in view of the problems in the related art, and eliminates the possibility of write / read failure at the time of initial memory access after power-on, thereby improving the operation reliability. It is intended to provide.

[Means for solving the problem]

In order to solve the above-described problem, the present invention forcibly switches the external address selected as a block at the time of start-up (at the time of power-on) to an internal address, and changes the external address during a predetermined period (dummy cycle) after power-on. By updating the internal address, all the divided blocks are sequentially selected (activated).

Thus, as shown in principle block diagram of Figure 1, the semiconductor memory device of the present invention includes a memory cell array 1 divided into a plurality of blocks B _l .about.B _n, each provided for each of the plurality of blocks selects a plurality of block activation circuit 2 _l to 2 _n to activate the respective response block corresponding to the selection signal S _l to S _n, the predetermined block activation circuit from said plurality of blocks activation circuit A block selection circuit 3 and switching means for switching between an external selection signal and an internal selection signal in response to a control signal from the block selection circuit;
The switching means selects an internal block selection signal, and the block selection circuit activates each of the plurality of blocks at least once.

The block selection circuit sequentially selects a plurality of block activation circuits in response to application of a power supply voltage at power-on.

Further, a refresh counter used only for refreshing the memory cell array is provided.

(Operation)

According to the above-described configuration, when the power is turned on, the selection signal S _l to S _n select multiple blocks activation circuit 2 _l to 2 _n sequentially by simply supplying from the block selecting circuit 3, whereby the plurality of blocks B _l .about.B _n at least once each is activated.

Therefore, no matter which block cell is selected at the time of the first memory access after the power is turned on, all the blocks can be activated without omission, and the activation time of the entire block can be reduced. It becomes possible.

The details of other structural features and operations of the present invention will be described with reference to the accompanying drawings and embodiments described below.

〔Example〕

FIG. 2 shows a circuit configuration of a semiconductor memory device as one embodiment of the present invention.

In the drawing, reference numerals 10a to 10d denote cell arrays divided into blocks, each having a memory capacity of 1/4, and having a configuration in which DRAM cells (not shown) are arranged in a matrix. Reference numeral 11 denotes a starter, which is turned on (power supply voltage Vc
In response to c), when the power supply voltage reaches a predetermined level Vo (see FIG. 3), the output signal φs is set to “L” level. 12
Is a NOR gate that responds to the output signal φs of the starter 11 and the active low row address strobe signal RASX, 13 is a refresh counter that responds to the output of the NOR gate 12, and 14 is a response to the active low column address strobe signal CASX. And an address buffer 14 for buffering the address signal ADD in response to the output of the refresh counter 13 and the output of the inverter 14.

Reference numeral 16 denotes a block counter, which is constituted by, for example, a binary counter using a delay flip-flop,
Has a function of counting the output of the NOR gate 12 (the number of rising edges of the row address strobe signal RASX) in response to the change of the output signal φs to “L” level.
The block counter 16 outputs 2-bit signals φa and φb (see FIG. 3) based on the count value, and outputs an “L” level control signal φX. To “H” level. At this time, the built-in clock generator (not shown) is stopped. In the present embodiment, the predetermined value is the cell array 10a divided into blocks.
It is set to the number "4" of ~ 10d.

Reference numerals 17a to 17d denote block decoders, which are sequentially activated in response to output signals φa and φb from the block counter 16, and output block selection signals φ0 to φ3 for selecting the corresponding cell array blocks 10a to 10d. . In this case, since the count value of the block counter 16 is set to “4”, each of the block decoders outputs the block selection signals φ0 to φ3 once.

18a to 18d indicate NAND gates and address buffers 15
Block selection signals BS0-B for selecting corresponding cell array blocks 10a-10d in response to two different bits of a 4-bit block selection address signal ADD1 from
Outputs S3. Reference numerals 19a to 19d denote multiplexers (MPX) which respond to a control signal φX from the block counter 16 and block selection signals BS0 to BS based on the external address ADD.
3 or one of the block selection signals φ0 to φ3 from the block decoders 17a to 17d. In this case, when the control signal φX is at “L” level, the block selection signals φ0 to φ
3 is selected, and when the control signal φX attains the “H” level, the block selection signals BS0 to BS3 are selected.

Reference numerals 20a to 20d and 21a to 21d denote clock generators, and the clock generators 20a to 20d (21a to 21d) respectively include an output of the NOR gate 12 (an output of the inverter 14) and a block selection selected by the multiplexers 19a to 19d. A memory access clock is generated in response to the signal. 22a-22d
Denotes a row decoder, and 23a to 23d denote column decoders, which select cells in response to clocks from clock generators 20a to 20d and 21a to 21d based on address information ADD2 from the address buffer 15, respectively. Reference numerals 24a to 24d denote multiplexers and sense circuits (MPX · S / A) for inputting and outputting data (D _IN / D _OUT ) with the outside.

Next, the operation of the circuit of FIG. 2 will be described with reference to the timing chart of FIG.

First, when the power is turned on, the starter 11 operates, and the output signal φs at which the power supply voltage reaches a predetermined level Vo becomes “L”.
Level and the internal circuit starts operating. That is, the block counter 16 counts the number of falling edges of the row address strobe signal RASX in response to the “L” level signal φs, and outputs the signals φa, φ based on the count value.
b is output.

The block decoders 17a to 17d are sequentially selected based on bit combinations of the output signals φa and φb, and output block selection signals φ0 to φ3. Thereby, the corresponding cell array blocks 10a to 10d are activated. In the present embodiment, the block selection signals φ0 to φ3 are output once each, so that each block
10a to 10d are also activated once.

When the last block selection signal φ3 is output, the control signal φX becomes “H” level, and the operation mode is the normal operation mode. That is, the block selection signal BS0 based on the external address ADD
~ BS3 is selected in MPX 19a ~ 19d, thereby activating each block 10a ~ 10d.

As described above, according to the configuration of the present embodiment, when the power is turned on, the external address ADD is changed to the internal address (the block selection signal φ0).
.About..phi.3), and the internal addresses are sequentially updated during a predetermined period (dummy cycle) after the power is turned on, whereby all the cell array blocks 10a to 10d are updated.
Are activated in order.

Therefore, at the time of the first memory access after the completion of the dummy cycle, it is possible to eliminate the possibility of a write / read failure as seen in the conventional type. As a result, malfunction can be prevented, and operation reliability can be improved.

In the above-described embodiment, each cell array block corresponds to one cell array block.
The activation is performed each time, but it goes without saying that the activation may be performed two or more times. This is realized by setting the count value of the block counter 16 to “5” or more.

In the above-described embodiment, the block counter 16 is provided independently, but as shown in FIG.
Since the DRAM is provided with the refresh counter 13, the refresh counter may be used for activating each cell array block.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, each of the plurality of divided cell array blocks can be activated at the time of power-on, whereby a write / read failure at the first memory access after power-on is achieved. Can be prevented from occurring. This contributes to increasing the operation reliability.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the principle of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing a configuration of an embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing a configuration of a semiconductor memory device as an example of a conventional type. (Reference Numerals) 1 ...... memory cell array, 2 _l to 2 _n ...... block activation circuit, 3 ...... block selection circuit, B _l .about.B _n ...... block, S _l to S _n ...... selection signal, Vcc ……Power-supply voltage.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/40-11/419

Claims (3)

(57) [Claims] A memory cell array divided into a plurality of blocks; a plurality of block activation circuits provided corresponding to each of the plurality of blocks to activate each of the plurality of blocks; A block selecting circuit for selecting a predetermined block activating circuit from the block activating circuit; switching means for switching between an external block selecting signal and an internal block selecting signal according to a control signal from the block selecting circuit; Wherein, during a predetermined period after power-on, the switching means selects a block selection signal from the inside, and the block selection circuit activates each of the plurality of blocks at least once. A semiconductor memory device characterized by the above-mentioned. 2. The semiconductor memory device according to claim 1, further comprising a refresh counter used only for refreshing said memory cell array. 3. The semiconductor memory according to claim 1, wherein said block selecting circuit sequentially selects said plurality of block activating circuits in response to application of a power supply voltage at power-on. apparatus.