JPH0887888A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To contrive a low dissipation of power by avoiding useless power consumption of a semiconductor memory device. CONSTITUTION: A selecting circuit 2 selects the specified memory cell of a memory cell array 1. A reading circuit 3 reads out the data of the selected memory cell. A writing circuit 4 writes the data into the selected specified memory cell. A first control circuit 5 reads the data out of the selected memory cell by controlling the reading circuit 3 in the same cycle of a clock signal and then writes the data to be read at the next time into the selected memory cell by controlling the writing circuit 4. A comparing circuit 6 compares the read-out data of the selected memory cell and the writing data. A second control circuit 7 prohibits the writing of the data to be written into the selected memory cell by nullifying the control of the writing circuit 4 with the first control circuit 5 when it is judged that the read-out data and the writing data are same from the result of the comparison with the comparing circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
More specifically, the present invention relates to a digital delay line memory for image data in which input data is delayed by a predetermined delay time and then output.

In recent years, there has been a demand for lower power consumption of semiconductor memory devices, and also for digital delay line memories.

[0003]

2. Description of the Related Art FIG. 6 shows a conventional digital delay line memory 10. Digital delay line memory 10
Includes a memory cell array 11, a column switch 12 including NMOS transistors, a write amplifier 13, a sense amplifier 14, a selection circuit 15 and a control circuit 16. In this memory 10, after data is read from the selected memory cell in one cycle of the clock signal,
Data is written in the selected memory cell.

The memory cell array 11 is connected to a selection circuit 15 for selecting a memory cell and a control circuit 16. The selection circuit 15 is the control circuit 16
It is connected to the. A write amplifier 13 and a sense amplifier 14 are connected in parallel to the memory cell array 11 via a column switch 12. The write amplifier 13 and the sense amplifier 14 are connected to the control circuit 16.

The memory cell array 11 is provided with a plurality of word lines WL extending in the horizontal direction and a plurality of pairs of bit lines extending in the vertical direction. In FIG. 6, only two word lines WL1 and WLn and a pair of bit lines BL and XBL are shown.

The memory cell array 11 includes a bit line pair BL,
Precharge circuit 17 for precharging XBL
Is provided. The precharge circuit 17 includes five NMOS transistors 18-22. Transistors 18, 19
Each drain is connected to the power source Vcc, and each source is connected to the bit lines BL and XBL. Transistor 18,
Each gate of 19 is connected to the power supply VCC, and the transistor 1
Reference numerals 8 and 19 are always turned on to precharge the pair of bit lines BL and XBL to a predetermined potential by the power supply VCC. The source and drain of the transistor 22 are bit lines BL and XBL
And the precharge signal PR from the control circuit 16 is input to the gate. Transistor 2
The drains of 0 and 21 are connected to the power supply Vcc, the sources are connected to the bit lines BL and XBL, and the precharge signal PR is input to the gates. Therefore, when the precharge signal PR is at H level, the transistors 20,
21, 22 are turned on, and the bit line pair BL, XBL is powered by the power supply V
Precharged to equal potential by CC.

A large number of memory cells 23 are connected between each word line WL1 to WLn and each bit line pair BL, XBL. The memory cell 23 includes two PMOS transistors 24 and 26 and four NMOS transistors 25 and 2.
7, 28, and 29. The transistors 24 and 25 are connected in series between the power supply Vcc and the ground GND, and the transistors 26 and 27 are connected in series between the power supply Vcc and the ground GND. The gates of the transistors 24 and 25 are connected to the drain of the transistor 27, and the gates of the transistors 26 and 27 are connected to the drain of the transistor 25. The drain of the transistor 25 is connected to the bit line BL via the transistor 28, and the drain of the transistor 27 is connected to the bit line XBL via the transistor 29.

The control circuit 16 uses the clock signal C shown in FIG.
In addition to inputting K, a write enable signal WE is input from a control device (not shown). The control circuit 16 outputs the clock signal CK to the selection circuit 15. Further, when the write enable signal WE is at L level, the control circuit 16 causes the clock signal CK in one cycle of the clock signal CK.
The H-level activation signal φ0 is output during the H-level period, and the H-level write signal WC0 is output during the L-level period of the clock signal CK. Further, when the write enable signal WE is at L level, the control circuit 16 outputs the precharge signal PR which is at H level for a certain period based on the H level pulse of the clock signal CK, as shown in FIG.

The selection circuit 15 sequentially selects the memory cells 23 by sequentially selecting the word lines WL1 to WLn of the memory cell array 11 based on the clock signal CK output from the control circuit 16.

The write amplifier 13 and the sense amplifier 14 are connected in parallel to the bit lines BL and XBL via the column switch 12. The gate of the column switch 12 is connected to the power supply VCC, so that the column switch 12 is always turned on to connect the bit lines BL and XBL to the write amplifier 13 and the sense amplifier 14.

The write amplifier 13 includes four NMOS transistors 30 to 33, an inverter 34, and two AND circuits 35 and 36. The transistors 30 and 31 are connected in series between the power source Vcc and the ground GND, and the node between the transistors 30 and 31 is connected to the bit line BL. The transistors 32 and 33 are connected in series between the power supply Vcc and the ground GND, and the node between the transistors 32 and 33 is connected to the bit line XBL. The output signal S1 of the AND circuit 35 is applied to the gates of the transistors 30 and 33, and the output signal S2 of the AND circuit 36 is applied to the gates of the transistors 31 and 32. The drain of the transistor 25 is connected to the bit line BL via the transistor 28, and the drain of the transistor 27 is connected to the bit line XBL via the transistor 29.

The write signal WC0 of the control circuit 16 is input to one input terminal of the AND circuit 35, and the inverted data of the write data WD is input to the other input terminal via the inverter 34. The write signal WC0 of the control circuit 16 is input to one input terminal of the AND circuit 36, and the write data WD is input to the other input terminal.

Therefore, when the write signal WC0 is at L level, the output signals S1 and S2 of the AND circuits 35 and 36 are both at L level, and all the transistors 30 to 33.
Is turned off and the levels of the bit lines BL and XBL are held in the original state, and the write amplifier 13 does not write data to the memory cell 23.

On the contrary, when the write signal WC0 is at the H level, the output signal S depends on the level of the write data WD.
Either one of S1 and S2 becomes H level, and the write amplifier 13 writes data to the selected memory cell 23. That is, when the write data WD is at H level, only the output signal S2 becomes H level and the transistors 30 and 33 are turned on. Bit line BL is charged to H level by being connected to power supply VCC by transistor 30, and bit line XBL is discharged to L level by being connected to ground GND by transistor 33. as a result,
The H level data WD is written to the selected memory cell 23. When the write data WD is at L level, only the output signal S1 goes to H level and the transistors 31 and 32 are turned on. Bit line BL is ground GN
When it is connected to D, it is discharged and becomes L level, and when it is connected to the power supply Vcc, it is charged and becomes H level. As a result, the L-level data WD is written in the selected memory cell 23.

The sense amplifier 14 is a bit line pair BL, XB.
It is connected to L and receives an activation signal φ0 from the control circuit 16. The sense amplifier 14 amplifies the data from the memory cell 23 selected based on the activation signal φ0 at the H level, and outputs the amplified data as read data RD.

Next, the operation of the digital delay line memory 10 configured as described above will be described with reference to FIG. When the first clock signal CK is input while the write enable signal WE is at L level, the H level precharge signal PR is output based on the H level pulse, and the bit line pair BL, XBL is Precharge circuit 17
Are precharged to an equal potential based on the power supply Vcc. For example, the word line WL1 is selected by the selection circuit 15 based on the first clock signal CK. Further, in the period when the clock signal CK is almost at the H level,
The activation signal φ0 becomes H level, and the write signal WC0
Becomes L level. As a result, the memory cell 23 connected to the word line WL1 is selected, and the data in the selected memory cell 23 is output to the bit line pair BL, XBL. The sense amplifier 14 is activated based on the H level activation signal φ0, the sense amplifier 14 amplifies the data on the bit line pair BL, XBL, and the read data R
It is output as D.

Further, the activation signal φ0 is at the L level and the write signal WC0 is at the H level during the period when the clock signal CK is at the almost L level. At this time, if the write data WD is at H level, only the output signal S2 is at H level.
It becomes a level and the NMOS transistors 30 and 33 are turned on. The bit line BL is supplied with the power source V by the transistor 30.
When it is connected to CC, it is charged and becomes H level, and when the bit line XBL is connected to the ground GND by the transistor 33, it is discharged and becomes L level. As a result, in one cycle of the clock signal CK, after the data is read from the selected memory cell 23, the H-level data WD is written to the memory cell 23. In addition, the write data WD is L
At the level, only the output signal S1 goes high and the NMOS transistors 31 and 32 are turned on. The bit line BL is discharged to the L level by being connected to the ground GND by the transistor 31, and the bit line XBL is supplied to the power source V by the transistor 32.
When it is connected to CC, it is charged and becomes H level. As a result, the L level data WD is written in the selected memory cell 23.

[0018]

However, in the digital delay line memory 10, the control circuit 16 sets the H level to the high level regardless of the read data from the selected memory cell and the data to be written in the memory cell. The write signal WC0 is output. Based on the write signal WC0, the write amplifier 13 writes data in the memory cell. Transistor 3 connected to ground GND when writing data
Either one of 1 and 33 is turned on, and the corresponding bit line BL, XBL is connected to the ground GND and discharged. As described above, in the digital delay line memory 10, since the write amplifier 13 performs the writing even when the read data from the selected memory cell and the write data to the memory cell match, wasteful power is consumed. Was consumed.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of reducing power consumption by eliminating wasteful power consumption. .

[0020]

FIG. 1 is a diagram for explaining the principle of the present invention. The memory cell array 1 includes a large number of memory cells. The selection circuit 2 is for selecting a predetermined memory cell in the memory cell array 1. The read circuit 3 is for reading data of a predetermined memory cell selected by the selection circuit 2. The writing circuit 4 is the selection circuit 2
It is for writing data in a predetermined memory cell selected by.

The first control circuit 5 controls the read circuit 3 in the same cycle of the clock signal to read data from the memory cell selected by the selection circuit 2, and then controls the write circuit 4. By doing so, the data to be read next is written into the selected memory cell.

The comparison circuit 6 is for comparing whether the read data and the write data of the memory cell selected by the selection circuit 2 match. Second
The control circuit 7 controls the write circuit 4 based on the comparison result of the comparison circuit 6 by permitting the control of the write circuit 4 by the first control circuit 5 when the read data does not match the write data. Write the write data. On the contrary, the second control circuit 7 disables the control of the write circuit 4 by the first control circuit 5 when the read data and the write data match each other, so that the write data to the selected memory cell is written. This is to prevent writing.

In the invention of claim 2, the second control circuit is
The control signal output from the first control circuit and the comparison signal output from the comparison circuit are input to control the writing circuit, and the output of the control signal to the writing circuit is controlled based on the comparison signal. It is a logic circuit for doing.

According to a third aspect of the invention, the semiconductor memory device according to the first or second aspect is characterized in that the selection circuit selects the memory cells of the memory cell array in the order of addresses. Claim 4
In the invention, the selection circuit includes a counter for counting the pulses of the clock signal, and a decoder for decoding the output of the counter into a selection signal and sequentially selecting the memory cells of the memory cell array.

[0025]

Therefore, in the present invention, the read data from the memory cell selected by the selection circuit 2 and the write data to the selected memory cell are compared by the comparison circuit 6. Based on the comparison result of the comparison circuit 6, when the read data and the write data do not match, the control of the write circuit 4 by the first control circuit 5 is permitted by the second control circuit 7, and the selected memory cell is selected. The write data is written to. Based on the comparison result of the comparison circuit 6, when the read data and the write data match, the control of the write circuit 4 by the first control circuit 5 is invalidated by the second control circuit 7, and the selected memory cell is selected. Write data is not written to. As a result, it is possible to reduce unnecessary power consumption by eliminating unnecessary power consumption of the semiconductor memory device.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
5 will be described. For convenience of explanation, the same components as those in FIG. 6 are designated by the same reference numerals, and the description thereof will be partially omitted.

FIG. 2 is a circuit diagram showing an embodiment embodied in the digital delay line memory 40 for image data. The digital delay line memory 40 includes a memory cell array 11, a column switch 12 including NMOS transistors, a write amplifier 13 as a write circuit, a sense amplifier 41 as a read circuit, a selection circuit 42, a first control circuit 43, and a comparison circuit. EOR circuit (exclusive OR circuit) 44, and an AND circuit (logical circuit) 45 as a second control circuit. In this memory 40, data is read from the selected memory cell in one cycle of the clock signal, and then the data is written to the selected memory cell.

The memory cell array 11 is connected to a selection circuit 42 for selecting a memory cell and is also connected to a first control circuit 43. The selection circuit 42 is connected to the first control circuit 43. Memory cell array 11
A write amplifier 13 and a sense amplifier 41 are connected in parallel via the column switch 12.

The memory cell array 11 is provided with a plurality of word lines WL extending in the horizontal direction and a plurality of pairs of bit lines extending in the vertical direction. Note that FIG. 2 shows only two word lines WL1 and WLn and a pair of bit lines BL and XBL. Each word line WL1 ~
A large number of memory cells 23 are connected between WLn and each bit line pair BL, XBL. Memory cell array 11
Includes a precharge circuit 17 for precharging the bit line pair BL, XBL.

The control circuit 43 includes four inverters 60,
61, 63, 64, a 2-input NAND circuit 62 and a 2-input AND circuit 65 are provided. The clock signal CK is input to one input terminal of the AND circuit 65, and the clock signal C is input to the other input terminal via the inverter 61.
A signal obtained by inverting K is input. The AND circuit 65 and the inverter 61 form a one-shot pulse generation circuit. Clock signal CK changes from L level to H
When the level changes to the level, the AND circuit 65 outputs the precharge signal PR, which is at the H level for a predetermined period, to the precharge circuit 1.
7 to control the precharge circuit 17.

A signal obtained by inverting the write enable signal WE from the control device (not shown) is input to one input terminal of the NAND circuit 62 via the inverter 60, and the clock signal CK is input to the other input terminal via the inverter 61. The inverted signal is input. An inverter 63 is connected to the output terminal of the NAND circuit 62, and the inverter 63 outputs a write signal WC1 for causing the write amplifier 13 to write. The inverter 64 is the inverter 6
3, the inverter 64 inverts the write signal WC1 and outputs an activation signal φ1 for operating the sense amplifier 41. As shown in FIGS.
When the write enable signal WE is at L level, the write signal WC1 is at L level and the activation signal φ1 is at H level while the clock signal CK is at H level. Further, when the write enable signal WE is at L level, the write signal WC is in the period when the clock signal CK is at L level.
1 becomes H level, and the activation signal φ1 becomes L level.

The selection circuit 42 includes a counter 46 and a decoder 4
7 and the memory cell 2 of the memory cell array 11
3 is sequentially selected in the order of addresses. Counter 4
Reference numeral 6 counts up the pulses of the clock signal CK and outputs the count value at that time to the decoder 47.
The carry terminal C of the counter 46 is connected to the reset terminal RST. When the count value of the counter 46 reaches a predetermined value and a carry signal is output, the counter 4
6 is reset and again counts up the pulses of the clock signal CK. The decoder 47 decodes the count value of the counter 46 into a selection signal, and the word lines WL1 to W
The memory cells 23 are selected in the address order (sequential) by sequentially selecting Ln.

The sense amplifier 41 includes three PMOS transistors 50, 52 and 55, three NMOS transistors 51, 53 and 54, and two inverters 56 and 57. The sources of the transistors 51 and 53 are connected to each other, and the sources of the transistors 51 and 53 are connected to the ground GND via the transistor 54. The drains of the transistors 51 and 53 are connected to the power supply Vcc through the transistors 50 and 52 that form the current mirror circuit. The activation signal φ1 of the first control circuit 43 is input to the gate of the transistor 54. The gates of the transistors 51 and 53 are connected to the bit lines BL and XBL. Transistor 5
1, 53 are bit line pairs B when reading data.
The potential difference between L and XBL is amplified. Inverters 56 and 57 are connected to the drain of the transistor 53, and the amplified data RD is output from the inverter 57. A transistor 55 is connected between the drain of the transistor 53 and the power supply Vcc, and the activation signal φ1 is input to the gate of the transistor 55. Therefore, the transistor 55 is turned on and the read data RD is at the H level while the activation signal φ1 is at the L level.

The write data WD is input to one input terminal of the EOR circuit 44, and the read data RD output from the sense amplifier 41 is input to the other input terminal. The EOR circuit 44 compares whether or not the read data RD of the memory cell and the write data WD of the memory cell match each other, and outputs a signal S3 indicating the comparison result to A
Output to the ND circuit 45. When the read data RD and the write data WD to the memory cell match, EO
The R circuit 44 outputs an L level signal S3. If the read data RD does not match the write data WD to the memory cell, the EOR circuit 44 outputs the H-level signal S3.
Is output.

The AND circuit 45 receives the write signal WC1.
And a signal S3, and a write signal W based on both signals
C2 is output to the write amplifier 13. If the read data RD and the write data WD of the selected memory cell do not match and the output signal S3 goes high, the AND circuit 45 outputs the write signal WC1 as the write signal WC2. Further, the read data RD and the write data WD of the selected memory cell match and the output signal S3
Becomes L level, the AND circuit 45 outputs the write signal W
L level write signal WC regardless of the level of C1
2 is output.

The write amplifier 13 includes four NMOS transistors 30 to 33, an inverter 34, and two AND circuits 35 and 36. The write signal WC2 of the AND circuit 45 is input to one input terminal of the AND circuit 35, and the data obtained by inverting the write data WD via the inverter 34 is input to the other input terminal. AN
The write signal WC2 of the AND circuit 45 is input to one input terminal of the D circuit 36, and the write data WD is input to the other input terminal.

Therefore, when the write signal WC2 is at the L level, the output signals S1 and S2 of the AND circuits 35 and 36 are both at the L level, and all the transistors 30 to 33.
Is turned off and the levels of the bit lines BL and XBL are held in the original state, and the write amplifier 13 does not write data to the memory cell 23. That is, when the read data RD and the write data WD of the selected memory cell match, the AND circuit 45 outputs the L level write signal WC2 regardless of the level of the write signal WC1. Light amplifier 1
The control of 3 is invalidated.

On the contrary, when the write signal WC2 is at H level, the output signal S depends on the level of the write data WD.
Either one of S1 and S2 becomes H level, and the write amplifier 13 writes data to the selected memory cell 23. At this time, if the write data WD is at H level, only the output signal S2 goes to H level and the transistors 30 and 33 are turned on. Bit line BL is charged to H level by being connected to power supply VCC by transistor 30, and bit line XBL is discharged to be L level by being connected to ground GND by transistor 33. as a result,
The H level data WD is written to the selected memory cell 23. When the write data WD is at L level, only the output signal S1 goes to H level and the transistors 31 and 32 are turned on. Bit line BL is ground GN
When it is connected to D, it is discharged and becomes L level, and when it is connected to the power supply Vcc, it is charged and becomes H level. As a result, the L-level data WD is written in the selected memory cell 23. That is, if the read data RD and the write data WD of the selected memory cell do not match, AN
The D circuit 45 converts the write signal WC1 into the write signal WC2.
By outputting as, the control of the write amplifier 13 by the first control circuit 43 is permitted.

Next, the operation of the digital delay line memory 40 configured as described above will be described with reference to FIGS. First, read data RD and write data WD
The operation in the case where and match will be described with reference to FIG. When the first clock signal CK is input while the write enable signal WE is at L level, the H level precharge signal PR is output based on the H level pulse, and the bit line pair BL, XBL is The precharge circuit 17 precharges the same potential based on the power supply Vcc.
The selection circuit 42 selects, for example, the word line WL1 based on the first clock signal CK. Further, the activation signal φ1 is at the H level and the write signal WC1 is at the L level during the period when the clock signal CK is at the H level. Since the write signal WC1 is at L level,
The write signal WC2 becomes L level, and the write amplifier 1
No data is written by 3.

As a result, the memory cell 23 connected to the word line WL1 is selected, and the selected memory cell 2 is selected.
The data of No. 3 is output to the bit line pair BL, XBL. At this time, the potentials on the bit line pair BL, XBL are set to H,
Let L. The transistor 54 is turned on based on the H-level activation signal φ1 to activate the sense amplifier 41,
The sense amplifier 41 amplifies the data on the bit line pair BL, XBL, and the sense amplifier 41 outputs the read data RD at the H level.

Next, when the clock signal CK becomes L level, the activation signal φ1
Becomes L level, and the write signal WC1 becomes H level. At this time, if the write data WD is at the H level, the read data RD and the write data WD match, so the output signal S3 is at the L level. for that reason,
Regardless of the level of the write signal WC1, the write signal WC2 is at L level, the output signals S1 and S2 are at L level, all the transistors 30 to 33 are turned off, and the levels of the bit lines BL and XBL are maintained in the original state. Therefore, the write amplifier 13 does not write data to the memory cell 23.

Next, the operation when the read data RD and the write data WD do not match will be described with reference to FIG. When the first clock signal CK is input while the write enable signal WE is at the L level, the H level precharge signal PR is output in the same manner as described above, and the bit line pair BL, XBL is supplied to the power supply VCC. Are precharged to the same potential. The selection circuit 42 selects, for example, the word line WL1 based on the first clock signal CK.

As a result, the memory cell 23 connected to the word line WL1 is selected, and the selected memory cell 2 is selected.
The data of No. 3 is output to the bit line pair BL, XBL. At this time, the potentials of the bit line pair BL, XBL are set to L,
H. The transistor 54 is turned on based on the H-level activation signal φ1 to activate the sense amplifier 41,
The sense amplifier 41 amplifies the data on the bit line pair BL, XBL, and the sense amplifier 41 outputs the read data RD at the L level.

Next, when the clock signal CK becomes L level, the activation signal φ1
Becomes L level, and the write signal WC1 becomes H level. At this time, if the write data WD is at the H level, the read data RD and the write data WD do not match, so the output signal S3 is at the H level. Therefore, the write signal WC1 is output as the write signal WC2. Since the write data WD is at the H level,
Only the output signal S2 becomes H level, and the NMOS transistors 30 and 33 are turned on. Bit line BL is charged to H level by being connected to power supply VCC by transistor 30, and bit line XBL is discharged to L level by being connected to ground GND by transistor 33. As a result, the H level data WD is written in the selected memory cell 23.

As described above, in this embodiment, the read data RD and the write data W of the selected memory cell 23 are written.
If D and D match, regardless of the level of the write signal WC1 of the first control circuit 43, the write signal WC
2 is set to the L level to prevent the write amplifier 13 from operating. Therefore, if the bit lines BL and XBL are not discharged and the read data RD and the write data WD match, useless power consumption can be saved and the power consumption of the digital delay line memory 40 can be reduced. You can

FIG. 5 shows a Y / C separation comb filter using the digital delay line memory 40 constructed as described above. This filter includes an A / D converter 71, a digital delay line memory 40, an adder 72 and a subtractor 73. A / D converter 71 receives the received NTSC
Converts a composite signal (analog signal) into a digital signal. The digital delay line memory 40 stores the output signal of the A / D converter 71. The adder 72 adds the output signal of the A / D converter 71 and the delayed signal read from the memory 40, and outputs a luminance signal (Y signal).
The subtractor 73 uses the output signal of the A / D converter 71 for the memory 4
The delayed signal read from 0 is subtracted to obtain the color signal (C
Signal) is output.

The present invention can be embodied by being arbitrarily modified as follows. (1) In this embodiment, the memory cells of the memory cell array 11 are embodied as the digital delay line memory 40 for accessing in the order of addresses, but the memory cells of the memory cell array may be embodied as a memory for random access.

(2) In this embodiment, one memory cell is selected by selecting one word line, but a plurality of memory cells (for example, eight) are selected by selecting one word line. It may be a memory cell array to be selected. In this case, an EOR circuit is provided for each of a plurality of selected memory cells, and instead of the AND circuit 45, a plurality of these EO circuits are provided.
A multi-input AND circuit that receives the output signal of the R circuit and the write signal WC1 of the first control circuit 43 may be provided.

[0049]

As described in detail above, according to the present invention,
It is possible to reduce wasteful power consumption and reduce power consumption.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a digital delay line memory of one embodiment.

FIG. 3 is a time chart showing the operation of one embodiment.

FIG. 4 is a time chart showing the operation of one embodiment.

FIG. 5 is a block diagram showing a Y / C separation comb filter.

FIG. 6 is a circuit diagram showing a conventional digital delay line memory.

FIG. 7 is a time chart showing the operation of the conventional example.

[Explanation of symbols]

1, 11 Memory cell array 2, 42 Selection circuit 3 Read circuit 4 Write circuit 5, 43 First control circuit 6 Comparison circuit 7 Second control circuit 13 Write amplifier as write circuit 41 Sense amplifier as read circuit 44 EOR circuit (exclusive OR circuit) as a comparison circuit 45 AND circuit as a second control circuit

Claims (4)

[Claims] 1. A memory cell array having a large number of memory cells, a selection circuit for selecting a predetermined memory cell of the memory cell array, and a read circuit for reading data of the predetermined memory cell selected by the selection circuit. A read circuit, a write circuit for writing data to a predetermined memory cell selected by the selection circuit, and a memory circuit selected by the selection circuit by controlling the read circuit in the same cycle of a clock signal. A first control circuit for causing the selected memory cell to write data to be read next by controlling the write circuit after reading the data; and the memory cell selected by the selection circuit. And a comparison circuit for comparing whether the read data and the write data of Based on the comparison result of the comparison circuit, when the read data and the write data do not match, the control of the write circuit by the first control circuit is allowed to allow the write data to be written to the selected memory cell. Writing is performed, and when the read data and the write data match, the control of the write circuit by the first control circuit is invalidated to cause the write data to be written to the selected memory cell. A semiconductor memory device including a second control circuit for disabling. 2. The second control circuit inputs a control signal output from the first control circuit and a comparison signal output from the comparison circuit to control the write circuit, 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a logic circuit for controlling the output of the control signal to the write circuit based on a comparison signal. 3. The semiconductor memory device according to claim 1, wherein the selection circuit selects the memory cells of the memory cell array in an address order. 4. The selection circuit includes a counter that counts pulses of the clock signal, and a decoder that decodes an output of the counter into a selection signal to sequentially select memory cells of the memory cell array. The semiconductor memory device according to 1.