JPH0883490A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To provide a semiconductor storage device which is capable of increasing the speed of operation while lowering the voltage. CONSTITUTION: The memory cell array 1 is provided with many memory cells 2 each composed from a static circuit. The peripheral circuit 3 selects a specified memory 2 from the memory cell array 1 and conducts reading and writing of the data of the selected memory cell. It is powered by a high-voltage source VDD and a low-voltage source VSS. Although the memory cell 2 is supplied with a high voltage VDD, it is supplied with a reference voltage Vref of which the potential is lower than a low-voltage source VSS at the time of data reading and that of data writing, of at least at the time of data reading.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
More specifically, the present invention relates to a memory cell including a large number of memory cells each including a static circuit.

In recent years, semiconductor memory devices have been required to lower the operating power supply voltage and to operate at higher speed.

[0003]

2. Description of the Related Art FIG. 4 shows a conventional static random access memory (SRAM) memory cell 10.

The memory cell 10 has two resistors R1 and R2.
And four NMOS transistors 11, 12, 13, 1
4 and. The resistor R1 and the transistor 11 are connected in series between the high power supply VDD and the low power supply VSS, and the resistor R2 and the transistor 12 are connected in series between the high power supply VDD and the low power supply VSS. High power supply VDD and low power supply VSS
Is the same as the power supplied to a peripheral circuit (not shown) that selects the memory cell 10 and reads and writes data. The gate of the transistor 11 is the transistor 1
2 and the gate of the transistor 12 is connected to the drain of the transistor 11. The drain of the transistor 11 is connected to the bit line BL0 via the transistor 13, and the drain of the transistor 12 is connected to the bit line BL0 via the transistor 14. The gates of the transistors 13 and 14 are connected to the word line WL0.

When the word line WL0 is selected at the time of reading data from the memory cell 10 configured as described above, the transistors 13 and 14 are turned on. At this time, when the potential of the node N1 is high and the potential of the node N2 is low, the transistor 11 is turned off and the transistor 12
Turns on. Therefore, the potential of the bit line BL0 does not decrease, a current flows from the bit line bar BL0 to the low power supply VSS via the transistor 12, and the potential of the bit line bar BL0 becomes the low power supply VSS. Then, the bit lines BL0 and BL
A signal of 0 is amplified by a sense amplifier (not shown),
It is output as read data.

[0006]

However, recent semiconductor memory devices are required to have a lower voltage, and the voltage of the high power supply VDD is becoming lower. Since the memory cell 10 is also supplied with the high power supply VDD and the low power supply VSS, the bit line BL0 and the bars BL0 to NM are used when reading data.
The value of the current flowing through the OS transistors 11 and 12 is small. Therefore, it takes time for the potential difference between the bit lines BL0 and BL0 to open, and the operation speed becomes slow.

The present invention has been made to solve the above problems, and its purpose is to reduce the voltage while
It is to provide a semiconductor memory device capable of increasing the read speed.

[0008]

FIG. 1 is a diagram for explaining the principle of the present invention. The memory cell array 1 includes a large number of memory cells 2 each composed of a static circuit. The peripheral circuit 3 selects a predetermined memory cell 2 in the memory cell array 1 and reads and writes data in the selected memory cell 2. A high power supply VDD and a low power supply VSS are supplied to the peripheral circuit 3 as operating power supplies. The memory cell 2 is supplied with a high power supply VDD and a reference power supply Vref having a potential lower than that of the low power supply VSS at least during data reading and writing.

[0009]

Therefore, according to the present invention, when the data is read, the memory cell 2 has the high power supply VDD and the low power supply VSS.
A reference power source Vref having a lower potential than that of the reference power source is supplied. Therefore, even if the voltage of the high power supply VDD is lowered, the current flowing in the memory cell 2 can be increased by the reference power supply Vref having a low potential, and the read speed can be increased.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied as a static random access memory (hereinafter referred to as SRAM) will be described below with reference to FIGS.

FIG. 2 shows the SRAM 20, which is a chip 20a.
An address buffer 21, a row decoder 22, a column decoder 23, a memory cell array 24, a column gate 25, a sense amplifier 26, an output circuit 27, a write amplifier 28, and an input circuit 29 are provided above. Further, a reference power supply generation circuit 30 and a switching circuit 31 are provided on the chip 20a. In this embodiment, the address buffer 2
1, a row decoder 22, a column decoder 23, a column gate 25, a sense amplifier 26, an output circuit 27, a write amplifier 28, and an input circuit 29 form a peripheral circuit.

The chip 20a has n address terminals 32 for inputting address signals AD1 to ADn, power supply terminals 33, 34, a control terminal 35 for inputting a write signal WE, and a data input terminal on the periphery of the chip 20a. It has a plurality of data terminals (not shown) for outputting.

The high power supply VDD is input to the power supply terminal 33,
The low power supply VSS is input to the power supply terminal 34. High power VDD
And the low power supply VSS are supplied to the address buffer 21, the row decoder 22, the column decoder 23, the column gate 25, the sense amplifier 26, the output circuit 27, the write amplifier 28 and the input circuit 29, and these circuits have a high power supply VDD and a low power supply. It operates based on VSS. The reference power supply generation circuit 30 inputs the high power supply VDD and the low power supply VSS, and supplies both power supplies VDD and VSS.
Reference power supply Vref having a lower potential than the low power supply VSS
Is generated, and the reference power supply Vref is supplied to the chip 20a.

The address buffer 21 is connected to n address terminals 32, receives address signals AD1 to ADn via the address terminals 32, and outputs them to the row decoder 2
2 and the column decoder 23.

The row decoder 22 decodes the input address signal into a selection signal SL and selects a predetermined word line of the memory cell array 24. The column decoder 23 decodes the input address signal into a column selection signal CL,
The selection signal CL is output to the column gate 26.

The column gate 2 is provided in the memory cell array 24.
A sense amplifier 26 is connected through the output amplifier 5, and an output circuit 27 is connected to the sense amplifier 26. The sense amplifier 26 amplifies the data on the bit line pair BL, BL and outputs the amplified signal to the output circuit 27. A write amplifier 28 is connected to the column gate 25, and an input circuit 29 is connected to the write amplifier 28. Input circuit 2
A data signal consisting of a plurality of bits (n bits in this embodiment) is input to 9 from a controller (not shown). The input circuit 29 outputs a data signal to the write amplifier 28 when writing data.

A switching circuit 31 is connected to the memory cell array 24. The switching circuit 31 inputs the low power supply VSS and the reference power supply Vref, and also supplies the row decoder 22.
The selection signal SL and the write signal WE are input. The switching circuit 31 uses the selection signal SL and the write signal WE.
Based on the above, the low-potential-side power supply supplied to the memory cells of the memory cell array 24 is switched to the low power supply VSS and the reference power supply Vref.

Next, the memory cell array 24 and the switching circuit 3
1 and the sense amplifier 26 will be described in detail with reference to FIG. The memory cell array 24 is provided with a plurality of word lines WL extending in the horizontal direction and a plurality of bit line pairs extending in the vertical direction. In addition, in FIG. 3, one word line WL
And only a pair of bit lines BL and BL are shown. A memory cell 40 is connected between each word line and each bit line pair.

The memory cell 40 has two resistors R3 and R4.
And four NMOS transistors 41, 42, 43, 4
4 and. The resistor R3 and the transistor 41 are connected in series between the high power supply VDD and the switching circuit 31, and the resistor R4 and the transistor 42 are connected in series between the high power supply VDD and the switching circuit 31. The gate of the transistor 41 is connected to the drain of the transistor 42, and
The gate of 2 is connected to the drain of the transistor 41. The drain of the transistor 41 is the transistor 43
To the bit line BL, and the drain of the transistor 42 is connected to the bit line bar BL via the transistor 44.
It is connected to the. The gates of the transistors 43 and 44 are connected to the word line WL. The memory cell 40 has the node N when the transistors 43 and 44 are off.
This is a static circuit that holds the potentials of N3 and N4.

The switching circuit 31 is provided for each word line of the memory cell array 24, and has a 2-input NAND circuit 50, inverters 51 and 52, and two NMOS transistors 53 and 53.
54 is provided. The transistor 53 is the memory cell 40.
Of the transistors 41 and 42 and the reference power source Vref. The transistor 54 is the transistor 41,
It is connected between 42 and the low power supply VSS. The gate of the transistor 53 is connected to the NAND circuit 50 via the inverter 51. The gate of the transistor 54 is connected to the NAND circuit 50 via the inverters 52 and 51. The NAND circuit 50 receives the selection signal SL and the write signal WE and outputs a signal based on both signals SL and WE. Data can be written in the memory cell when the write signal WE is at L level, and data in the memory cell can be read when the write signal WE is at H level.

Therefore, when writing the data in which the write signal WE is at the L level, regardless of the selection signal SL,
The output signal of the NAND circuit 50 becomes H level. As a result, the transistor 53 is turned off, the transistor 54 is turned on, and the low power supply VSS is supplied to the memory cell 40. Further, when the selection signal SL becomes H level at the time of reading the data in which the write signal WE is H level, the output signal of the NAND circuit 50 becomes L level. As a result, the transistor 53 is turned on, the transistor 54 is turned off, and the reference power supply Vref is supplied to the memory cell 40.

The bit line pair BL and bar BL are connected to a sense amplifier 26 via a column gate 25.
A column selection signal CL from the column decoder 23 is input to the column gate 25. When the column selection signal CL becomes H level, the column gate 25 is turned on, and the data of the bit line pair BL and bar BL is transferred to the sense amplifier 26.

The sense amplifier 26 includes two PMOS transistors 57, 58, three NMOS transistors 59,
60 and 61 are provided. The sources of the transistors 59 and 60 are connected to each other, and both transistors 59 and 6 are connected.
The source of 0 is connected to the low power supply VSS via the transistor 61. The drains of the transistors 59 and 60 are connected to the high power supply VDD through the transistors 57 and 58 which form a current mirror circuit. Transistor 61
An activation signal φ1 is input to the gate of the. The gates of the transistors 59, 60 are connected to the bit lines BL, BL. When reading data,
When the activation signal φ1 goes high, the transistor 61 is turned on, and the transistors 59 and 60 amplify the potential difference between the bit line pair BL and bar BL. The amplified signal VOUT is output from the drain of the transistor 60.

Now, the SRAM 2 configured as described above
The operation of 0 will be described. To read data from the memory cell array 24, address signals AD1 to ADn are used.
And a write signal WE of H level are supplied to the chip 20a. The address signals AD1 to ADn are used for the row decoder 2
2 and the column decoder 23 select signals SL, CL
Is decoded into. At this time, since the write signal WE is at the H level, the transistor 53 of the switching circuit 31 is turned on, and the reference power supply Vref is supplied to the memory cell 40 as the power supply on the low potential side.

The word line WL is selected based on the selection signal SL, and the bit line pair B is selected by the selection signal CL.
When L and bar BL are selected, the transistors 43 and 44 of the memory cell 40 are turned on. At this time, when the potential of the node N3 is high and the potential of the node N4 is low, the transistor 41 is turned off and the transistor 42 is turned on. Therefore, the potential of the bit line BL does not decrease, and the bit line bar BL
Current flows through the transistor 42 to the reference power supply Vref. Since the reference power supply Vref has a lower potential than the low power supply VSS, the current flowing through the transistor 42 increases and the potential of the bit line bar BL drops at high speed.

Data on the bit lines BL and BL are transferred to the sense amplifier 26 via the column gate 25. Then, the sense amplifier 26 amplifies the data on the bit line pair BL, BL and the amplified signal VOUT is output to the output circuit 27.

To write data in the memory cell array 24, the address signals AD1 to ADn and the L-level write signal WE are supplied to the chip 20a. The address signals AD1 to ADn are decoded into selection signals SL and CL by the row decoder 22 and the column decoder 23.
At this time, since the write signal WE is at the L level, the transistor 54 of the switching circuit 31 is turned on, and the memory cell 4
A low power supply VSS is supplied to 0 as a power supply on the low potential side.

The word line WL is selected based on the selection signal SL, and the bit line pair B is selected by the selection signal CL.
When L and bar BL are selected, the transistors 43 and 44 of the memory cell 40 are turned on. At this time, the bit line BL
Is high and the potential of the bit line bar BL is low, the transistor 41 is turned off and the transistor 42 is turned on.
Therefore, the potential of the node N3 becomes high and the potential of the node N4 becomes low. When the selection signal SL is not output and the word line WL is not selected, the transistors 43,
44 is turned off, and data is written in the memory cell 40.

As described above, in this embodiment, the memory cell 4
The low-potential-side power supply to supply 0 to the low power supply VSS and the low power supply V
A switching circuit 31 for switching to the reference power supply Vref having a lower potential than SS is provided. The memory cell 40 has a high power supply V
In addition to supplying DD, the reference power supply Vref was supplied by the switching circuit 31 when reading data, and the low power supply VSS was supplied by the switching circuit 31 when writing data. Therefore, even if the voltage of the high power supply VDD is lowered, the current flowing through the memory cell 40 increases due to the reference power supply Vref having a low potential. As a result, the potential difference between the bit lines BL and BL can be opened faster, and the read speed can be increased.
Therefore, it is possible to reduce the voltage of the high power supply VDD.

Further, in this embodiment, the reference power supply Vref of the reference voltage generation circuit 30 for supplying the back gate voltage to the chip 20a is supplied as the power supply on the low potential side of the memory cell 40 at the time of data reading. . Therefore, it is not necessary to provide a dedicated power supply circuit for the power supply to the memory cell array 24, and the SRAM 20 can be prevented from increasing in size.

Further, at the time of reading data, the memory cell 4
The current flowing through 0 can be made extremely small as compared with the current consumption of peripheral circuits such as the sense amplifier 26 and the write amplifier 28 by dividing the memory cells in block units selected by the switching circuit 31. Therefore, at the time of reading data, the reference power source Vre having a lower potential than the low power source VSS
Even if f is supplied to the memory cell 40, an increase in power consumption can be suppressed.

The present invention can be embodied by being arbitrarily modified as follows. (1) The reference power supply Vref may be supplied from outside the chip. (2) The selection signal CL of the column decoder 23 and the write signal WE are input to the switching circuit, and the low-potential-side power supply to the memory cell based on both signals CL and WE is set to the low power supply VSS.
May be switched to the reference power source Vref.

(3) The selection signal SL of the row decoder 22, the selection signal CL of the column decoder 23 and the write signal WE are input to the switching circuit, and these signals SL, CL and WE are input.
The low-potential-side power supply supplied to the memory cell may be switched between the low power supply VSS and the reference power supply Vref based on the above.

(4) The switching circuit may be omitted and the reference power supply Vref may be supplied as the power supply on the low potential side of the memory cell. (5) PMO in place of the resistors R3 and R4 of the memory cell 40
SRAM with memory cell using S-transistor
You can also carry out.

[0035]

As described in detail above, according to the present invention,
There is an excellent effect that the operation speed can be increased while lowering the voltage of the semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a semiconductor memory device of one embodiment.

FIG. 3 is a circuit diagram showing a memory cell array, a switching circuit, and a sense amplifier.

FIG. 4 is a circuit diagram showing a conventional memory cell.

[Explanation of symbols]

 1, 24 Memory cell array 2, 40 Memory cell 3 Peripheral circuit 30 Reference power supply generation circuit 31 Switching circuit VDD High power supply Vref Reference power supply VSS Low power supply

Claims (3)

[Claims] 1. A memory cell array having a large number of memory cells each comprising a static circuit, and a peripheral circuit for selecting a predetermined memory cell of the memory cell array and reading and writing data from the selected memory cell. In the semiconductor memory device including, a high power supply and a low power supply are supplied to the peripheral circuit as operation power supplies, the high power supply is supplied to the memory cells, and at least a data read operation or a data write operation is performed. A semiconductor memory device adapted to supply a reference power supply having a lower potential than the low power supply at the time of reading. 2. A switching circuit for switching the power supply to the memory cell to the low power supply when writing data, and to the reference power supply to the memory cell when reading the data. The semiconductor memory device described. 3. The semiconductor memory device according to claim 1, further comprising a reference power supply generation circuit that generates the reference power supply based on the high power supply and the low power supply.