JP2002042476A - Static semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a static semiconductor memory in which a write-in margin can be taken. SOLUTION: The static semiconductor memory is provided with a voltage supply circuit 72. An internal power source line 6 is connected to a memory cell. An external power source line 5 is connected to a power source node 722 and external power source voltage is supplied to the power source node 72. An internal write-in signal WEi of a H level is inputted to the voltage supply circuit 72 at the time of write-in of data, voltage VCC-VTH is supplied to a memory cell by a N channel MOS transistor 721. Also, an internal write-in signal WEi of a L level is inputted to the voltage supply circuit 72 at the time of read-out of data, and voltage VCC is supplied to a memory cell by a P channel MOS transistor 720.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a static semiconductor memory device, and more particularly, to a static semiconductor memory device having a large write margin.

[0002]

2. Description of the Related Art Conventionally, low power consumption SRAM (Static)
In the Random Access Memory, a high resistance load type memory cell 1 as shown in FIG.
20 were used. High resistance load type memory cell 12
0 includes resistors 2a, 2b and channel MOS transistors 3a, 3b, 4a, 4b. Resistance 2a is connected in series with N-channel MOS transistor 4a. Resistance 2b is connected in series with N-channel MOS transistor 4b. An external power supply voltage is supplied from power supply node 1 to resistors 2a and 2b. The drain terminals of N channel MOS transistors 4a and 4b are connected to ground node 8. N-channel MOS transistor 3a is arranged between node N1, which is a connection point between resistor 2a and N-channel MOS transistor 4a, and bit line BL. Also, N
The channel MOS transistor 3b is connected to a node N which is a connection point between the resistor 2b and the N-channel MOS transistor 4b.
2 and bit line / BL.

[0003] N-channel MOS transistors 3a, 3b
Is connected to a word line W. Node N1 is connected to the gate terminal of N-channel MOS transistor 4b, and node N2 is connected to the gate terminal of N-channel MOS transistor 4a. Resistance 2a, 2
b is a high resistance of 1 TΩ or more.

At the time of reading data from memory cell 120, N-channel MOS transistors 3a and 3b are turned on, and a column current flows into a low potential side storage node.
That is, it is the same as when a low-impedance load is connected in parallel to the resistors 2a and 2b as load elements, and it is the same as the absence of the resistors 2a and 2b as high-impedance load elements. Therefore, it is necessary to treat N-channel MOS transistors 3a and 3b as loads. As a result, N channel MOS transistors 3a and 4a and N channel MOS transistors 3b and 4b
The inverter characteristics shown in FIG.

A curve k1 shows the inverter characteristics of the N-channel MOS transistors 3a and 4a, and a curve k2 shows the N-channel MOS transistors 3a and 4a.
6 shows inverter characteristics of the channel MOS transistors 3b and 4b. The relationship between the curves k1 and k2 is a relationship in which one of the curves is symmetrically moved with respect to a line having an inclination of 45 degrees.
Then, a curve k1, which is generally called a "cell eye",
A region surrounded by k2 is formed. Curve k1 and curve k2
Is a distance L from the static noise margin SNM (S
This is called “static noise margin”, and indicates that the larger the static noise margin SNM, the more stable the characteristics.

The points S1 and S2 are stable points, and the stable points S
1 indicates data “0”, and stable point S2 indicates data “1”. To increase the static noise margin SNM, the N-channel MOS transistor 3a (or 3
b) Drain current and N-channel MOS transistor 4
The ratio of a (or 4b) to the drain current (referred to as “β ratio”) is increased. Then, the curve k3 in FIG.
As indicated by the dotted line, the static noise margin SN
M increases. To increase the β ratio, N channel M
The length of the N-channel MOS transistor 3a (or 3b) is made longer than that of the OS transistor 4a (or 4b), and the N-channel MOS transistor 3a (or 3b)
N channel MOS transistor 4a (or 4
It is conceivable to increase the width of b), but this increases the area of the memory cell.

[0007] Therefore, as shown in FIG.
Between the resistor and the N-channel MOS transistor 3a.
By inserting a resistor R2 between the node N2 and the N-channel MOS transistor 3b, respectively.
The ratio has been increased.

However, even if the β ratio is increased by such a method, the lower limit of the operating voltage of the memory cell is 2.4 to
It is about 2.5 V, and could not cope with recent low-voltage operation (about 2 V).

For this reason, the full CMO shown in FIG.
The S-type memory cell 121 has been used. The memory cell 121 uses the resistances 2a and 2b of the high resistance load type memory cell 120 as P channel MOS transistors 7a and
7b. The inverter characteristics of the memory cell 121 also depend on the N-channel MOS transistor 3a (or 3b) and the N-channel MOS transistor 4a (or 4
b) In the case of the full CMOS type memory cell 121, since the P-channel MOS transistors 7a and 7b are used as loads, the N-channel M
OS transistor 3a (or 3b) and N-channel MO
It is necessary to take into consideration the load of the P-channel MOS transistors 7a and 7b in the inverter characteristics with the S transistor 4a (or 4b). As a result, as shown in FIG. 24, the P-channel MOS transistors 7a and 7b are added as loads, so that the inverter characteristics start from the external power supply voltage Vcc. On the other hand, the N-channel MO
S transistor 3a (or 3b) and N-channel MOS
The inverter characteristic with the transistor 4a (or 4b) starts from Vcc-Vth (Vth: threshold value of the N-channel MOS transistor 3a or 3b).

[0010] Inverter characteristics include an N-channel MOS transistor 3a (or 3b) and an N-channel M transistor.
In the case of the OS transistor 4a (or 4b), which is determined by the threshold value of the N-channel MOS transistor 4a (or 4b), when the P-channel MOS transistors 7a and 7b are added as loads,
The overhang is determined by the competition between the loads of the P-channel MOS transistors 7a and 7b and the threshold value of the N-channel MOS transistor 4a (or 4b).

Due to these differences, in the case of the full CMOS type memory cell 121, the static noise margin SNM becomes larger than that of the high resistance load type memory cell 120 without increasing the β ratio.

Also, a full CMOS type memory cell 121 is provided.
Also, as shown in FIG. 25, a resistor R1 is inserted between node N1 and N-channel MOS transistor 3a, and a resistor R2 is inserted between node N2 and N-channel MOS transistor 3b to increase the β ratio. In this case, the static noise margin SNM can be further increased as shown by the dotted line in FIG. As a result, the lower limit of the operating voltage increases.

[0013]

SUMMARY OF THE INVENTION As described above, the full CMO
In the S-type memory cell 121, the static noise margin SNM increases and the operation margin increases, but the write margin decreases. Ease of writing means static noise margin SN
This means that M is small, and particularly at a relatively high voltage of 2.5 V or more, there is a problem that writing cannot be performed unless a sufficient writing margin is taken.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a static semiconductor memory device capable of providing a write margin in a memory cell having a large static noise margin SNM. To provide.

[0015]

The static semiconductor memory device according to the present invention has a first inverter characteristic having a first static noise margin or a second static noise margin larger than the first static noise margin. A plurality of memory cells driven according to the second inverter characteristic and, when data is written to each of the plurality of memory cells, each of the plurality of memory cells is driven according to the first inverter characteristic and each of the plurality of memory cells And a driving circuit for driving each of the plurality of memory cells in accordance with the second inverter characteristic when reading data from the memory cell, wherein each of the plurality of memory cells includes a first driving transistor of a first conductivity type and a first driving transistor. A first inverter comprising a first load transistor of a second conductivity type and a first conductivity type A flip-flop circuit having a second inverter including a second driving transistor and a second load transistor of a second conductivity type, and a first conductivity type first flip-flop circuit connected to an output node of the first inverter; 1
And an access transistor of the first conductivity type connected to the output node of the second inverter.

In the static semiconductor memory device according to the present invention, each of a plurality of memory cells is driven according to a first inverter characteristic having a small static noise margin when data is written, and when data is read. It is driven according to a second inverter characteristic having a large static noise margin.
Therefore, according to the present invention, when reading data,
The memory cell can be driven according to more stable characteristics, and at the time of data writing, the memory cell can be driven according to a characteristic having a large write margin.

Preferably, the drive circuit of the static semiconductor memory device, when writing data into each of the plurality of memory cells, applies a first voltage for driving according to a first inverter characteristic to each of the plurality of memory cells. And when reading data from each of the plurality of memory cells, a second voltage for driving according to the second inverter characteristic is supplied to each of the plurality of memory cells.

The drive circuit supplies a first voltage to each memory cell when writing data to each memory cell, and supplies a second voltage to each memory cell when reading data from each memory cell. Then, at the time of data writing, each memory cell has a first static noise margin having a small static noise margin.
And at the time of data reading, in accordance with the second inverter characteristic having a large static noise margin.

Therefore, according to the present invention, by changing the voltage supplied to each memory cell, the memory cell can be driven in accordance with more stable characteristics when reading data, and the write margin can be increased when writing data. A memory cell can be driven according to large characteristics.

Preferably, the drive circuit of the static semiconductor memory device supplies the first and second voltages to the high voltage nodes of each memory cell.

The drive circuit supplies a first voltage to a high voltage node of each memory cell when writing data to each memory cell, and supplies a high voltage node of each memory cell when reading data from each memory cell. Is supplied with a second voltage. Then, when the first voltage is supplied, each memory cell is driven according to the inverter characteristic having a small static noise margin, and when the second voltage is supplied, each memory cell is driven according to the inverter characteristic having a large static noise margin.

Therefore, according to the present invention, by changing the voltage supplied to the high voltage node of each memory cell, the memory cell can be driven according to more stable characteristics at the time of data reading, and at the time of data writing. In addition, the memory cell can be driven according to the characteristic that the write margin is large.

Preferably, the drive circuit of the static semiconductor memory device generates a first activation signal in response to the activation of the write signal, and generates a second activation signal in response to the inactivation of the write signal.
An activation signal generating circuit for generating an activation signal of the type described above, and, when writing data to each of the plurality of memory cells, supplying a first voltage to each of the plurality of memory cells based on the first activation signal. And a voltage supply circuit for supplying a second voltage to each of the plurality of memory cells based on a second activation signal when data is read from each of the plurality of memory cells. An external power supply line to which a power supply voltage is supplied,
An internal power supply line connected to a high voltage node of each of the plurality of memory cells; and an internal power supply line connected between the external power supply line and the internal power supply line, receiving a first activation signal and applying a first voltage to the internal power supply line. A first voltage supply transistor of the first conductivity type to be supplied to the first power supply transistor, and a first voltage supply transistor connected between the external power supply line and the internal power supply line in parallel to receive the second activation signal A second voltage supply transistor of a second conductivity type for supplying a second voltage to the internal power supply line.

When data is written in each memory cell, the first voltage supply transistor generates a first voltage based on an external power supply voltage by a first activation signal generated in response to activation of a write signal. Supply to internal power line. When data is read from each memory cell, the second activation signal generated along with the inactivation of the write signal causes the second activation signal to be generated.
Supplies the second voltage to the internal power supply line based on the external power supply voltage.

Therefore, according to the present invention, the first voltage and the second voltage are selectively supplied to the high voltage node of each memory cell by selectively activating two transistors having different conductivity types. it can. As a result, at the time of data reading, the memory cell can be driven according to more stable characteristics, and at the time of data writing, the memory cell can be driven according to a characteristic having a large write margin.

Preferably, the drive circuit of the static semiconductor memory device supplies the first and second voltages to the low voltage nodes of each memory cell.

The drive circuit supplies a first voltage to a low voltage node of each memory cell when writing data into each memory cell, and supplies a low voltage node to each memory cell when reading data from each memory cell. Is supplied with a second voltage. Then, when the first voltage is supplied, each memory cell is driven according to the inverter characteristic having a small static noise margin, and when the second voltage is supplied, each memory cell is driven according to the inverter characteristic having a large static noise margin.

Therefore, according to the present invention, by changing the voltage supplied to the low voltage node of each memory cell, the memory cell can be driven according to more stable characteristics at the time of data reading, and at the time of data writing. In addition, the memory cell can be driven according to the characteristic that the write margin is large.

Preferably, the drive circuit of the static semiconductor memory device generates a first activation signal when the write signal is activated, and generates a second activation signal when the write signal is deactivated.
An activation signal generating circuit for generating an activation signal of the type described above, and, when writing data to each of the plurality of memory cells, supplying a first voltage to each of the plurality of memory cells based on the first activation signal. And a voltage supply circuit for supplying a second voltage to each of the plurality of memory cells based on a second activation signal when data is read from each of the plurality of memory cells. A ground node to which a voltage is supplied, an internal power supply line connected to each low voltage node of the plurality of memory cells, and a first activation signal connected between the ground node and the internal power supply line A third voltage supply transistor of a second conductivity type for supplying a first voltage to the internal power supply line;
A fourth transistor of the first conductivity type, connected in parallel with the third voltage supply transistor between the ground node and the internal power supply line, receiving the second activation signal and supplying the second voltage to the internal power supply line Voltage supply transistor.

When writing data into each memory cell, the third voltage supply transistor internally supplies the first voltage based on the ground voltage by the first activation signal generated in response to the activation of the write signal. Supply to power line. Further, when reading data from each memory cell, the fourth voltage supply transistor internally supplies the second voltage based on the ground voltage by the second activation signal generated in accordance with the inactivation of the write signal. Supply to power line. In this case, the transistor that supplies the first voltage to the internal power supply line and the transistor that supplies the second voltage to the internal power supply line supply the first and second voltages to the high voltage node of each memory cell. This is a transistor of the opposite conductivity type to that in the case of FIG.

Therefore, according to the present invention, the first voltage and the second voltage are selectively supplied to the low voltage node of each memory cell by selectively activating two transistors having different conductivity types. it can. As a result, at the time of data reading, the memory cell can be driven according to more stable characteristics, and at the time of data writing, the memory cell can be driven according to a characteristic having a large write margin.

Preferably, when writing data to each of the plurality of memory cells, the drive circuit of the static semiconductor memory device applies a first load for driving the load of each memory cell in accordance with the first inverter characteristic. When setting and reading data from each of the plurality of memory cells, the load of each memory cell is set to a second load for driving according to the second inverter characteristic.

When writing data into each memory cell, the drive circuit connects a large load in series with each memory cell and operates each memory cell according to the first inverter characteristic having a small static noise margin. When reading data from each memory cell, the drive circuit connects a small load in series with each memory cell and operates each memory cell in accordance with the second inverter characteristic having a large static noise margin.

Therefore, according to the present invention, by changing the load connected in series with each memory cell, each memory cell can be changed according to the first inverter characteristic having a small static noise margin or the second inverter characteristic having a large static noise margin. Can be operated. As a result, at the time of data reading, the memory cell can be driven according to more stable characteristics, and at the time of data writing, the memory cell can be driven according to a characteristic having a large write margin.

Preferably, the drive circuit of the static type semiconductor memory device generates an activation signal in accordance with activation of the write signal, and generates an inactivation signal in accordance with inactivation of the write signal. And when writing data to each of the plurality of memory cells, supplying a second voltage based on the inactivation signal to set the load of each memory cell to the first load, When reading data from
A voltage supply circuit for supplying a second voltage based on the activation signal to set the load of each memory cell to the second load.

The drive circuit changes the load of each memory cell to a first load and a second load by using an activation signal / inactivation signal generated in synchronization with activation / inactivation of the write signal. Set to. In this case, the same second voltage is supplied to each memory cell.

Therefore, according to the present invention, each memory cell can be driven in accordance with the first inverter characteristic having a small static noise margin when writing data, and in accordance with the second inverter characteristic having a large static noise margin in reading data. Each memory cell can be driven.

Further, according to the present invention, it is possible to switch the inverter characteristics of each memory cell by supplying the same voltage and changing the load.

Preferably, the voltage supply circuit included in the drive circuit of the static type semiconductor memory device includes an external power supply line to which an external power supply voltage is supplied, and an internal power supply connected to each high voltage node of the plurality of memory cells. And a second voltage connected between the external power supply line and the internal power supply line, for receiving the activation signal, supplying a second voltage to the internal power supply line, and setting the load of each memory cell to the second load. And a voltage supply transistor connected between the external power supply line and the internal power supply line in parallel with the voltage supply transistor of the conduction type. And a resistor for supplying a second voltage to the power supply line and setting the load of each memory cell to the first load.

In the voltage supply circuit, when the voltage supply transistor is activated by the activation signal, the load of each memory cell is set to the second load having a large static noise margin, and the voltage supply is performed by the inactivation signal. When the use transistor is inactivated, the load of each memory cell is set to the first load having a small static noise margin.

Therefore, according to the present invention, the inverter characteristics of each memory cell can be switched by selectively activating the voltage supply transistor.

Preferably, the drive circuit of the static semiconductor memory device generates a first activation signal when the write signal is activated, and generates a second activation signal when the write signal is deactivated.
And an activation signal generating circuit for generating an activation signal for each of the plurality of memory cells. When writing data to each of the plurality of memory cells, a second voltage is supplied based on the first activation signal to reduce the load on each memory cell. When the first load is set and data is read from each of the plurality of memory cells, the second load is set based on the second activation signal.
And a voltage supply circuit for setting the load of each memory cell to the second load.

The drive circuit applies a first activation signal / second activation signal generated in synchronization with activation / inactivation of the write signal to respectively load each memory cell into the first activation signal / second activation signal.
And the second load. In this case, the same second voltage is supplied to each memory cell.

Therefore, according to the present invention, each memory cell can be driven in accordance with the first inverter characteristic having a small static noise margin by the first activation signal, and the second activation signal has a large static noise margin by the second activation signal. Each memory cell can be driven in accordance with the inverter characteristic of (1).

Further, according to the present invention, it is possible to switch the inverter characteristics of each memory cell by supplying the same voltage and changing the load.

Preferably, the voltage supply circuit included in the drive circuit of the static semiconductor memory device includes an external power supply line to which an external power supply voltage is supplied, and an internal power supply connected to each high voltage node of the plurality of memory cells. Connected between the external power supply line and the internal power supply line, receiving the first activation signal, supplying a second voltage to the internal power supply line, and setting the load of each memory cell to the first load A second conductive type thin film transistor, and a thin film transistor connected in parallel between the external power supply line and the internal power supply line, and receiving a second activation signal to supply a second voltage to the internal power supply line; Cell load to 2nd
And a second conductivity type voltage supply transistor set to a load of

In the voltage supply circuit, the load of each memory cell is switched to the first load or the second load by selectively activating the thin film transistor and the voltage supply transistor. Then, each memory cell is driven according to the first inverter characteristic or the second inverter characteristic.

Therefore, according to the present invention, the inverter characteristics of the memory cell can be switched by using the thin film transistor as a load for changing the load of the memory cell.

Further, the static semiconductor memory device according to the present invention has a first inverter characteristic having a first static noise margin or a second inverter having a second static noise margin larger than the first static noise margin. A plurality of memory cells driven in accordance with the characteristics, and when writing data to each of the plurality of memory cells, a first memory cell is supplied according to the supplied external power supply voltage.
And a driving circuit for driving each of the plurality of memory cells according to the inverter characteristic or the second inverter characteristic, wherein each of the plurality of memory cells includes a first driving transistor of the first conductivity type and a second conductive transistor. Inverter having a first load transistor of a first conductivity type and a second inverter having a second drive transistor of a first conductivity type and a second load transistor of a second conductivity type A circuit, a first access transistor of a first conductivity type connected to an output node of the first inverter, and a second access transistor of a first conductivity type connected to an output node of the second inverter; including.

In the static semiconductor memory device according to the present invention, when a low external power supply voltage is supplied to each memory cell, each memory cell is driven according to an inverter characteristic having a large static noise margin, and a high external power supply voltage is driven. Then, each memory cell is driven according to the inverter characteristic having a small static noise margin.

Therefore, according to the present invention, the static noise margin is large in the region where the external power supply voltage is low, so that data is not lost from the memory cell and data can be written easily. Further, in a region where the external power supply voltage is high, the static noise margin becomes small, so that a sufficient write margin is provided, and loss of data from the memory cell can be prevented.

Preferably, the drive circuit of the static semiconductor memory device has an inverter characteristic between the first drive transistor and the first access transistor or an inverter characteristic between the second drive transistor and the second access transistor. When an external power supply voltage higher than the lower limit voltage at which the power supply disappears is supplied, each of the plurality of memory cells
And when an external power supply voltage equal to or lower than the lower limit voltage is supplied, each of the plurality of memory cells is driven according to the second inverter characteristic.

Based on the lower limit voltage at which the inverter characteristics of two transistors of the same conductivity type disappear, in the region where the external power supply voltage is lower than the lower limit voltage, each memory cell is driven in accordance with the inverter characteristics having a large static noise margin. In a region where the voltage is higher than the lower limit voltage, each memory cell is driven according to the inverter characteristic having a small static noise margin.

Therefore, according to the present invention, data writing and reading can be performed stably even when the operating voltage of the memory cell shifts in both directions with the lower limit voltage therebetween.

Preferably, the drive circuit of the static type semiconductor memory device, when an external power supply voltage higher than the lower limit voltage is supplied along with activation of the write signal, causes each of the plurality of memory cells to be connected to the first inverter. Outputting a first voltage for driving according to the characteristic, and outputting a second voltage for operating each of the plurality of memory cells according to the second inverter characteristic when an external power supply voltage equal to or lower than the lower limit voltage is supplied; External power supply voltage control circuit.

When the write signal is activated, the external power supply voltage control circuit of the drive circuit outputs a different voltage to each memory cell according to the supplied external power supply voltage. That is, the external power supply voltage control circuit outputs the first voltage to each memory cell when the external power supply voltage higher than the lower limit voltage is supplied, and outputs the second voltage when the external power supply voltage equal to or lower than the lower limit voltage is supplied.
Is output to each memory cell. Then, each memory cell is driven according to the first inverter characteristic having a small static noise margin when the first voltage is supplied, and according to the second inverter characteristic having a large static noise margin when the second voltage is supplied. Driven. Also, when an external power supply voltage equal to or lower than the lower limit voltage is supplied, the inverter characteristics of the two transistors of the first conductivity type disappear, but the first driving transistor of the first conductivity type and the second driving type are not. The inverter characteristic of the first load transistor or the inverter characteristic of the first conductive type second driving transistor and the second conductive type second load transistor does not disappear.

Therefore, according to the present invention, data can be read and written stably even when the external power supply voltage decreases and the operating voltage decreases.

Preferably, the drive circuit of the static semiconductor memory device drives each of the plurality of memory cells according to the first inverter characteristic during a period shorter than a period during which the write signal is activated.

The drive circuit drives each memory cell according to the first inverter characteristic having a small static noise margin during a period shorter than the period during which the write signal is activated.

Therefore, according to the present invention, a low power consumption static semiconductor memory device having a large write margin can be realized.

Preferably, the drive circuit of the static semiconductor memory device drives each of the plurality of memory cells according to the first inverter characteristic only during a period in which data is written to the memory cells in response to activation of the write signal. .

The drive circuit drives each memory cell according to the first inverter characteristic having a small static noise margin only during a period in which a data write operation is actually performed, which is shorter than a period during which a write signal is activated.

Therefore, according to the present invention, a static semiconductor memory device having a large write margin and lower power consumption can be realized.

Preferably, a plurality of memory cells of the static semiconductor memory device are divided into a plurality of blocks, and a driving circuit is provided corresponding to the plurality of blocks.

The plurality of memory cells are divided into a plurality of blocks, and a driving circuit is provided corresponding to each of the divided blocks. Each drive circuit operates a plurality of memory cells included in the corresponding block according to the first inverter characteristic when writing data, and according to the second inverter characteristic when reading data.

Therefore, according to the present invention, data can be read for each block and data with a large margin can be written.

Preferably, the drive circuit of the static semiconductor memory device supplies the first voltage to a plurality of memory cells included in the corresponding block in response to activation of a block selection signal for selecting the corresponding block.

Each drive circuit provided corresponding to each block supplies a first voltage to the block when the corresponding block is selected, and a plurality of memory cells included in the block are supplied to the first circuit. Drive according to inverter characteristics.

Therefore, according to the present invention, at the time of writing data, a plurality of memory cells included in each block can be accurately driven according to the first inverter characteristic.

[0070]

Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] Referring to FIG. 1, a static semiconductor memory device 100 according to a first embodiment of the present invention includes an external power supply line 5, an internal power supply line 6, a row address buffer 10, Column address buffer 20, row address decoder 30, column address decoder 40, read / write buffer 50, word line driver 60, drive circuit 70, write driver 80, sense amplifier 90
, Column selection switch 110, and memory cells 121 to 12
4, an input / output buffer 130, and P-channel MOS transistors 141 to 144. The driving circuit 7
0 includes an inverter 71 and a voltage supply circuit 72.

The external power supply line 5 supplies the external power supply voltage input from the input / output terminal to the voltage supply circuit 72 of the drive circuit 70. Internal power supply line 6 supplies the voltage output from voltage supply circuit 72 to memory cells 121-124.

The row address buffer 10 converts a row address signal input from an input / output terminal into a row address decoder 30.
Output to The column address buffer 20 converts a column address signal input from an input / output terminal into a column address decoder 40.
Output to

The row address decoder 30 decodes the input row address signal and outputs it to the word line driver 60. The column address decoder 40 decodes the input column address signal and outputs it to the column selection switch 110.

The read / write buffer 50 receives the read / write control signal input from the input / output terminal to drive the inverter 71 of the drive circuit 70, the write driver 80, and the sense amplifier 9
Output to 0.

The word line driver 60 sets the word line of the row corresponding to the row address from the row address decoder 30 to H.
Raise to the level. Inverter 71 outputs an internal write signal WEi obtained by inverting L-level read / write control signal / WE to voltage supply circuit 72 when writing data. Voltage supply circuit 72 outputs a different voltage to internal power supply line 6 based on internal write signal WEi by a method described later.

Write driver 80 is activated by an L (logic low) level read / write control signal from read / write buffer 50, and a pair of bit lines BL1, / BL1 connected by column select switch 110. , BL2, / BL
Write the data amplified by the sense amplifier 90 to 2,.

Sense amplifier 90 is activated by a read / write control signal from read / write buffer 50.
When data is read, sense amplifier 90 connects bit line pair BL connected by column selection switch 110.
, And amplify the output signals on and output to the input / output buffer 130. When writing data, the sense amplifier 90 amplifies data from the input / output buffer 130 and outputs the amplified data to the write driver 80 via the input / output buffer 130.

The column selection switch 110 is connected to the bit line pair B of the column corresponding to the column address from the column address decoder 40.
, L1, / BL1, BL2, / BL2,... Are connected to the write driver 80 or the sense amplifier 90.

The memory cells 121 to 124 store a logical value “0” or “1” corresponding to storage information. The input / output buffer 130 outputs data from an input / output terminal to the sense amplifier 90 when writing data, and outputs data amplified by the sense amplifier 90 to the write driver 80. When reading data, the input / output buffer 130 outputs the data amplified by the sense amplifier 90 to the input / output terminal.

P channel MOS transistors 141-1
44 is always turned on and the corresponding bit line pair BL1,
/ BL1, BL2, / BL2,... Are supplied with an external power supply voltage.

Referring to FIG. 2, voltage supply circuit 72
Channel MOS transistor 720 and N-channel MO
An S transistor 721 and a power supply voltage node 722 are provided. Power supply voltage node 722 is connected to external power supply line 5. P-channel MOS transistor 720 and N-channel MOS transistor 721 are connected in parallel between an external power supply line and internal power supply line 6. Also, P-channel MOS
Transistor 720 and N-channel MOS transistor 7
21 receives internal write signal WEi at its gate terminal.

When data is written to memory cells 121 to 124, read / write control signal / WE at L level is read /
When input from write buffer 50 to inverter 71 of drive circuit 70, inverter 71 outputs an internal write signal WEi at H (logical high) level obtained by inverting read / write control signal / WE at L level. . Then, P-channel MOS transistor 720 and N-channel MOS transistor 721 receive the internal write signal WEi at the H level at the gate terminal, and receive P-channel MOS transistor 720.
Is turned off, and N-channel MOS transistor 721 is turned on. Then, N-channel MOS transistor 72
1 is a voltage VCC lower than the external power supply voltage VCC by the threshold value VTH of the N-channel MOS transistor 721.
-VTH is output to the internal power supply line 6.

The memory cells 121 to 124 are full CMOS type memory cells shown in FIG. Internal power line 6
Is connected to the power supply node 1 of the full CMOS type memory cell, the voltage VCC output to the internal power supply line 6
-VTH is the power supply node 1 of the memory cells 121 to 124
Supplied to Then, the load, P-channel MO
Since the voltage VCC-VTH is supplied to the S transistors 7a and 7b, the memory cells 121 to 124 are driven according to the inverter characteristics shown in FIG.

On the other hand, when reading data from memory cells 121 to 124, read / write buffer 50 outputs read / write control signal / WE at H level to inverter 71 of drive circuit 70. Outputs an L level internal write signal WEi. Then, P-channel MOS transistor 720 and N-channel MOS transistor 721 receive L-level internal write signal WEi at the gate terminal, and receive P-channel MOS transistor 72.
0 is turned on, and the N-channel MOS transistor 721 is turned off. Then, the P-channel MOS transistor 7
20 outputs the external power supply voltage VCC to the internal power supply line 6.

Since external power supply voltage VCC is supplied to power supply node 1 of memory cells 121 to 124, memory cells 121 to 124 are driven according to the inverter characteristics shown in FIG.

Therefore, voltage supply circuit 72 supplies voltage VC when writing data based on internal write signal WEi.
C-VTH is the power supply node 1 of the memory cells 121 to 124
To supply the external power supply voltage VCC to the power supply node 1 when data is read. Then, the memory cells 121 to 1
24 is driven according to an inverter characteristic having a small static noise margin SNM according to the voltage VCC-VTH, and driven according to an inverter characteristic having a large static noise margin SNM according to the voltage VCC. As a result, at the time of writing data, the static noise margin SNM becomes smaller and the write margin becomes larger.

Note that the inverter 71 of the drive circuit 70
P channel MOS transistor 720 and N channel MO
L-level internal write signal WE for selectively activating S transistor 721 and H-level internal write signal WE
In order to generate i, an activation signal generation circuit is configured in the present invention.

Referring again to FIG. 1, memory cell 121
The operation of reading / writing data from / to 124 will be described. In the read operation, an address signal and an H-level read / write control signal are externally input to semiconductor memory device 100 via input / output terminals. Row address buffer 10 outputs the input row address signal to row address decoder 30, and row address decoder 30 decodes the row address signal and outputs the decoded signal to word line driver 60. Then, the word line driver 60
Raises the word line corresponding to the row address to the H level.

The column address buffer 20 outputs the input column address signal to the column address decoder 40. The column address decoder 40 decodes the column address signal and outputs it to the column selection switch 110. Then, the column selection switch 110 controls the bit line pair BL1, BL1,
, / BL1, BL2, / BL2,.
Connect to 0.

On the other hand, read / write buffer 50 supplies an H level read / write control signal to inverter 7 of drive circuit 70.
1, and the inverter 71 outputs the L level internal write signal WEi to the voltage supply circuit 72. Then, voltage supply circuit 72 applies external power supply voltage VCC via internal power supply line 6 to memory cells 121 to 12 by the above-described method.
Supply to 4. Then, among the memory cells 121 to 124, the word line raised to the H level and the bit line pair BL1, / BL1, BL2, / BL2,... Connected to the sense amplifier 90 by the column selection switch 110 are connected. The connected memory cells are driven according to an inverter characteristic having a large static noise margin SNM, and output an output signal corresponding to stored data.

The sense amplifier 90 amplifies the output signal output and outputs the amplified output signal to the input / output buffer 130. And
The input / output buffer 130 outputs data to the outside via an input / output terminal.

In the write operation, the semiconductor memory device 1
At 00, an address signal and an L-level read / write control signal are externally input via an input / output terminal. Row address buffer 10 outputs the input row address signal to row address decoder 30, and row address decoder 30 decodes the row address signal and outputs the decoded signal to word line driver 60. Then, the word line driver 60 raises the word line corresponding to the row address to the H level.

Column address buffer 20 outputs the input column address signal to column address decoder 40, and column address decoder 40 decodes the column address signal and outputs it to column selection switch 110. Then, the column selection switch 110 controls the bit line pair BL1, BL1,
.. / BL1, BL2, / BL2,.
Connect to 0.

On the other hand, read / write buffer 50 supplies an L level read / write control signal to inverter 7 of drive circuit 70.
1, and the inverter 71 outputs the internal write signal WEi at the H level to the voltage supply circuit 72. Then, voltage supply circuit 72 applies external power supply voltage VCC-VTH to memory cell 12 via internal power supply line 6 by the method described above.
1 to 124. Then, the memory cells 121 to 1
24, the pair of bit lines BL1, / BL1, BL2, / BL2, connected to the write driver 80 by the column selection switch 110 and the word line raised to the H level.
Are driven according to the inverter characteristic having a small static noise margin SNM.

The input / output buffer 130 outputs data input via the input / output terminal to the sense amplifier 90, and receives amplified data from the sense amplifier 90. Then, the input / output buffer 130 outputs the amplified data to the write driver 80. Then, the write driver 8
0 indicates that the input data is a bit line pair BL1, / BL1, BL2, / B connected by the column selection switch 110.
Write to L2, ... Then, the bit line pairs BL1, / BL1, BL2, / BL2,.
Are driven in accordance with the inverter characteristic having a small static noise margin SNM, the bit line pair BL1, / BL1, BL2
The data on / BL2,... Is easily written to the memory cells.

According to the first embodiment, at the time of writing data, static semiconductor memory device 100 has a voltage VCC-VT for driving a memory cell according to an inverter characteristic having a small static noise margin SNM.
H is supplied to the memory cell, and at the time of data reading, the voltage VCC for driving the memory cell is supplied to the memory cell in accordance with the inverter characteristic having a large static noise margin SNM.
In addition, the data write margin can be increased.

[Second Embodiment] A static semiconductor memory device 200 according to a second embodiment differs from the static semiconductor memory device 100 shown in FIG. 1 in that the voltage supply circuit 72 is replaced with a voltage supply circuit 73. Is the same as in the first embodiment.

Referring to FIG. 3, voltage supply circuit 73 includes N-channel MOS transistor 722 of voltage supply circuit 72.
Is replaced by a high-resistance resistor 731. Resistance 731
Has a resistance value on the order of tera (T) Ω.

At the time of writing data to memory cells 121 to 124, P channel MOS transistor 720 receives an H level internal write signal WEi at its gate terminal and is turned off. Then, the resistor 731 outputs the voltage VCC to the internal power supply line 6 without substantially reducing the external power supply voltage VCC on the external power supply line 5. Then, the memory cells 121 to 124
Receives voltage VCC at power supply node 1. In this case, the memory cells 121 to 124 are driven according to the inverter characteristics having a small static noise margin SNM shown in FIG. 21 instead of the inverter characteristics having a large static noise margin SNM shown in FIG.
When the voltage supply circuit 73 supplies the voltage VCC to the memory cells 121 to 124 by the resistor 731, the memory cell 1
Since the P-channel MOS transistors 7a and 7b, which are loads of 21 to 124, and the resistor 731 are connected in series, the memory cells 121 to 124 substantially have the configuration shown in FIG.
Are driven in the same manner as the high resistance load type memory cell shown in FIG. Therefore, in this case, the memory cells 121 to 124
Is a small static noise margin S shown in FIG.
It is driven according to the inverter characteristics having NM.

In reading data from memory cells 121 to 124, on the other hand, P-channel MOS transistor 720
Is turned on in response to a low level internal write signal WEi received at the gate terminal. Then, since the resistance of P-channel MOS transistor 720 is very small,
Transistor 720 outputs voltage VCC to internal power supply line 6. The memory cells 121 to 124 are connected to the voltage VC
C is received by power supply node 1 and driven according to the inverter characteristics having a large static noise margin SNM shown in FIG. In this case, the memory cells 121 to 124
P-channel MOS transistors 7a and 7b which are loads of
Are connected in series with each other, the memory cells 121 to 124 are driven according to the inverter characteristic having a large static noise margin SNM shown in FIG. 24 since the resistance of the P-channel MOS transistor 720 of the voltage supply circuit 73 is very small. Is done.

As described above, in the second embodiment, the same voltage VCC is supplied from voltage supply circuit 73 to memory cells 121 to 124.
Driven according to different inverter characteristics. That is, when writing data, the voltage supply circuit 73 connects the resistor 731 in series with the memory cells 121 to 124 to connect the memory cell 1 to the memory cell 1.
The loads 21 to 124 are set as loads for driving according to the inverter characteristics having a small static noise margin SNM. On the other hand, at the time of data reading, voltage supply circuit 73 has a static noise margin SNM in which the load on memory cells 121 to 124 is large by connecting P-channel MOS transistor 720 having a very small resistance in series with memory cells 121 to 124. Set the load to drive according to the inverter characteristics.

Therefore, the inverter characteristics of the memory cells 121 to 124 can also be changed by changing the load connected in series with the memory cells 121 to 124. The rest is the same as the first embodiment.

According to the second embodiment, static semiconductor memory device 200 sets the load of the memory cell to a different load at the time of writing data and at the time of reading data.
When writing data, static noise margin SNM
Drive memory cells according to the small inverter characteristics of
When reading data, static noise margin SNM
Since the memory cell is driven according to the inverter characteristic having a large value, the memory cell can be driven stably and the data write margin can be increased.

[Third Embodiment] A static semiconductor memory device 300 according to a third embodiment differs from the static semiconductor memory device 100 shown in FIG. 1 in that the voltage supply circuit 72 is replaced with a voltage supply circuit 74. Is the same as in the first embodiment.

Referring to FIG. 4, voltage supply circuit 74 includes N-channel MOS transistor 722 of voltage supply circuit 72.
Is replaced by a P-channel thin film transistor 741. The P-channel thin film transistor 741 has a resistance value on the order of tera (T) Ω in the on state.

When writing data to memory cells 121 to 124, internal write signal WEi is at the H level. Therefore, P-channel MOS transistor 720 receives H level internal write signal WEi at its gate terminal, and is turned off.
The P-channel thin-film transistor 741 is turned on by receiving the L-level signal obtained by inverting the H-level internal write signal WEi by the inverter 742 at the gate terminal. Then, P-channel thin-film transistor 741 outputs voltage VCC to internal power supply line 6 without substantially reducing external power supply voltage VCC on external power supply line 5. Then, memory cells 121 to 124 receive voltage VCC at power supply node 1. In this case, since the P-channel thin film transistor 741 performs the same function as the resistor 731 of the second embodiment, the memory cells 121 to 124 are driven according to the inverter characteristic having a small static noise margin SNM shown in FIG.

On the other hand, at the time of reading data from memory cells 121 to 124, P-channel MOS transistor 720
Is turned on by receiving an L level internal write signal WEi at its gate terminal, and is turned off by receiving an H level signal at its gate terminal. Then, as described in the second embodiment, memory cells 121 to 124 receive voltage VCC at power supply node 1 and have a large static noise margin S shown in FIG.
It is driven according to the inverter characteristics having NM.

As described above, also in the third embodiment, the same voltage VCC is supplied from voltage supply circuit 73 to memory cells 121 to 124.
Driven according to different inverter characteristics. That is, the P channel M is used for data writing and data reading.
The OS transistor 720 and the P-channel thin film transistor 741 are selectively activated, and the memory cells 121 to 1
Set 24 loads to different loads. The rest is the same as the second embodiment.

According to the third embodiment, the static semiconductor memory device 300 sets the load of the memory cell to be different between when writing data and when reading data,
When writing data, static noise margin SNM
Drive memory cells according to the small inverter characteristics of
When reading data, static noise margin SNM
Since the memory cell is driven according to the inverter characteristic having a large value, the memory cell can be driven stably and the data write margin can be increased.

[Fourth Embodiment] A static semiconductor memory device 400 according to a fourth embodiment is obtained by replacing the voltage supply circuit 72 of the static semiconductor memory device 100 shown in FIG. The rest is the same as the semiconductor memory device 100.

Referring to FIG. 5, voltage supply circuit 75 includes N
Channel MOS transistor 751 and P-channel MO
An S transistor 752 and an inverter 753 are provided. N channel MOS transistor 751 and P channel MOS transistor 752 are connected to ground node 750
And the internal power supply line 6 are connected in parallel. Inverter 7
53 inverts the internal write signal WEi and outputs
Gate terminal of S transistor 751 and P channel M
This is supplied to the gate terminal of the OS transistor 752. Internal power supply line 6 is connected to ground node 8 in FIG.

At the time of writing data to memory cells 121 to 124, H level internal write signal WEi is input to inverter 753 of voltage supply circuit 75. Then, inverter 753 outputs an L-level signal to N-channel MOS.
Gate terminal of transistor 751 and P-channel MO
This is applied to the gate terminal of S transistor 752, N channel MOS transistor 751 is turned off, and P channel
S transistor 752 is turned on.

Then, P-channel MOS transistor 7
52 is a voltage GND + higher than the ground voltage GND by the threshold value VTH of the P-channel MOS transistor 752.
VTH is output to the internal power supply line 6. Memory cells 121-
124 receives the voltage GND + VTH at the ground node 8,
It is driven according to the inverter characteristics shown by the dotted line in FIG.
In this case, memory cells 121 to 124 are connected to ground node 8
Is raised to the potential GND + VTH, the potential of the node N2 in a region where a high voltage is supplied to the gate terminal of the N-channel MOS transistor 4a as the driving transistor rises by VTH. As a result, the inverter characteristic shown by the dotted line in FIG. 6 is obtained, and the static noise margin SN
M becomes smaller.

On the other hand, when writing data to memory cells 121 to 124, voltage supply circuit 75 receives an internal write signal WEi at L level. Then, the inverter 7
53 supplies an H-level signal to the gate terminal of N-channel MOS transistor 751 and the gate terminal of P-channel MOS transistor 752, so that N-channel MOS transistor 751 is turned on and P-channel MOS transistor 752 is turned off.

Then, N-channel MOS transistor 7
51 outputs the ground voltage GND to the internal power supply line 6. Memory cells 121 to 124 receive ground voltage GND at ground node 8 and are driven according to the inverter characteristics shown in FIG. 24, and static noise margin SNM increases.

As described above, in the fourth embodiment, at the time of data writing, voltage GND + VTH is supplied to ground node 8 of memory cells 121 to 124 to drive memory cells 121 to 124 according to the inverter characteristic having a small static noise margin. When data is read, voltage G is applied to ground node 8 of memory cells 121-124.
By supplying ND, the memory cells 121 to 121 have a large static noise margin according to the inverter characteristics.
124 is driven. The rest is the same as the first embodiment.

Note that a P-channel MOS transistor and N
The same as in the first embodiment, except that the channel MOS transistor is selectively activated to supply different voltages to the memory cells and drive the memory cells according to inverter characteristics having different static noise margins SNM. A voltage for driving a memory cell according to an inverter characteristic having a static noise margin SNM, and a small static noise margin SNM;
A transistor for supplying a voltage for driving a memory cell in accordance with the inverter characteristic having the above-mentioned characteristics to the memory cell is of a conductivity type opposite to that of the first embodiment.

According to the fourth embodiment, static semiconductor memory device 400 supplies different voltages to the ground node of the memory cell at the time of data writing and at the time of data reading. Since the memory cell is driven according to the inverter characteristic having a small margin SNM, and the memory cell is driven according to the inverter characteristic having a large static noise margin SNM during data reading, the memory cell is driven stably and the data write margin is increased. it can.

[Fifth Embodiment] Referring to FIG. 7, memory cells 121 to 124 are arranged in an array. When writing data to memory cell 121, word line W1 corresponding to the row address decoded by row decoder 30 is pulled up to H level by a word line driver (not shown in FIG. 7), and column decoder 20
Bit line pair BL corresponding to the column address decoded by
1, column select line 15 for writing data to / BL1
Is launched. Then, N-channel MOS transistors 13a and 13b are turned on, write data on I / O line 14a is transmitted to bit line pair BL1 and / BL1, and data is written into memory cell 121.

In this case, the adjacent memory cell 123 connected to the same word line W1 as the memory cell 121 automatically enters the read state. When the power supply voltage supplied to the memory cells 121 to 124 is extremely low at 2.2 V or less, the inverter of the N-channel MOS transistor 3a (or 3b) and the N-channel MOS transistor 4a (or 4b) of the memory cells 121 to 124 Since the characteristics disappear, the same word line W as that of the selected memory cell 121 is used.
1 is connected to the word line W1 of H.
When the level is raised to the level, there is no static noise margin SNM, and there is a problem that written data is lost. For this reason, when the voltage supply circuits 72 to 75 described in the first to fourth embodiments are used, when the power supply voltage falls to 2.2 or less, the memory cells other than the memory cell into which data is being written are not stored. Data loss cannot be prevented.

Therefore, static semiconductor memory device 500 according to the fifth embodiment uses voltage supply circuit 76 shown in FIG. 8 instead of voltage supply circuit 72 shown in FIG.

Referring to FIG. 8, the voltage supply circuit 76
It includes channel MOS transistors 720 and 763, an external power supply voltage control circuit 761, an inverter 762, and an N-channel MOS transistor 764. P-channel MOS transistor 763 and N-channel MOS transistor 764 connected in parallel are connected in series to external power supply voltage control circuit 761. External power supply voltage control circuit 761 is connected to power supply node 722, and has P-channel MOS transistors 763 and N connected in parallel.
Channel MOS transistor 764 is connected to internal power supply line 6. Also, a P-channel MOS transistor 72
0 is arranged between the power supply node 722 and the internal power supply line 6, and is connected to the external power supply voltage control circuit 761 and the P-channel MOS
Transistor 763 and N-channel MOS transistor 764 are connected in parallel.

P channel MOS transistor 720 and N channel MOS transistor 764 receive internal write signal WEi at the gate terminal, and are turned on / off. P channel MOS transistor 763 receives internal write signal WE
i receives the signal inverted by the inverter 762 at the gate terminal and is turned on / off.

When data is written to memory cells 121 to 124, that is, when H-level internal write signal WEi is input to voltage supply circuit 76, P-channel MOS transistor 720 is turned off, and P-channel MOS transistor 763 is turned off. And N channel MOS transistor 76
4 is turned on. Then, the external power supply voltage control circuit 761
Outputs a voltage corresponding to the level of external power supply voltage VCC to internal power supply line 6 by a method described later.

When data is read from memory cells 121-124, that is, L level internal write signal W
When Ei is input to voltage supply circuit 76, P channel MOS transistor 720 is turned on, and P channel MO transistor 720 is turned on.
S transistor 763 and N channel MOS transistor 764 are turned off. Then, P-channel MOS transistor 720 outputs voltage VCC to internal power supply line 6.

Referring to FIG. 9, external power supply voltage control circuit 7
61 includes resistors 765 and 767, P-channel MOS transistors 768 and 769, and an N-channel MOS transistor 770. The resistor 765 is connected to the power supply node 72.
3 and a ground node 766 are connected in series, and divide the external power supply voltage VCC supplied to the power supply node 722.

P channel MOS transistor 768 is
A resistor 76 is connected between power supply node 722 and ground node 766.
7,767 in series. In addition, P-channel MO
S transistor 768 receives the voltage on node 772 at its gate terminal, and is turned off when a voltage higher than lower limit voltage Vgn at which the inverter characteristics in FIG. 21 disappears is input to the gate terminal.

P channel MOS transistor 769 and N
Channel MOS transistor 770 is connected to power supply node 7
22 and a node 771 are connected in parallel. Also,
P-channel MOS transistor 769 is connected to node 763
The upper voltage is received at the gate terminal, and is turned off when a voltage higher than the lower limit voltage Vgn is input to the gate terminal. N-channel MOS transistor 770 is always on.

External power supply voltage VCC lower than lower limit voltage Vgn
Is supplied to power supply node 722, P-channel MOS transistor 768 is turned on because the voltage on node 772 is low, external power supply voltage VCC is supplied to node 763, and P-channel MOS transistor 769 receives external power supply voltage VCC. To the gate terminal. However, since external power supply voltage VCC is lower than lower limit voltage Vgn, P-channel MOS transistor 769 turns on and outputs external power supply voltage VCC to node 771. In this case, the N-channel MOS transistor 770 is also turned on, but the N-channel MOS transistor 770 has the voltage VCC-VTH
(VTH is the threshold value of the N-channel MOS transistor 770) is output to the node 771, and the voltage on the node 771 becomes the voltage VTH.

External power supply voltage VCC not lower than lower limit voltage Vgn
Is supplied to power supply node 722, node 772 applies a voltage lower than lower limit voltage Vgn to P-channel MOS transistor 768, so that P-channel MOS transistor 768 is turned on and node 763 attains external power supply voltage VCC. . Then, node 763 applies external power supply voltage VCC to the gate terminal of P-channel MOS transistor 769, so that P-channel OS transistor 769 is turned off. Then, N-channel MOS transistor 770 outputs voltage VCC-VTH to node 771.

Therefore, external power supply voltage control circuit 761
Indicates that when external power supply voltage VCC is lower than or equal to lower limit voltage Vgn, as shown in FIG.
Outputs external power supply voltage VCC to node 771,
When external power supply voltage VCC becomes higher than lower limit voltage Vgn, voltage VCC-VTH is output to node 771.

Then, referring to FIG. 8 again, when data is written to memory cells 121 to 124, a voltage is output from external power supply voltage control circuit 761 to internal power supply line 6, but external power supply voltage VCC is lower than the lower limit. External power supply voltage VCC is output to internal power supply line 6 when voltage is lower than voltage Vgn, and voltage V when external power supply voltage VCC is higher than lower limit voltage Vgn.
CC-VTH is output to internal power supply line 6. Then, the voltage VCC or VCC-VT output to the internal power line 6
H is supplied to the power supply node 1 of the memory cells 121 to 124.

As a result, the memory cells 121 to 124
When external power supply voltage VCC is lower than or equal to lower limit voltage Vgn, driving is performed according to the inverter characteristics shown in FIG. 24, and when external power supply voltage VCC becomes higher than lower limit voltage Vgn, FIG.
Are driven according to the inverter characteristics shown in FIG. When the external power supply voltage VCC is lower than the lower limit voltage Vgn, the memory cell 12
Although the inverter characteristics of the N-channel MOS transistors 3a (or 3b) and the N-channel MOS transistors 4a (or 4b) disappear, the N-channel M
OS transistor 4a (or 4b) and P-channel MO
Since the inverter characteristics with the S transistor 7a (or 7b) do not disappear, the memory cells 121 to 124
4 is driven according to the inverter characteristics shown in FIG.

Therefore, when external power supply voltage VCC is lower than or equal to lower limit voltage Vgn, data can be easily written to memory cells 1231 to 124 because the operating voltage is low.
Data is not lost because the static noise margin SNM is large. When the external power supply voltage VCC is higher than the lower limit voltage Vgn, the operating voltage is high, so that no data is lost and the static noise margin S
Since NM is small, the write margin is large.

When data is read, P channel M
Since the voltage VCC is supplied to the memory cells 121 to 124 by the OS transistor 720, the memory cell 121
To 124 are large static noise margins SNM
Driven according to the inverter characteristics having the following.

The other points are the same as those described in the first embodiment. According to the fifth embodiment, in the static semiconductor memory device 500, at the time of data writing, an inverter characteristic having a large static noise margin SNM or an inverter having a small static noise margin SNM according to the level of the supplied external power supply voltage VCC. Since the memory cell is driven according to the characteristics and the memory cell is driven according to the inverter characteristic having a large static noise margin SNM at the time of data reading, the external power supply voltage V
Even if CC fluctuates, data can be written and read stably.

[Sixth Embodiment] Referring to FIG. 11, a static semiconductor memory device 600 according to a sixth embodiment will be described.
Replaces the drive circuit 70 of the static semiconductor memory device 100 shown in FIG.
50 is added. Drive circuit 70A includes an inverter 71 and a voltage supply circuit 78.

Signal generation circuit 150 generates an internal write signal WLi based on a read / write control signal / WE from read / write buffer 50 by a method described later, and supplies voltage supply circuit 78 of drive circuit 70A. And word line driver 6
Output to 0.

Referring to FIG. 12, signal generation circuit 150
Consists of one-shot multis 151 and 152. The one-shot multi 151 and the one-shot multi 152 have different periods during which the output signal is held at the H level.

Referring to FIGS. 12 and 14, signal generation circuit 1
The generation of the internal write signal WLi at 50 is generated. A period for writing data to a memory cell specified by the address signal together with the address signal, L
Read / write control signal / WE holding the level is input. Then, read / write buffer 50 outputs read / write control signal / WE holding L level to signal generation circuit 150.
Output to Then, one shot multi 151
Generates a signal WEM that rises to the H level in synchronization with the fall of the read / write control signal / WE, and outputs it to the one-shot multi 152. And one shot multi 1
52 generates an internal write signal WLi which rises to the H level in synchronization with the fall of the signal WEM. Internal write signal W
Li holds the H level for a period shorter than the period in which read / write control signal / WE holds the L level.

Referring to FIG. 13, voltage supply circuit 78 includes:
This is obtained by adding a NAND 781 and an inverter 782 to the voltage supply circuit 72 shown in FIG. NAND 781
Inputs the internal write signals WEi and WLi and takes the logic of the two signals. And, the inverter 782
The output signal of ND781 is inverted and applied to the gate terminal of P-channel MOS transistor 720 and the gate terminal of N-channel MOS transistor 721. That is, the voltage supply circuit 78 outputs the internal write signal WEi and the internal write signal WL.
When i and H are both at the H level, the N-channel MOS transistor 721 is turned on to supply the voltage VCC-VTH to the memory cells 121 to 124.

When the mode shifts to the data read mode, read / write control signal / WE is maintained at H level, so that signal generation circuit 150 sets internal write signal WL at H level.
Output i. Then, NAND 781 receives L level internal write signal WEi and H level internal write signal WLi, outputs an H level signal, and inverter 721 outputs an L level signal. Then, N
Channel MOS transistor 721 is turned off, P channel MOS transistor 720 is turned on, and voltage VCC is output to internal power supply line 6.

Therefore, when writing data to memory cells 121 to 124, voltage supply circuit 78 applies voltage VCC-VTH to memory cell for a period shorter than the period during which read / write control signal / WE holds L level. Cells 121 to 12
4 and drives the memory cells 121 to 124 in accordance with the inverter characteristics having a small static noise margin SNM, and stores data in the memory cell 1.
When reading from memory cells 21 to 124, voltage VCC is supplied to power supply node 1 of memory cells 121 to 124, and memory cells 121 to 124 are driven in accordance with inverter characteristics having a large static noise margin SNM.

Referring to FIG. 11 again, data read operation and write operation in static semiconductor memory device 600 will be described. In the read operation, an address signal and an H level read / write control signal /
WE is input. Row address buffer 10 outputs the input row address signal to row address decoder 30, and row address decoder 30 decodes the row address signal and outputs the decoded signal to word line driver 60.

On the other hand, signal generation circuit 150 outputs H level internal write signal WLi to voltage supply circuit 78 of drive circuit 70 A and word line driver 60 based on H level read / write control signal / WE. . Then, word line driver 60 receives internal write signal WLi held at the H level, and sets the word line corresponding to the row address to H level.
Raise to the level.

Column address buffer 20 outputs the input column address signal to column address decoder 40, and column address decoder 40 decodes the column address signal and outputs it to column selection switch 110. Then, the column selection switch 110 controls the bit line pair BL1, BL1,
, / BL1, BL2, / BL2,.
Connect to 0.

On the other hand, read / write buffer 50 outputs read / write control signal / WE at H level to inverter 71 of drive circuit 70A, and inverter 71 supplies internal write signal WEi at L level to the voltage supply circuit. 78. Then, voltage supply circuit 78 outputs internal write signal W of H level.
Based on Li and the L level internal write signal WEi, the voltage VCC is supplied to the memory cells 121 to 124 via the internal power supply line 6 as described above. And memory cell 1
Of the word lines 21 to 124, the word line raised to the H level and the column selection switch 110
Bit lines BL1, / BL1, BL2, /
The memory cells connected to BL2,... Are driven according to the inverter characteristic having a large static noise margin SNM, and output an output signal corresponding to the stored data.

Sense amplifier 90 amplifies the output signal thus output and outputs it to input / output buffer 130. And
The input / output buffer 130 outputs data to the outside via an input / output terminal.

In the write operation, the semiconductor memory device 6
00, an address signal and an L-level read / write control signal / WE are input from the outside via an input / output terminal. Row address buffer 10 outputs the input row address signal to row address decoder 30, and row address decoder 30 decodes the row address signal and outputs the decoded signal to word line driver 60.

On the other hand, as described above, the signal generation circuit 150 generates a signal based on the read / write control signal / WE at L level.
Internal write signal WLi holding H level for a period shorter than read / write control signal / WE holding L level
To the voltage supply circuit 78 of the drive circuit 70A and the word line driver 60. Then, word line driver 60 receives internal write signal WLi held at the H level, and raises the word line corresponding to the row address to the H level only while internal write signal WLi holds the H level.

Column address buffer 20 outputs the input column address signal to column address decoder 40, and column address decoder 40 decodes the column address signal and outputs it to column selection switch 110. Then, the column selection switch 110 controls the bit line pair BL1, BL1,
.. / BL1, BL2, / BL2,.
Connect to 0.

On the other hand, read / write buffer 50 outputs an L level read / write control signal / WE to inverter 71 of drive circuit 70A, and inverter 71 supplies an H level internal write signal WEi to a voltage supply circuit. 78. Then, voltage supply circuit 78 supplies external power supply voltage VCC-VTH to memory cells 121 to 124 via internal power supply line 6 only during the period in which internal write signal WLi holds the H level by the method described above. Then, the memory cell 12
Among the word lines 1 to 124, the word line raised to the H level and the bit line pair BL1, / BL1, BL2, / B connected to the write driver 80 by the column selection switch 110
The memory cells connected to L2,... Are driven according to the inverter characteristic having a small static noise margin SNM.

The input / output buffer 130 outputs data input via the input / output terminal to the sense amplifier 90, and receives amplified data from the sense amplifier 90. Then, the input / output buffer 130 outputs the amplified data to the write driver 80. Then, the write driver 8
0 indicates that the input data is a bit line pair BL1, / BL1, BL2, / B connected by the column selection switch 110.
Write to L2, ... Then, the bit line pairs BL1, / BL1, BL2, / BL2,.
Are driven in accordance with the inverter characteristic having a small static noise margin SNM, the bit line pair BL1, / BL1, BL2
The data on / BL2,... Is easily written to the memory cells. In this case, the period during which the memory cells 121 to 124 are driven according to the inverter characteristics having a small static noise margin SNM coincides with the period during which the word line is raised to the H level.

In the above description, the example using the voltage supply circuit 72 in the first embodiment has been described. However, the sixth embodiment is not limited to this, and the voltage supply circuit 72 is replaced with the voltage supply circuit 72 in the second embodiment. A voltage supply circuit 78 may be configured using the supply circuit 73, the voltage supply circuit 74 in the third embodiment, the voltage supply circuit 75 in the fourth embodiment, and the voltage supply circuit 76 in the fifth embodiment.

When voltage supply circuit 78 is formed using these voltage supply circuits 72 to 76, internal write signal WL
Only during the period when i holds the H level, the memory cell can be driven according to the inverter characteristics having a small static noise margin SNM.

According to the sixth embodiment, static semiconductor memory device 600 has a small static noise only during a period shorter than a period in which read / write control signal / WE indicating a data write mode period holds L level. Since the memory cells are driven according to the inverter characteristics having the margin SNM, the write margin can be increased and the consumption of the semiconductor memory device can be reduced.

[Seventh Embodiment] Referring to FIG. 15, a static semiconductor memory device 700 according to a seventh embodiment will be described.
Is a static semiconductor memory device 600 shown in FIG.
Is replaced by a signal generation circuit 150A, and the rest is the same as the semiconductor memory device 600.

Signal generation circuit 150A generates internal write signals WLi and WLSi based on read / write control signal / WE, outputs internal write signal WLi to word line driver 60, and outputs internal write signal WLSi. To the voltage supply circuit 78 of the drive circuit 70A. Other than that, the semiconductor memory device 6
Same as 00.

Referring to FIG. 16, signal generation circuit 150A
Consists of one-shot multis 151, 152, 153. The one-shot multis 151 and 152 are the same as those described in the sixth embodiment. One Shot Multi 1
53 holds the output signal at the H level during a period different from those of the one-shot multis 151 and 152.

Referring to FIGS. 16 and 17, signal generation circuit 1
The generation of the internal write signals WLi and WLSi at 50A will be described. Along with the address signal, a read / write control signal / W holding L level during a period for writing data to a memory cell designated by the address signal.
E is input. Then, the read / write buffer 50
The read / write control signal / WE holding the L level is output to the signal generation circuit 150. Then, one-shot multi 151 generates signal WEM which rises to H level in synchronization with the fall of read / write control signal / WE and outputs it to one-shot multis 152 and 153. Then, one-shot multi 152 generates internal write signal WLi which rises to H level in synchronization with the fall of signal WEM. The one-shot multi 153 outputs the internal write signal W which rises to the H level in synchronization with the fall of the signal WEM.
Generate LSi. Internal write signal WLi holds H level for a shorter period than read / write control signal / WE holds L level. Also, the internal write signal WL
Si is shorter than the period in which read / write control signal / WE holds L level, and stores data in memory cell 12.
The H level is maintained during the period of actually writing data to 1 to 124.

On the other hand, when data is read, signal generation circuit 1
50A receives an H level read / write control signal / WE. Then, the one-shot multi 151 is H
The level signal WEM is output. Then, one-shot multis 152 and 153 also have internal write signal WL at H level.
i, WLSi.

Then, at the time of writing data to memory cells 121 to 124, voltage supply circuit 78 supplies H level internal write signal WEi and H level internal write signal WLS.
i is input, and the word line driver 60 receives the internal write signal WLi at the H level. Voltage supply circuit 78 receives N-channel MOS transistor 721 only during a period of actually writing data based on H-level internal write signal WEi and H-level internal write signal WLSi.
The voltage VCC-VTH is applied to the memory cells 121 to 12
4 to the power supply node 1. The word line driver 60 raises the word line corresponding to the row address to the H level only while the internal write signal WLi is at the H level.
Thus, the memory cells 121 to 124 can be driven according to the inverter characteristics with a small static noise margin SNM only during the period when data is actually written to the memory cells 121 to 124.

On the other hand, when data is read from memory cells 121 to 124, voltage supply circuit 78 receives an internal write signal WEi at L level and an internal write signal WLSi at H level, and Receives an H level internal write signal WLi. And the voltage supply circuit 7
8, a voltage VCC is applied to the memory cell 12 by the P-channel MOS transistor 720 based on the L level internal write signal WEi and the H level internal write signal WLSi.
The power is supplied to the power supply nodes 1 to 124. The word line driver 60 raises the word line corresponding to the row address to the H level only while the internal write signal WLi is at the H level. Thus, during a period in which data is read from memory cells 121 to 124, memory cells 121 to 124 can be driven according to the inverter characteristic having a large static noise margin SNM.

Data reading and writing operations in static semiconductor memory device 700 are the same as those in the sixth embodiment.

In the above description, the example using the voltage supply circuit 72 in the first embodiment has been described. However, the seventh embodiment is not limited to this, and the voltage supply circuit 72 in the second embodiment is used instead of the voltage supply circuit 72. A voltage supply circuit 78 may be configured using the supply circuit 73, the voltage supply circuit 74 in the third embodiment, the voltage supply circuit 75 in the fourth embodiment, and the voltage supply circuit 76 in the fifth embodiment.

When voltage supply circuit 78 is formed using these voltage supply circuits 72 to 76, internal write signal WL
The memory cell can be driven according to the inverter characteristic having a small static noise margin SNM only during the period when Si holds the H level.

According to the seventh embodiment, static type semiconductor memory device 600 actually writes data shorter than the period in which read / write control signal / WE indicating the data write mode period is at L level. Since the memory cells are driven in accordance with the inverter characteristics having a small static noise margin SNM only during the period of writing, the write margin can be increased, and the power consumption of the semiconductor memory device can be further reduced.

[Eighth Embodiment] Recently, the capacity of a static semiconductor memory device has been increased, and a plurality of cell arrays exist. Therefore, as shown in FIG. 18, a plurality of memory cells are divided into a plurality of blocks BLK1, BLK2,..., BLKn.
, And each block BLK1, BLK2,.
Drive circuits 901, 902,... Corresponding to LKn
・, 90n are provided. Each drive circuit 901, 902,...
, 90n are connected to the external power supply line 5 and supplied with the external power supply voltage VCC.

Each driving circuit 901, 902,..., 90
n includes the voltage supply circuits 72 to 76 described in the first to fifth embodiments. Each drive circuit 901, 902,
, 90n include the voltage supply circuits 72 to 74, 76 described in the first to third and fifth embodiments, the external power supply voltage VCC is supplied via the external power supply line 5. The voltage supply circuit 7 of each of the driving circuits 901, 902,.
Each of memory cells 2 to 74 and 76 supplies voltage VCC or VCC-VTH to power supply node 1 of the memory cell, and includes a memory included in a corresponding block according to an inverter characteristic having a small static noise margin SNM or an inverter characteristic having a large static noise margin. Drive the cell.

The driving circuits 901, 902,...
., 90n include the voltage supply circuit 75 shown in the fourth embodiment, the ground voltage GND is supplied via the external power supply line 5. Each of the driving circuits 901, 902,.
90n voltage supply circuit 75 supplies voltage GND or GND + VTH to ground node 8 of the memory cell, and drives a memory cell included in a corresponding block according to an inverter characteristic having a small static noise margin SNM or an inverter characteristic having a large static noise margin. I do.

The driving circuits 901, 902,...
, 90n correspond to the selection of the corresponding blocks BLK1 to BLKn by the block selection signals BLS1 to BLSn, and the corresponding blocks BLK1 to BLKn
Are driven according to different inverter characteristics.

Referring to FIG. 19, for example, when each drive circuit 901, 902,..., 90n includes the voltage supply circuit 72 in the first embodiment, each drive circuit 901, 9
, 90n are a voltage supply circuit 72 and a NAND
801 and an inverter 802. NAND80
1 is the internal write signal WEi and the block select signal BLS1
To BLSn. When writing data,
H level internal write signal WEi and corresponding block B
When an H-level block selection signal indicating that LK1 to BLKn has been selected is input, NAND 801
An L-level signal is output, and inverter 802 outputs an H-level signal. Therefore, the voltage supply circuit 72
The voltage VCC is set by the channel MOS transistor 721.
-VTH is output to the internal power supply line 6. Then, the memory cells included in corresponding blocks BLK1 to BLKn are driven according to the inverter characteristic having a small static noise margin SNM, and the write margin is increased.

The corresponding blocks BLK1 to BLK
When n is not selected, the NAND 801 outputs an L level signal because the L level block selection signals BLS1 to BLKn are input, and the inverter 802 outputs an L level signal. As a result, the voltage supply circuit 72
Outputs voltage VCC to internal power supply line 6 by P-channel MOS transistor 720. Then, the external power supply voltage VCC is supplied to the memory cells included in the corresponding blocks BLK1 to BLKn. Therefore, the memory cells included in the block are stable without losing data.

At the time of data reading, NADN 801 outputs L
Since the internal write signal WEi of the level is input, regardless of whether the corresponding blocks BLK1 to BLKn are selected, that is, the block selection signals BLS1 to BLSB
Regardless of whether LSn is at H level or L level, an H level signal is output, and the inverter 802 outputs an L level signal. Then, as described above, the voltage supply circuit 72
Outputs voltage VCC to internal power supply line 6 by P-channel MOS transistor 720. The memory cells included in the corresponding blocks BLK1 to BLKn include:
An external power supply voltage VCC is supplied. Therefore, when a corresponding block is selected for data reading, memory cells included in the block are driven according to the inverter characteristic having a large static noise margin SNM to read data. In the data read mode, when the corresponding block is not selected, the memory cells included in the block are stable without data loss.

The same applies when other voltage supply circuits 73 to 76 are used. Therefore, the voltage supply to the memory cells included in the corresponding block by voltage supply circuits 72 to 76 is associated with the block selection signal, so that the memory cells included in the corresponding block are suitable for writing data or reading data. It can be driven accurately according to the inverter characteristics.

According to the eighth embodiment, when a corresponding block is selected, each drive circuit provided corresponding to each block can change a memory cell included in the block to an inverter characteristic or a static noise margin having a small static noise margin. Since driving is performed in accordance with the inverter characteristic having a large static noise margin, data can be written and data can be read accurately.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0179]

According to the present invention, a static semiconductor memory device supplies a voltage VCC-VTH for driving a memory cell according to an inverter characteristic having a small static noise margin SNM to a memory cell at the time of writing data. When data is read, voltage VCC for driving the memory cell is supplied to the memory cell in accordance with the inverter characteristic having a large static noise margin SNM, so that the memory cell can be driven stably and the data write margin can be increased. .

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a static semiconductor memory device according to a first embodiment.

FIG. 2 is a circuit diagram of a voltage supply circuit in the semiconductor memory device shown in FIG.

FIG. 3 is a circuit diagram of a voltage supply circuit of a static semiconductor memory device according to a second embodiment;

FIG. 4 is a circuit diagram of a voltage supply circuit of a static semiconductor memory device according to a third embodiment.

FIG. 5 is a circuit diagram of a voltage supply circuit of a static semiconductor memory device according to a fourth embodiment.

6 is an inverter characteristic diagram of a memory cell when a voltage is supplied by the voltage supply circuit shown in FIG. 5; .

FIG. 7 is a schematic block diagram of a static semiconductor memory device.

FIG. 8 is a circuit diagram of a voltage supply circuit of a static semiconductor memory device according to a fifth embodiment.

9 is a circuit diagram of an external power supply voltage control circuit included in the voltage supply circuit of FIG.

FIG. 10 is a characteristic diagram of a voltage output by an external power supply voltage control circuit included in the voltage supply circuit of FIG. 8;

FIG. 11 is a schematic block diagram of a static semiconductor memory device according to a sixth embodiment.

12 is a block diagram of a signal generation circuit of the static semiconductor memory device shown in FIG.

13 is a circuit diagram of a voltage supply circuit of the static semiconductor memory device shown in FIG.

14 is a timing chart of signals in the static semiconductor memory device shown in FIG. 11;

FIG. 15 is a schematic block diagram of a static semiconductor memory device according to a seventh embodiment.

16 is a block diagram of a signal generation circuit in the static semiconductor memory device shown in FIG.

17 is a timing chart of signals in the static semiconductor memory device shown in FIG.

FIG. 18 is a block diagram of a static semiconductor memory device according to an eighth embodiment.

19 is a circuit diagram of a drive circuit of the static semiconductor memory device shown in FIG.

FIG. 20 is a circuit diagram of a high resistance load type memory cell.

21 is an inverter characteristic diagram of the memory cell shown in FIG.

FIG. 22 is another circuit diagram of a high resistance load type memory cell.

FIG. 23 is a circuit diagram of a full CMOS type memory cell.

24 is an inverter characteristic diagram of the memory cell shown in FIG.

FIG. 25 is another circuit diagram of a full CMOS type memory cell.

[Explanation of symbols]

1,722 power supply nodes, 2a, 2b, 731, 76
5,767 resistance, 5 external power line, 6 internal power line, 1
0 row address buffer, 3a, 3b, 4a, 4b, 1
3a, 13b, 141 to 144, 721, 751, 76
4,770 N-channel MOS transistors, 7a, 7
b, 720,752,763,768,769 P-channel MOS transistor, 8,750,766 Ground node, 14a I / O line, 20 column address buffer,
30 row address decoder, 40 column address decoder,
50 read / write buffers, 60 word line drivers,
70, 70A, 901 to 90n drive circuit, 71, 74
2,753,762,782,802 Inverter, 7
2, 73, 74, 75, 76, 78 Voltage supply circuit, 8
0 Write driver, 90 sense amplifier, 100-60
0 semiconductor memory device, 110 column selection switch, 120
~ 124 memory cells, 130 I / O buffers, 15
0,150A signal generation circuit, 151-153 one-shot multi, 741 P-channel thin film transistor,
761 external power supply voltage control circuit, 763, 771, 77
2 nodes, 781, 801 NAND.

Claims (18)

[Claims] 1. A plurality of memory cells driven according to a first inverter characteristic having a first static noise margin or a second inverter characteristic having a second static noise margin larger than the first static noise margin. When writing data to each of the plurality of memory cells, driving each of the plurality of memory cells according to the first inverter characteristic, and reading data from each of the plurality of memory cells, A driving circuit for driving each of the plurality of memory cells according to the inverter characteristics of the first and second inverters, wherein each of the plurality of memory cells includes a first driving transistor of a first conductivity type and a second driving transistor of a second conductivity type. A first inverter comprising a load transistor and a second drive transistor of a first conductivity type; And a flip-flop circuit having a second inverter including a second load transistor of a second conductivity type and a first access transistor of a first conductivity type connected to an output node of the first inverter. And a second access transistor of a first conductivity type connected to an output node of the second inverter. 2. The method according to claim 1, wherein when writing data to each of the plurality of memory cells, the drive circuit supplies a first voltage for driving the plurality of memory cells to each of the plurality of memory cells. 2. The static type according to claim 1, wherein when data is read from each of said plurality of memory cells, a second voltage for driving according to said second inverter characteristic is supplied to each of said plurality of memory cells. Semiconductor storage device. 3. The static semiconductor memory device according to claim 2, wherein said drive circuit supplies said first and second voltages to a high voltage node of each of said memory cells. 4. An activation signal for generating a first activation signal in response to activation of a write signal, and for generating a second activation signal in response to inactivation of the write signal. A generation circuit, when writing data to each of the plurality of memory cells, supplying the first voltage to each of the plurality of memory cells based on the first activation signal; And a voltage supply circuit for supplying the second voltage to each of the plurality of memory cells based on the second activation signal when reading data from each of the plurality of memory cells. An external power supply line to which a voltage is supplied; an internal power supply line connected to a high voltage node of each of the plurality of memory cells; a first power supply line connected between the external power supply line and the internal power supply line; In response to the activation signal, the first voltage is increased. A first voltage supply transistor of a first conductivity type to be supplied to the internal power supply line, and the first voltage supply transistor connected between the external power supply line and the internal power supply line in parallel with the first voltage supply transistor; 4. The static semiconductor memory device according to claim 3, further comprising a second voltage supply transistor of a second conductivity type that receives the second activation signal and supplies the second voltage to the internal power supply line. 5. The static semiconductor memory device according to claim 2, wherein said drive circuit supplies said first and second voltages to a low voltage node of each of said memory cells. 6. An activation signal for generating a first activation signal in response to activation of a write signal, and for generating a second activation signal in response to inactivation of the write signal. A generation circuit, when writing data to each of the plurality of memory cells, supplying the first voltage to each of the plurality of memory cells based on the first activation signal; And a voltage supply circuit for supplying the second voltage to each of the plurality of memory cells based on the second activation signal when reading data from each of the plurality of memory cells. A first activation signal connected between the ground node and the internal power supply line, the first activation signal being connected between the ground node and the internal power supply line. Receiving the first voltage and A third voltage supply transistor of a second conductivity type to be supplied to the internal power supply line, and a third voltage supply transistor connected in parallel with the third voltage supply transistor between the ground node and the internal power supply line; 7. The static semiconductor memory device according to claim 6, further comprising a fourth voltage supply transistor of a first conductivity type for receiving said activation signal and supplying said second voltage to said internal power supply line. 7. The drive circuit, when writing data to each of the plurality of memory cells, sets a load of each of the memory cells to a first load for driving according to the first inverter characteristic, 2. The static semiconductor memory according to claim 1, wherein when reading data from each of said plurality of memory cells, a load of each of said memory cells is set to a second load for driving according to said second inverter characteristic. apparatus. 8. A signal generation circuit for generating an activation signal in accordance with activation of a write signal, and generating an inactivation signal in accordance with inactivation of the write signal; When writing data to each of the cells, the second voltage is supplied based on the inactivation signal to set the load of each of the memory cells to the first load. And a voltage supply circuit for supplying the second voltage based on the activation signal and setting a load of each of the memory cells to the second load when reading data from the memory cell. Static semiconductor memory device. 9. The external power supply line to which an external power supply voltage is supplied, an internal power supply line connected to a high voltage node of each of the plurality of memory cells, the external power supply line and the internal power supply line. A second conductive type connected between the power supply line and the power supply line, receiving the activation signal, supplying the second voltage to the internal power supply line, and setting the load of each memory cell to the second load; The voltage supply transistor is connected in parallel with the voltage supply transistor between the external power supply line and the internal power supply line, and the voltage supply transistor is inactivated by the inactivation signal. 9. The static semiconductor memory device according to claim 8, further comprising: a resistor that supplies the second voltage to the internal power supply line and sets a load of each of the memory cells to the first load. 10. An activation signal generator for generating a first activation signal when a write signal is activated and for generating a second activation signal when a write signal is deactivated. A circuit, when writing data to each of the plurality of memory cells, supplying the second voltage based on the first activation signal to set the load of each memory cell to the first load And
When reading data from each of the plurality of memory cells,
8. The static semiconductor according to claim 7, further comprising: a voltage supply circuit configured to supply the second voltage based on the second activation signal to set a load of each of the memory cells to the second load. Storage device. 11. The voltage supply circuit includes: an external power supply line to which an external power supply voltage is supplied; an internal power supply line connected to a high voltage node of each of the plurality of memory cells; And a second power supply line connected to the internal power supply line in response to the first activation signal.
And a second conductive type thin film transistor for setting the load of each memory cell to the first load, and the thin film transistor is connected in parallel with the thin film transistor between the external power supply line and the internal power supply line, A second conductivity type voltage supply transistor for receiving the second activation signal, supplying the second voltage to the internal power supply line, and setting the load of each of the memory cells to the second load; 11. The static semiconductor memory device according to claim 10, comprising: 12. A plurality of memory cells driven according to a first inverter characteristic having a first static noise margin or a second inverter characteristic having a second static noise margin larger than the first static noise margin. And when driving data in each of the plurality of memory cells, driving each of the plurality of memory cells according to the first inverter characteristic or the second inverter characteristic according to a supplied external power supply voltage. A first inverter comprising a first drive transistor of a first conductivity type and a first load transistor of a second conductivity type, and a first conductivity type. A second driving transistor of the second conductivity type and a second load transistor of the second conductivity type. A flip-flop circuit having an inverter, a first access transistor of a first conductivity type connected to an output node of the first inverter, and a first conductivity type connected to an output node of the second inverter. And a second access transistor. 13. The drive circuit according to claim 1, wherein an inverter characteristic between the first drive transistor and the first access transistor or an inverter characteristic between the second drive transistor and the second access transistor disappears. When an external power supply voltage higher than the lower limit voltage is supplied, each of the plurality of memory cells is driven according to the first inverter characteristic, and when the external power supply voltage equal to or lower than the lower limit voltage is supplied, the plurality of memory cells are driven. 13. The method according to claim 12, wherein each of the memory cells is driven according to the second inverter characteristic.
3. The static semiconductor memory device according to 1. 14. The drive circuit, when an external power supply voltage higher than the lower limit voltage is supplied along with activation of a write signal, drives each of the plurality of memory cells according to the first inverter characteristic. Outputting a first voltage for causing
11. An external power supply voltage control circuit that outputs a second voltage for operating each of the plurality of memory cells according to the second inverter characteristic when an external power supply voltage equal to or lower than the lower limit voltage is supplied. 14. The static semiconductor memory device according to item 13. 15. The drive circuit according to claim 1, wherein the drive circuit drives each of the plurality of memory cells according to the first inverter characteristic for a period shorter than a period during which a write signal is activated. Static semiconductor memory device. 16. The drive circuit according to claim 1, wherein the drive circuit drives each of the plurality of memory cells according to the first inverter characteristic only during a period in which data is written to the memory cells in response to activation of a write signal. 13. The static semiconductor memory device according to claim 12. 17. The static semiconductor memory device according to claim 1, wherein said plurality of memory cells are divided into a plurality of blocks, and said driving circuit is provided corresponding to said plurality of blocks. 18. The drive circuit according to claim 17, wherein the drive circuit supplies the first voltage to a plurality of memory cells included in the corresponding block in response to activation of a block selection signal for selecting the corresponding block. Static semiconductor memory device.