JPS63281296A - Dynamic ram - Google Patents

Abstract

PURPOSE:To prevent the fluctuation of a power source voltage and to eliminate the generation of malfunction by generating a sense amplifier activating signal for a dividing action based on an array selection signal and a sense amplifier activating signal. CONSTITUTION:At the time of a refresh mode, by the control of an external signal RPC, a dividing action control signal, the inverse of RPC and array selecting signals Aj and the inverse of Aj are generated and continuously, word line driving signals for a dividing action RX and RX and sense amplifier activating signals S1 and S2 are generated based on these array selecting signals Aj and the inverse of Aj. When an address counter goes around, only one of the divided memory cell arrays is refreshed. Namely, since a refreshing is divided and executed, the peak current at the time if reduced. Thus, the fluctuation of a power source voltage is prevented and an erroneous action generating is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a dynamic RAM, and particularly relates to a reduction in peak current during refresh.

<Prior art> In recent years, dynamic RAMs have divided memory cell arrays into multiple blocks for the purpose of reducing bit line capacitance, etc., and have built-in address counters that are activated at timings such as CAS before RAS. Dynamic r(A) has an auto-refresh function that automatically refreshes using the counter output.
M is becoming mainstream.

FIG. 5 is a configuration diagram of such a conventional dynamic RAM memory cell array, and FIG. 6 is a diagram of a dynamic RAM memory cell array.
FIG. 3 is a configuration diagram of an address counter for auto-refresh built in the . In these figures, laS lb is a memory cell array divided into two blocks on the left and right in the figure,
2a and 2b are row decoders provided in each memory cell array 1a and lb, and 3 is a column decoder (including a sense amplifier).

Further, RX is a word line drive signal, and this word line drive signal RX is commonly given to each of the left and right row decoders 2a and 2b. WLk, , WLk are the word lines from the left in each of the left and right memory cell arrays 1a and Ib. 5a, 5b are common source lines of sense amplifiers, 6a, 6
b is a MOS)-transistor, S is a sense amplifier activation signal commonly applied to the gates of both MOS transistors 6a and 6b, and 8 is an address counter for auto-refresh. This address counter 8 is composed of a plurality of flip-flops 10a-10+, and receives a counter decrement signal CD that changes from low level to high level every refresh cycle, and outputs Qo-Qi according to this signal CD. Change. Note that this dynamic RAM includes a circuit for equalizing and precharging bit lines, and a circuit for restoring, although not shown.

Next, the operation of this conventional dynamic RAM will be explained with reference to the timing chart shown in FIG.

In refresh mode, the external signal is τWτbefo
re RA S , that is, the column address strobe signal τπ1 goes low first (time to), and then the row address strobe signal RAS goes low (time to). Then, this row address strobe signal τT
A refresh transition signal REF synchronized with 'ff is generated. In an address buffer (not shown), input of an external address signal is cut off in response to the refresh transition signal REF, while address counter outputs Q0 to Qi are input instead. The address buffer latches the output Q0 to Qi of the address counter 8 and sends it to the row decoders 2a, 2b as a row address signal, so that one corresponding word line from among the word lines in the memory cell array 1aslb, e.g. WLk,
, WLkt are selected. Subsequently, the word line drive signal R
X becomes high level (time 11), and the memory cell enters the read state. In this state, the address buffer has already latched the row address signal, so the address counter 8 output Q.

~Changes in Qi are allowed. Therefore, the address counter 8 is counted down by the counter decrement signal CD (time t,) and moves on to specifying the next row address. On the other hand, when the memory cells connected to both word lines WLk, WLkt enter the read state (time 11
), the sense amplifier activation signal S goes high, and sense restoration (refresh) is performed.

In this way, the output Q of the address counter 8. ~Qi
By making one round, the left and right memory cell arrays 1a and lb, which are divided into two, are all refreshed.

<Problems to be Solved by the Invention> Incidentally, in a conventional dynamic RAM, a peak current flows due to charging current and through current during refreshing. Moreover, since a large number of dynamic RAMs are normally arranged closely on a mounting board, their peak currents are integrated and become excessive, resulting in fluctuations in the power supply voltage. As a result, there is a problem in that noise is generated in the power supply line, causing an adverse effect such as causing malfunction of not only the dynamic RAM arranged on the mounting board but also other ICs.

The present invention was made to solve the above-mentioned problems, and its purpose is to reduce the peak current during refresh, thereby preventing fluctuations in the power supply voltage and preventing malfunctions from occurring. It is said that

<Means for Solving the Problems> In order to achieve the above-mentioned object, the present invention adopts the following configuration. That is, in the dynamic RAM of the present invention, the count output of the address counter is increased by one high-order bit, and the level of the refresh transition signal REF is inverted based on the division operation transition signal RPC and the refresh transition signal REF which are applied from the outside during the refresh mode. A division operation control signal generation circuit that generates division operation control signal RPC, and latch outputs Qja, Qj of the added most significant bit of the division operation control signal RPC and the address counter.
an array selection signal generation circuit that generates an array selection signal Aj, h3'' based on the array selection signal A;
Based on j, h3 and word line drive signal RX, word line drive signals RX, RX! for division operation are generated. a word line drive signal generation circuit for division operation that generates a word line drive signal generation circuit for division operation; and a division operation word line drive signal generation circuit that generates sense amplifier activation signals S and SS for division operation based on this array selection decode signal AjSAj and sense amplifier activation signal S. The configuration includes a sense amplifier activation signal generation circuit.

According to the above configuration, in the refresh mode, the division operation control signal RPC and the array selection signal Aj1Aj are generated under the control of the external signal RPC, and then the division operation control signal RPC and the array selection signal Aj1Aj are generated based on the array selection signal AjSAj. Word line drive signal RXSRX and sense amplifier activation signal 5
ISSt is generated.

While the division operation control signal RPC is at a low level, one of the division operation word line drive signals RX, RX and sense amplifier activation signals S1, S is at a high level and the other is at a low level. When the address counter completes one cycle, only one of the divided memory cell arrays is refreshed. Subsequently, when the address counter completes one cycle, the remaining memory cell array is refreshed. In other words, since refresh is performed in parts, the peak current at that time is reduced.

<Embodiment> FIG. 1 is a configuration diagram of a memory cell array of a dynamic RAM of the present invention. This dynamic RAM has divided operation word drive signals RX, RX, which will be described later for the row decoders 2a and 2b, and a divided operation sense amplifier activation signal S3, which will be described later for the MOS transistors 6a and 6b. This differs from the conventional example in that each St is input.

FIG. 2 is a configuration diagram of an address counter for auto-refresh according to the present invention. In this address counter 9, a flip-flop 10j is added for one high-order bit, and the count output from Q0 to Qi is used as a refresh address as before, and the output of the most significant bit Qj is used as an array selection signal AjSAj to be described later. are used to generate each. The other configurations are the same as the conventional example shown in FIG.

FIG. 3 shows the division operation transition signal R in the refresh mode.
This is a signal generation circuit activated by the PC to control the division operation, and is formed on the same chip as the dynamic RAM.

In the figure, reference numeral 10 denotes a division operation control signal generation circuit that generates a division operation control signal RPC, which is the level of the refresh transition signal REF inverted, based on the division operation transition signal RPC and refresh transition signal REF applied from the outside during the refresh mode. A plurality of MOS transistors connected in series and a NAND circuit 1
It consists of 3.

Reference numeral 15 denotes a latch output Qja obtained by latching the above-mentioned division operation control signal RPC and the output of the most significant bit Qj of the address counter 9 by an address buffer not shown.
, Qja is an array selection signal generation circuit that generates array selection signals Aj, Aj based on two NOR circuits 16.
Consists of 17.

19 is a word line drive signal R for division operation based on the above array selection signal AjSAj and word line drive signal RX.
X,,RX! This is a word line drive signal generation circuit for divided operation that generates two inverters 20 and 21 and two NO
It is composed of R circuits 22 and 23.

Reference numeral 25 denotes a sense amplifier activation signal generation circuit for division operation which generates sense amplifier activation signals Sl and St for division operation based on the above-mentioned array selection signal AjSAj and sense amplifier activation signal S, and includes two inverters 26. .27, two NOR circuits 28, and a circuit 9.

Next, the operation of the dynamic RAM of the present invention having the above configuration will be explained with reference to the timing chart shown in FIG.

In refresh mode, CAS before
RAS, a refresh transition signal REF is generated, and a counter decrement signal CD.

Word line drive signal RX and sense amplifier activation signal S
is generated at a predetermined timing, and Q of the address counter 9 is generated at a predetermined timing. The point that the row address is specified by the count output up to -Qi is the same as in the conventional case, so the explanation thereof will be omitted.

In the dynamic RAM of the present invention, a high-level division operation transition signal RPC and a refresh transition signal RBF are input from the outside.
is applied to the divided operation control signal generation circuit IO. The division operation transition signal RPC is set to a specified voltage (for example, power supply voltage Vcc).
, ), the NAND circuit 13 is turned on. Next, when the refresh transition signal REF becomes high level (time t+), the NAND circuit 13 outputs a low level division operation control signal RPC synchronized with the refresh transition signal REF.
is output. This allows the reduced peak current mode according to the present invention to be
mode).

When entering this mode, the array selection signal generation circuit 15 outputs a signal Q jalQ ja obtained by latching the count output Qj of the most significant bit of the address counter 9 and a division operation control signal RPC, one of which is set to a high level and the other of which is set to a high level. Low level array selection signals Aj, Aj are generated. This array selection signal AjSAj is commonly input to the word line drive signal generation circuit 19 for division operation and the sense amplifier activation signal generation circuit 25 for division operation at the next stage.

At this time, when the word line drive signal RX is applied to the division operation word line drive signal generation circuit 19 (time 11), the high level division operation word is output from the NAND circuit 22 into which the low level array selection signal Aj is manually input. Line drive signal RX,
However, the NAN where the high level array selection signal Aj is manually input is
Each of the D circuits 23 outputs a low-level word line drive signal RX for division operation. These divided operation word line drive signals RX1. RX, is input to the row decoders 2a, 2b shown in FIG. only have a high level.

In addition, the sense amplifier activation signal generation circuit 25 for divided operation
When the sense amplifier activation signal S is applied to (time t,
), NAN to which low-level array luck signal Aj is input
A high level sense amplifier activation signal Sl for division operation is output from the D circuit 28, and a low level sense amplifier activation signal St for division operation is output from the NAND circuit 29 to which a high level array selection signal Aj is input. Ru. These divided operation sense amplifier activation signals S1, S
, are input to the MOS transistors 6a and 6b shown in FIG. 1, so only the sense amplifiers connected to the left word lines wt and L are activated. Therefore, the memory cells connected to this word line WLk are refreshed.

Then, as in the conventional case, the word line drive signal RX for division operation is
, becomes high level, input of the counter decrement signal CD to the address counter 9 is allowed.

In this way, the count output Q of the address counter 9
When 0 to Qi complete one cycle, all the memory cell arrays 1a on the left side shown in FIG. 1 are refreshed. Then, the level of the count output Qj of the most significant bit of the address counter 9 is inverted. After that, the counter output Q of the address counter 9 is obtained in the same manner as above. The right memory cell array 1b is all refreshed until -Qi completes one cycle.

To refresh all memory cell arrays 1a and lb, twice the number of refresh cycles is required compared to the conventional one, but the refresh current in one refresh cycle is 1/2 of the conventional one. peak current is reduced.

Note that, in order to return from the auto-refresh in the low peak current mode to the auto-refresh in the normal CA Sr before RA S mode, the division operation transition signal RPC is made floating or set to a low level. Then, the division operation control signal RPC becomes high level and the array selection signals Aj1Aj both become low level invalid data, so AS before RA is the same as before.
S refresh is realized.

In the above embodiment, the memory cell array 1a1 lb is 2
Although an example of dividing into two blocks has been described, the invention is not limited to this, and the present invention can be applied to any division into an even number of blocks. Furthermore, in this example, the CAS
Although the before RAS refresh mode has been described, a similar effect can be achieved if the refresh is performed in which the column system is inactive (the column system is not selected and only the row system is operated).

To input the division operation transition signal RPC, an external address pin may be used if an address counter for auto-refresh is used, or an external R/W, Din pin may be used if the column system is refreshed in a non-operating manner. . In that case, it is possible to configure a signal generation circuit shown in FIG. 3 in which the internal signal becomes valid when the external signal exceeds the power supply voltage. Also, R/W before CA
A signal generated at a timing such as S before RAS may also be used.

<Effects of the Invention> As described above, according to the present invention, refresh can be performed in divisions under the control of an external signal during the refresh mode, so that the peak current during refresh can be reduced.

As a result, fluctuations in the power supply voltage are prevented and malfunctions can be eliminated.

[Brief explanation of drawings]

Figures 1 to 4 show an embodiment of the present invention, and Figures 5 to 7 show a conventional example. Figure 1 is a configuration diagram of a dynamic RAM memory cell array, and Figure 2 is a diagram of a divided FIG. 3 is a block diagram of an address counter for auto-refresh to perform operations sequentially. FIG. 3 is a signal generation circuit for controlling division operations using external signals in refresh mode. FIG. 4 is a diagram of the operation of an embodiment of the present invention. A timing chart for explanation, FIG. 5 is a conventional dynamic R.
FIG. 6 is a block diagram of an address counter for auto-refresh, and FIG. 7 is a timing chart for explaining the operation of a conventional example. la, lb...memory cell array, 2a, 2b...
Row decoder, 3... Column decoder, 9... Address counter, 10... Division operation control signal generation circuit,
15... Array selection signal generation circuit, 19... Word line drive signal generation circuit for division operation, 25... Sense amplifier activation signal generation circuit for division operation, RPC... Division operation transition signal, RPC.・・Division operation transition signal, REF・
...Refresh transition signal, AjlAj...Array selection signal, RX...Word line drive signal, RX1, RX2
...Word line drive signal for division operation, S...Sense amplifier activation signal, 5ISS1...Sense amplifier activation signal for division operation.

Claims (1)

[Claims] (1) In a dynamic RAM that has a memory array divided into an even number of blocks and is equipped with an address counter for auto-refresh, and whose column system is inactive during refresh mode, the count output of the address counter is divided into the upper 1 bit. a division operation control signal generation circuit that generates a division operation control signal @RPC@, which is a level inversion of the refresh transition signal REF, based on the division operation transition signal RPC and the refresh transition signal REF applied from the outside during the refresh mode; The divided operation control signal @RPC@ and the added latch output of the most significant bit of the address counter Qja, @Q
an array selection signal generation circuit that generates array selection signals Aj, @Aj@ based on the array selection signals Aj, @Aj@ and a word line drive signal for division operation based on the array selection signals Aj, @Aj@ and the word line drive signal RX; RX_1
, RX_2, and generates sense amplifier activation signals S_1 and S_2 for the division operation based on the array selection signals Aj, @Aj@ and the sense amplifier activation signal S. A dynamic RAM comprising: a sense amplifier activation signal generation circuit for divided operation;