JPS6310517B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device with increased data output buffer speed.

(2) Prior art and problems Generally, in a MOS static type semiconductor memory device, a static type memory cell configured as a flip-flop is provided at each intersection of a word line and a bit line pair, and a row address buffer, a row address decoder, column address buffer,
1 by addressing means such as a column address decoder.
one memory cell is selected. In the read mode, the potential difference between the bit line pair connected to the selected memory cell is sensed or amplified by the sense amplifier, and then the data output is sent to the outside via the output buffer.

However, recently, the degree of integration of semiconductor memory devices has increased, and as a result, the current flowing through the selected memory cell has become smaller, but the output load capacity has been relatively large, so there has been a problem in that high-speed reading cannot be expected. .

(3) Purpose of the Invention The purpose of the present invention is to focus on the fact that the change from low level to high level is slower than the change from high level to low level in the data output of the output buffer, and to temporarily stop the data output when the address changes. The object of the present invention is to increase the read speed by obtaining the original valid data output after the data is held at a high level, thereby solving the problems in the conventional type described above.

(4) Structure of the invention In order to achieve the above-mentioned object, according to the present invention,
The present invention is characterized by comprising a clamping means for clamping the level at the output end of the output buffer circuit which outputs the information of the selected memory cell sensed by the sense amplifier to the outside at a high level for a certain period of time immediately after the input address signal changes. A semiconductor memory device is provided.

(5) Examples of the invention The present invention will be explained below with reference to the drawings.

FIGS. 1A to 1C are timing diagrams for explaining the read operation of a conventional static type semiconductor memory device. Figure 1A shows potential change of address ADD.
Figure 1B shows the potential change of the sense data SD of the sense amplifier, and Figure 1C shows the data output of the output buffer.
Indicates the potential change of D _OUT . That is, at time t ₀ , the address ADD potential changes, and then at time t ₁
The sense data SD is generated by the sense amplifier at
The potential of changes. Of course, in this case, even if the address ADD changes, the potential of the sense data SD will not change if the data is the same. When the potential of the sense data SD changes, the potential of the data output D _OUT of the output buffer also changes at time _t2 , but
When the output load capacitance is large, the change from high level to low level ends at time t ₄ , whereas the change from low level to high level ends later, at time t ₄ '. That is, this difference is based on the difference between the charging operation and discharging operation of the output load capacity. Therefore, the read operation speed depends on the time Δt.

In contrast, in the present invention, the address
After ADD changes, the data output D OUT of the output buffer is held at a high level for a predetermined time regardless of the potential of the sense data _SD of the sense amplifier, and then the potential of the data output D _OUT is changed according to the potential of the sense data SD. is changing.

FIGS. 2A to 2D are timing diagrams for explaining the read operation of the static semiconductor memory device according to the present invention, in which FIG. 2A shows the potential change of the address ADD, and FIG. Figure 2C shows the potential change of the clock pulse signal CP, and the second diagram shows the potential change of the sense data SD of the sense amplifier.
Figure D shows the potential change of the data output D _OUT of the output buffer. That is, as shown in FIG. 2B, a pulse signal CP with a pulse width of a predetermined time T is generated from the potential change time _t0 of address ADD, and using this, as shown in FIGS. 2C and D, sense data
Pushes or holds the output buffer's data output D _OUT to high level regardless of the SD potential.
After this, at time _t2 , the potential of the data output D _OUT changes, but as shown in FIG. 2D, this change occurs only when changing from high level to low level. Therefore, the read operation speed according to the present invention depends on the time Δt' and is therefore faster than in the prior art.

FIG. 3 is a block circuit diagram showing an embodiment of a static type semiconductor memory device according to the present invention.
In FIG. 3, known static type memory cells C _ij (i, j=0, 1, . . . , n-1) are arranged in a matrix of n rows and n columns, and each memory cell has one word and one It is connected to a pair of bit lines.
For example, _memory cell C ₀₀ is connected to word line WL ₀ and bit lines BL _0,0 . word line
WL ₀ , WL ₁ , ......, WL _o-1 is selected by the row selection signal X ₀ , X ₁ , ...... of the row address decoder RD.
In this _case , the row address decoder RD receives the address signals A ₀ , ₀ , A ₁ , ₁ , ......, A _l-1 , _l-1 (2 ^l
=n). Also, the bit line BL ₀ ,
BL ₀ , BL ₁ , ₁ , ......, BL _o-1 , _o-1 are column selection gates Q _B0 , Q _B0 ′, Q _B1 , Q _B1 ′, ......,
Q _B,o-1 , Q _B,o-1 ' are respectively connected, and the selection of each gate pair is controlled by column selection signals Y ₀ , Y ₁ , . . . , Y _o-1 . That is, the bit line pairs are connected to the column selection signals Y ₀ , Y ₁ , . . . of the column address decoder CD.
Y _o-1 , in which case the column address decoder CD decodes the address signals A ₀ ′, ₀ ′, ………, A _l-1 ′, _l-1 ′ of the column address buffer CB. . The bit line pair is connected to the data bit line DB through the selected column selection gate. A sense amplifier SA is connected to the data bit line DB, and an output buffer OB is further connected to the subsequent stage.

PG is a clock pulse generation circuit added according to the present invention, which generates address signals A ₀ , A ₁ , . . .
. . , A _{l- 1} , A ₀ ′, . When the potential of the clock pulse signal CP is high level, the output buffer is
The OB data output D _OUT is set to high level.

Next, the clock pulse generating circuit PG will be explained with reference to FIGS. 4, 5, and 6.

Figure 4 shows the clock pulse generation circuit PG of Figure 3.
FIG. As shown in Figure 4,
The pulse generation circuit PG generates each address signal A ₀ , A ₁ ,...
......, A _l-1 , A ₀ ′, A ₁ ′, ......, For A _l-1 ′, the clock pulse generation circuit PG ₀ , PG ₁ , ......,
It has PG ₀ ′, PG ₁ ′, ......, PG _l-1 ′. Therefore, if any one address signal, for example address signal _A0 , changes, the clock pulse generating circuit _PG0 will generate the clock pulse signal CP via the OR gate OR. That is, when the selected memory cell in FIG. 3 changes, the clock pulse generation circuit PG will generate the clock pulse signal CP.

Figure 5 shows the clock pulse generation circuit PG of Figure 4.
FIG. 2 is a detailed logic circuit diagram of one of the clock pulse generation circuits PG _i . In FIG. 5, G ₁ to _{G 4} are NAND gates, G ₅ and G ₆ are Noah gates, G ₇ is an OR gate, and C ₁ and C ₂ are capacitors. The operation will be explained with reference to FIG. 6. As shown in FIG. 6, the address signal A _i (node a) is "1", "0",
, the output b of NAND gate _G1 becomes the sixth
As shown in FIG. 2, the output d of the NAND gate _G2 becomes an inverted signal slightly delayed by the capacitor _C1 , as shown in FIG. As a result, the output f of the NOR gate _G5 is as shown in FIG.
This is a pulse generated at the rising edge of address signal A _i . The Nand Gate G ₃ , G ₄ , Capacita C ₂ , and Noah Gate G ₆ systems are similar, but the Nand Gate
The output g of _G6 is a pulse generated at the falling edge of the address signal _Ai , as shown in FIG. 6 and FIG. Therefore, as shown in FIG. 6, the output CP _i of the OR gate G ₇ which is a combination of the signals f and g is the address signal A _i
This is a clock pulse signal that occurs when .

FIG. 7 is a circuit diagram of the output buffer OB of FIG. 3. In FIG. 7, sense data SD is supplied to an inverter I1 composed of a depletion type transistor _Q1 and an enhancement type transistor _Q2 , and sense data is supplied to an inverter _I1 composed of a depletion type transistor _Q3 and an enhancement type transistor _Q4 . Inverter I ₂
supplied to Also, the output of inverter I ₁ is the circuit
I ₃ is connected to the charging transistor Q ₅ and the inverter
The output of I ₂ is connected to the discharge transistor Q ₆ of circuit I ₃ . Furthermore, according to the present invention, the inverter
A transistor _Q7 is connected to the input side of _I1 , and a transistor _Q8 is connected to the output side of the inverter _I2 . These transistors Q ₇ and Q ₈ receive the clock pulse signal of the clock pulse generation circuit PG (Figure 3).
It is controlled by CP.

First, the case where the clock pulse signal CP is at a low level will be described. The potential of the sense data SD is inverted by the inverter _I1 , and the potential of the sense data is inverted by the inverter _I2 . Therefore, normally, one of the sense data SD is at a high level and the other is at a low level, so one of the transistors Q ₅ and Q ₆ is in an on state and the other is in an off state. For example, if transistor Q ₅ is on, the data output D _OUT becomes high level due to the charging operation of transistor Q ₅ , and on the other hand,
If the transistor Q ₆ is on, the data output D _OUT becomes low level due to the discharging operation of the transistor Q ₆ . That is, the potential of the data output D _OUT follows the potential of the sense data SD.

When the clock pulse signal CP is at a high level, transistor _Q7 is turned on, and as a result,
The input of the inverter _I1 is at a low level, and therefore its output is at a high level, turning on the charging transistor _O5 . In other words, sense data SD
Charging transistor _Q5 is turned on regardless of the potential of Q5. At the same time, transistor _Q8 is also turned on, so the output of inverter _I2 becomes low level,
Discharge transistor _Q6 is turned off. In other words,
The discharge transistor _Q6 is turned off regardless of the potential of the sense data. After all, sense data SD,
The data output D _OUT will be at high level regardless of the potential of .

In this way, in the output buffer OB of FIG. 7, the clock pulse signal CP shown in FIG.
When the potential of the sense data SD shown in FIG. 2C is applied, the data output D _OUT has the waveform shown in FIG. 2D.

It should be noted that although the above description has been made using a static type memory as an example, the scope of application of the present invention is not limited to static type memories.

(6) Effects of the Invention As explained above, according to the present invention, the readout speed is faster than that of the conventional type.

[Brief explanation of the drawing]

1A to 1C are timing diagrams for explaining the read operation of a conventional static type semiconductor memory device, and FIGS. 2A to 2D are timing diagrams for explaining the read operation of the static type semiconductor memory device according to the present invention. 3 is a block circuit diagram showing an embodiment of the static semiconductor memory device according to the present invention, FIG. 4 is a block circuit diagram of the clock pulse generation circuit of FIG. 3, and FIG. 5 is a block circuit diagram of the clock pulse generation circuit of FIG. 4. One clock pulse generation circuit in the generation circuit
A detailed logic circuit diagram of PG _i , Figures 6, 1 to 8 are timing diagrams for explaining the circuit operation of Figure 5, and Figure 7 is a detailed logic circuit diagram of PG i.
The figure is a circuit diagram of the output buffer of FIG. 3. C ₀₀ ~ _{C o-1,o-1} : static memory cell,
WL ₀ , WL ₁ , ......, WL _o-1 : Word line, BL ₀ ,
BL ₀ , ......, BL _o-1 , _o-1 : Bit line, RD:
Row address decoder, RB: Row address buffer, CD: Column address decoder, CB: Column address buffer, SA: Sense amplifier, OB: Output buffer, PG: Clock pulse generation circuit, CP: Clock pulse signal.

Claims (1)

[Claims] 1. The present invention is characterized by comprising a clamping means for clamping the level at the output end of the output buffer circuit which outputs the information of the selected memory cell sensed by the sense amplifier to the outside at a high level for a certain period of time immediately after the input address signal changes. semiconductor storage device.