JP2845187B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a function of simultaneously inputting / outputting a plurality of bits of data in parallel.

[0002]

2. Description of the Related Art Generally, a semiconductor memory device can simultaneously input / output a plurality of bits, for example, one of 4, 8, 16, or 32 bits in parallel as a data unit, depending on an upper system to which the semiconductor memory device is applied. In many cases, there is provided a memory cell array in which a plurality of addresses are arranged with such a plurality of bits of data as one address.

In such a semiconductor memory device, a plurality of memory cells are arranged in a row direction and a column direction in a memory cell array, and one row is selected by a row address signal and selected by a column address signal. A plurality of memory cells (a plurality of bits) which are simultaneously input / output in parallel in one row are selected to input / output data. here,
When memory cells for one row are selected by the row address signal, the bit lines corresponding to these memory cells are charged and discharged in accordance with the data of the memory cells, and these bit lines correspond to the data of the memory cells. Level. Therefore, when the number of addresses (memory capacity) increases, the number of memory cells in one row increases, the power consumption by the charging and discharging of the bit line at the time of selection increases, and the operating speed also decreases.

Therefore, in order to reduce power consumption and increase operating speed, recently, many semiconductor memory devices have been proposed in which a memory cell array is divided into a plurality of units so as to be operated in a divided manner (eg, for example). JP-A-58-2113
93).

FIG. 4 shows an example of a general semiconductor memory device in which a memory cell array is disassembled into a plurality of parts to perform a division operation.

The semiconductor memory device has a plurality of memory cells MC arranged in a predetermined number in a row direction and a column direction, and is provided corresponding to each row of the plurality of memory cells MC. And a plurality of block word lines BW1x to BWmx for selecting a memory cell of a selected state, and a plurality of block word lines BW1x to BWmx provided for each column of a plurality of memory cells MC and transmitting data of a selected state of the memory cell in the corresponding column. First and second bit lines BL11, BL12
.., BLn2,..., And one row corresponding to each of the memory blocks (MB1x, MB2x,...). A plurality of word lines WL1 to WLm provided at a ratio and a row address signal R
AD, one of a plurality of word lines WL1 to WLm.
The row selection circuit 1 having a book selection level and memory block selection signals (BS1, BS2) provided corresponding to the respective memory blocks (MB1x, MB2x,...).
When a plurality of block row selection circuits (BRSs) select a word line at a selected level of a corresponding memory block and a corresponding block word line as a selected level when (2,.
1, BRS2,...) And a memory block (MB1
x, MB2x,...) provided for each of the plurality of first and second bit lines BL11, BL12 to BLn1, BLn2 of the corresponding memory block at a predetermined timing in accordance with the precharge control signal PCC. A plurality of precharge circuits (P1x, P2x,...)
.), A column decoder 5 that decodes a column address signal CAD to generate a column selection signal CSS, and a corresponding memory block selection signal provided corresponding to each of the memory blocks (MB1x, MB2x,...). A plurality of column switch circuits (CS1, SC2,...) For connecting predetermined first and second bit lines of the corresponding memory block to the data bus 4 in accordance with the column selection signal CSS when the level is at the level. ing.

In this semiconductor memory device, as shown in FIG. 5, each memory cell MC is connected to transistors Q1-Q
4 and a flip-flop circuit composed of resistance elements R1 and R2, and a precharge circuit Pkx
(K = 1, 2,...) Are connected to the first and second bit lines BLj1, BLj2 (j =
1 to n) to supply the power supply potential Vcc.

Next, the operation of the semiconductor memory device will be described.

First, the row selection circuit 1 sets one of the plurality of word lines WL1 to WLm (for example, WL1) to a selection level by the row address signal RAD. In addition, the memory block (M
B1x, MB2x,...)
L11 and BL12 to BLn1 and BLn2 are changed to the power supply potential Vc.
Precharge to the c level.

Subsequently, a block selection signal (BS1, BS
When one of (2,...) (For example, BS1) becomes the selection level, the block selection signal (BS1) of the selection level
And the block word line (BW) corresponding to the word line (WL1) of the selected level of the memory block (MB1x) corresponding to
1x) is at the selection level by the block row selection circuit (BRS1), and the memory cells MC connected to this block word line (BW1x) are in the selected state. Then, the first and second bit lines BL11 and BL12 to BLn1 and BLn2 are charged / discharged by the data level of the memory cells MC in one row, and the bit lines have a level corresponding to the data level of the memory cells MC.

Subsequently, the column decoder 5 supplies a column address signal CA
D is decoded to generate a column selection signal CSS, and the column switch circuit (CS1) corresponding to the block selection signal (BS1) at the selected level is activated, and the first and second bit lines BL11, BL11, BL12 to BLn1,
A predetermined bit line is selected from BLn2 and connected to the data bus 4. The number of the first and second bit lines connected to the data bus 4 is the same as the number of bits of data that are simultaneously input / output in parallel, and is usually one of the above-described 4 to 32 bits, for example, It is fixed to 8 bits.

In this semiconductor memory device, the precharge of the first and second bit lines BL11 to BL12 to BLn1 and BLn2 is controlled by a precharge control signal PCC. The power supply potential VCC is always supplied to the gates of Q5 and Q6, and these transistors Q5 and Q6 are connected to the first and second transistors.
In many cases, the load element of the bit line is used.

[0013]

In the conventional semiconductor memory device described above, the memory cell array is divided into a plurality of memory blocks (MB1x, MB2x,...), And one of the plurality of memory blocks is selected by block selection. Signal (BS1, BS2,...)
After selecting one row of the memory block , a predetermined number of memory cells (bit lines) (the same number as the number of bits of data to be simultaneously input / output in parallel) are selected from the memory cells in this row. Therefore, although the power consumption is reduced and the operation speed is increased by the division of the memory cell array, the memory corresponding to the data to be simultaneously input / output in parallel is included in the selected one row of the selected memory block. A large number of memory cells other than the cell are also included, and the data of all the memory cells in one row including these memory cells are first and second cells.
Since the second bit line is charged / discharged, there is still a problem that much power is wasted. Further, since the bit lines of each memory block are simultaneously controlled by the precharge control signal (PCC), an unselected memory cell is not selected. Since the bit line of the block is also pre-charged, the power consumption by the bit line pre-charge is large. Even if only the selected memory block is pre-charged in the same way as the memory cell selection, simultaneous parallel input / output Since the bit lines corresponding to data other than the data to be precharged are also precharged, there is still a problem that a large amount of power is wasted. Is limited.

An object of the present invention is to provide a semiconductor memory device capable of reducing power consumption by eliminating waste of power consumption during data reading and writing operations and expanding the applicable range.

[0015]

According to the present invention, there is provided a semiconductor memory device having a plurality of memories arranged in the same number as the basic number of bits of data simultaneously input / output in parallel in the row direction and a predetermined number in the column direction. A plurality of cell blocks each including a cell and a plurality of bit lines provided corresponding to each column of the plurality of memory cells and transmitting data of a selected memory cell in the corresponding column; and the plurality of cell blocks. And decodes a selected block address signal having information on the block address corresponding to and the number of cell blocks to be selected simultaneously including one and a plurality of cells, and simultaneously selects a predetermined number of cell blocks from the plurality of cell blocks. A cell block selecting circuit for selecting one row of each of a predetermined number of cell blocks selected by the cell block selecting circuit. Te and selecting a memory cell of the row formed so as to parallel input and output data of the memory cells at the same time.

Also, each of the plurality of cell blocks includes a plurality of block word lines provided corresponding to each of the rows of the cell blocks and selecting a memory cell of the corresponding row at a selected level. A plurality of word lines provided at a ratio of one to one corresponding block word line, and a row in which one of the plurality of word lines is selected according to a row address signal. A selection circuit, provided in correspondence with each of the plurality of cell blocks, and a plurality of cells, when a corresponding cell block is selected, selecting a block word line corresponding to the selected word line at the selected level of the selected cell block; And a plurality of bit lines of a cell block selected from the plurality of cell blocks by a predetermined data. A bus interface circuit connected to a data bus having a data width of the selected cell block for simultaneously performing parallel input / output control of data of a memory cell in a selected row of the selected cell block. When a corresponding cell block is selected, a plurality of precharge circuits are provided for precharging a plurality of bit lines of the selected cell block at a predetermined timing.

The information on the number of cell blocks to be selected at the same time is information including one, a plurality, and all, and a plurality of cell blocks corresponding to all of the information on the number are regarded as one memory block. A plurality of memory blocks are provided, and a memory block selection circuit for selecting one of the plurality of memory blocks is provided, and a selected one of the memory blocks selected by the memory block selection circuit is selected. The data of the memory cells in a row are simultaneously input / output in parallel. Further, one row address signal is provided for each of a plurality of cell blocks of a plurality of memory blocks. And a plurality of word lines each having a selection level according to the following. A selected number of cell blocks of the plurality of cell blocks are selected through a memory block selection circuit, and a word line at a selected level among the plurality of word lines of the cell block selected through the memory block selection circuit. The memory cells in the corresponding row are selected and the data of these memory cells are simultaneously input / output in parallel.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, the same number of bits (8 in FIG. 1) as the basic number of bits of data to be input and output simultaneously in parallel in the row direction
A plurality of memory cells MC arranged in a predetermined number (m in FIG. 1) in the column direction, and a memory cell MC provided in correspondence with each row of the plurality of memory cells and in the corresponding row at the selection level. A plurality of block word lines BW1 to BWm to be in a selected state, and a memory cell M provided in correspondence with each of a plurality of columns and in a selected state of a corresponding column
C and a plurality of first and second bit lines B for transmitting data of C
Each of a plurality (4) of cell blocks CB1 to CB4 including L11, BL12 to BL81, and BL82, and one block word line (for example, BW1) corresponding to each of the cell blocks CB1 to CB4.
Word lines WL1 to WLm provided at a ratio of
And a plurality of word lines WL according to a row address signal RAD.
1 to WLm as a selection level, and a corresponding cell block selection signal (CBS1 to CBS1C) provided corresponding to each of the cell blocks CB1 to CB4.
When BS4) is at the select level, a plurality of block row select circuits CBRS1 to CBRS1 to select the block word line corresponding to the select level word line of the corresponding cell block as the select level.
The cell block selection signal CBS1 is decoded by decoding the BRS4 and the selected block address signal SBA having the information of the block address corresponding to each of the cell blocks CB1 to CB4 and the information of the number of cell blocks to be simultaneously selected including one, plural and all. To CBS4, a predetermined signal is selected as a selection level, and active of precharge control signal PCC when cell block selection signals provided corresponding to cell blocks CB1 to CB4 are at the selection level, respectively. In response to the level, the first and second bit lines BL11, B of the corresponding cell block
Precharge control circuits PC1 to PC4 for precharging L12 to BL81 and BL82 and a precharge circuit P
1 to P4 and the first and second bit lines BL11, B of the cell block corresponding to the cell block selection signal of the selection level.
The bus interface circuit 3 connects the L12 to BL81 and BL82 to the data bus 4.

The cell block selection circuit 2 is, for example, as shown in FIG.
As shown in (A), AND gates AG1 to AG7 and O
R gates OG1 to OG4 are provided and 3 bits (SBA0
To SBA2), and outputs cell block selection signals CBS1 to CBS4. The selected block address signal SBA and the cell block selection signal CBS1 by the cell block selection circuit 2
2B is as shown in FIG. 2B, and the most significant bit S of the selected block address signal SBA is
When BA2 is “1”, the lower 2 bits SBA0 to SBA
At BA1, one of the cell block selection signals CBS1 to CBS4 is set to a selection level ("1"), and when the upper two bits (SBA2, SBA1) are "01", the least significant bit SBA0 is used as the cell block selection signal. Two signals of one set of two sets (CBS1, CBS2 / CBS3, CBS4) of two sets are simultaneously set to the selection level, and when the upper two bits are "00", the least significant bit is "1". If all the cell block selection signals are set to the selection level and "0"
In the case of, all are set to non-selection level.

Next, the operation of this embodiment will be described.

First, the most significant bit SBA2 of the selected block address signal SBA is set to the "1" level, and the number of bits of data which is selected one by one and simultaneously input / output in parallel is set to the basic number of 8 bits. The operation at that time will be described.

Assuming that the selected block address signal SBA is, for example, "100", the cell block selecting circuit 2 decodes this and outputs the cell block selecting signals CBS1 to CBS4.
Only the CBS1 is selected as the selection level. That is,
Only the cell block CB1 is selected.

When the precharge control signal PCC changes to the active level, the cell block selection signal C of the selected level is set.
By the precharge control circuit PC1 and the precharge circuit P1 corresponding to BS1, the first and second bit lines BL11, BL12 to BL81, B of the cell block CB1 are provided.
L82 is precharged.

Subsequently, the row address signal RAD is decoded by the row selection circuit 1, and one of the word lines WL1 to WLm (for example, WL1) is set to the selection level. Then, the cell row CB1 corresponding to the word line (WL1) of the selected level is set by the block row selection circuit CBRS1.
Of the block word line (BW1) at the selected level, the eight memory cells MC connected to the block word line (BW1) are in the selected state, and at the time of the read operation, the first and second bits of the cell block CB1 are read. Line BL11, BL
12 to BL81 and BL82 are charged and discharged in accordance with the level of the storage data of these memory cells MC, and have a level corresponding to the storage data.

In response to the cell block selection signal CBS1 at the selected level, the bus interface circuit 3 provides the first and second bit lines BL11, BL of the corresponding cell block CB1.
L12 to BL81 and BL82 are connected to the data bus 4,
At the time of the read operation, the data of the first and second bit lines at a level corresponding to the data stored in the memory cell MC are simultaneously output to the outside through the data bus 4 in parallel. At the time of a write operation, external write data input through the data bus 4 is transmitted to the first and second bits to perform charging and discharging, and write to the corresponding memory cell MC.

As described above, when the number of bits of data that are simultaneously input / output in parallel is the basic number of 8 bits, one cell block is selected, and then all memory cells in one row of this cell block are selected. Data is read and written as the status.

When the number of bits of data input / output simultaneously in parallel is 16 bits, which is twice the basic number of bits, the upper bit of the selected block address signal SBA is set to "01" and the four cell blocks CB1 are set. ~ CB4
(CB1, CB2 / CB3, CB4)
Is selected, and the selected two cell blocks (for example, CB
1, CB2) Data is read and written with all memory cells in one row selected.

Further, when the number of bits of data that is simultaneously input / output in parallel is 32, which is four times the basic number of bits, the selected block address signal SBA is set to "001".
, All four cell blocks CB1 to CB4 are selected, and all the memory cells in one row of each of these four cell blocks are selected to read and write data.

In the first embodiment, when reading and writing data, only the same number of memory cells MC as the number of bits of data that are simultaneously input / output in parallel are set to the selected state. Only the corresponding bit line is charged and discharged by storage data or externally-written data, and precharging of the bit line at the time of read operation is the same. It is possible to eliminate waste of power consumption required for charging / discharging the wire and reduce power consumption.

The number of bits that are simultaneously input / output in parallel by the selected block address signal SBA is 8 bits.
Since it is possible to switch between 16 bits and 32 bits, the number of bits can be switched according to the specifications of the host system, and the applicable range can be expanded.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

The second embodiment is different from the first embodiment in that the cell blocks CB1 to CB4, the block row selection circuits CBRS1 to CBRS4, the precharge circuit P1
To P4 and a plurality of memory blocks (MB1, MB2,.
..), and the row selection circuit 1 and the plurality of word lines WL
1 to WLm are assigned to these memory blocks (MB1, M
B2,...), And the cell block selection circuit 2 is connected to the plurality of memory blocks (MB
, MB2,...) And the cell block selection signal CBS (CBS1 to CBS1) from the cell block selection circuit 2.
CBS4) into memory blocks (MB1, MB2,...)
..) Memory block selection signals (MBS1, MBS2,...) Corresponding to the memory blocks (MB1, MB2,...) Through memory block selection circuits (MBSC1, MBSC2,. ) Is transmitted to the corresponding memory block only when it is at the selection level, and the bus interface circuit 3a is connected to the cell selected by the cell block selection signal CBS transmitted through the memory block selection circuit (MBSC1, MBSC2,...). Block bit lines (BL11, BL1
2 to BL81, BL82) to the data bus 4.

In the second embodiment, one of a plurality of memory blocks (MB1, MB2,...)
One is a memory block selection signal (MBS1, MBS2,
...). Operations and effects such as data reading and writing operations for the selected memory block and switching of the number of bits of data input / output simultaneously in parallel are the same as in the first embodiment.

The second embodiment is suitable for a semiconductor memory device having a large memory capacity because the number of memory cells connected to one word line can be increased.

In the second embodiment, one of the memory blocks is selected by the memory block selection circuit (MBSC1, MBSC2,...). The information of the address corresponding to (MB1, MB2,...) Can also be taken in, and the cell block selection circuit can be provided with a memory block selection function. In this case, the memory block selection circuit (MBSC1, MBSC2,...)
Becomes unnecessary.

The present invention is basically applicable whether the memory cell is of a static type as shown in FIG. 5 or a dynamic type of one transistor and one capacitor.

[0039]

As described above, according to the present invention, when reading and writing data, only the same number of memory cells as the number of bits of data that are simultaneously input / output in parallel are set to the selected state. Only the bit lines corresponding to the memory cells are charged / discharged with the stored data or external write data.The precharge of the bit lines during the read operation also corresponds to the data input / output in parallel at the same time. Since the configuration is such that only the bit lines to be used are used, it is possible to eliminate waste of power consumption required for charging and discharging the bit lines and the like during data reading and writing operations, and to reduce power consumption. . Further, since the number of bits of data input / output simultaneously can be switched at the same time, the number of bits can be adjusted to the specifications of the host system, and the range of application can be expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the cell block selection circuit of the embodiment shown in FIG. 1 and a diagram showing a level relationship of input / output signals.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating an example of a conventional semiconductor memory device.

5 is a circuit diagram showing an example of a memory cell of the semiconductor memory device shown in FIG. 4 and peripheral circuits thereof;

[Explanation of symbols]

1 row selection circuit 2 cell block selection circuit 3, 3a bus interface circuit 4 data bus 5 column decoder BL11, BL12 to BL81, BL82, BLn1,
BLn2 Bit line BRS1, BRS2 Block row selection circuit BW1 to BWm, BW1x to BWmx Block word line CB1 to CB4 Cell block CBRS1 to CBRS4 Block row selection circuit CS1, CS2 Column switch circuit MB1, MB2, MB1x, MB2x Memory block MBSC1, MBSC2 Memory block selection circuit MC Memory cell P1 to P4, P1x, P2x Precharge circuit PC1 to PC4 Precharge control circuit WL1 to WLm Word line

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/40-11/419

Claims (6)

(57) [Claims] 1. A row direction and respectively to the column direction of the predetermined number
And the cell block formed memory cells are arranged, double
A number of said cell blocks, corresponding to said cell blocks
Block address information and number of cell blocks to select
Of the selected block address signal having
And, a predetermined and a cell block selection circuit for selecting simultaneously cell block number, the cell block one row of cell blocks each predetermined number selected by the selection circuit of the plurality of cell blocks A semiconductor memory device wherein a memory cell of a selected row is selected, and data of the selected memory cell is simultaneously input / output in parallel. 2. A basic view of data input / output simultaneously and in parallel.
A predetermined number of memory cells are arranged in the row direction in the same number as the number of memory cells.
Cells composed of memory cells arranged in the column direction
A block, a plurality of the cell blocks, and the cell block.
Block address information corresponding to the block and select
Selected block address signal having cell block number information
And decodes a predetermined one of the plurality of cell blocks.
Block selection to select a number of cell blocks at the same time
And a circuit selected by the cell block selection circuit.
Select one row of each of the specified number of cell blocks
Select the memory cells in that row, and select the basic number of bits.
Integral data is input / output in parallel at the same time
A semiconductor memory device characterized by the above-mentioned . 3. A cell block corresponding to each row.
And a word line provided in the cell block.
One pair is assigned to one set of the corresponding block word lines.
In accordance with the multiple word lines connected together and the row address signal.
One of the plurality of word lines is selected as a selection level.
Row selection circuit, and each of the plurality of cell blocks
A correspondingly provided block row selection circuit;
The bit line of the cell block is set to a data having a predetermined data width.
A memory for a selected row of the cell block connected to a bus
Bus interface to control cell data in parallel
3. The semiconductor memory device according to claim 1 , further comprising: 4. A plurality of cell blocks corresponding to each of
Selection when the cell block is selected
Multiple bit lines of the cell block
A plurality of precharge circuits <br/> claim 1, further comprising a semiconductor memory device 請 Motomeko 2 or claim 3 wherein the precharge grayed. 5. Information on the number of cell blocks selected simultaneously.
Is the number of information including one, plural and all
One cell block corresponding to all of the information
Multiple memory blocks as memory blocks
First, one of the plurality of memory blocks is selected.
Memory block selection circuit, and the memory block
The selected one of the memory blocks selected by the selection circuit
Claim 1 or claim cell block in the selected row of data in the memory cell were to be parallel input and output at the same time
3. The semiconductor memory device according to 2 . 6. Each of the memory blocks
Cell blocks, one for each set of rows that correspond to each other
The selection level is provided according to the row address signal.
Multiple word lines, and the cell block selection circuit
A plurality of cells of each of the plurality of memory blocks.
Memory block selection of the number of cell blocks in the lock
Through the memory block selection circuit.
The plurality of cell blocks selected through the clock selection circuit.
Row corresponding to the word line of the selected level among the word lines of
Of memory cells, and the data of these memory cells are
6. The semiconductor device according to claim 5, wherein the input and output are performed at the same time.
Storage device.