JP2530125B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Dynamic random access memory (D-RA
The M) clear operation is connected to a high-level power source or a low-level power source, and is performed by a transistor controlled by a signal derived from the dummy word line signal to clear all cell information and 1
Allows clearing cell information corresponding to words.

[Industrial applications]

An object of the present invention is to provide a semiconductor memory device capable of clearing all cell information of a memory and cell information of an arbitrary word.

[Conventional technology]

In a dynamic random access memory (D-RAM) of a semiconductor memory device, an operation of rewriting (clearing) all the contents of the memory device to "0" may be necessary. For example, in a video RAM using D-RAM as a video memory, there are cases where it is desired to erase the screen or a part thereof and rewrite it to another screen.

In that case, generally, a "0" or "1" is written in each memory cell in a normal write mode. However, in that case, it is necessary to scan addresses sequentially and write "0" or "1" in each memory cell, which has a disadvantage that the time required for clearing becomes long.

Therefore, as another method of the related art, as shown in FIG. 2, a high power supply Vcc or a low power supply is provided to each of the bit lines BL and ▲ ▼ of each sense amplifier S / A (hereinafter, bar indicates the inverted signal). One transistor QAB connected to Vss,
Q'AB and each word line WL connected to high-level power supply Vcc 1
Providing individual transistors QAW, transistors QAB, Q'A
It has been proposed to apply a clear signal φc to the gates of B and QAW. In the clearing operation, by raising the clear signal φc to high, all word lines WL are raised to high, all word lines are selected at once, all bit lines BL are low, and all bit lines ▲ ▼ are high. Therefore, information "0" is written in all the memory cells.

In this case, all memory cell information can be cleared at one time, but it is necessary to provide an additional transistor QAW for each word line WL to give the decoder side the function of selecting all word lines, which complicates the configuration. . Further, it is desired to erase and rewrite a part of the screen when used for a video RAM, but in the conventional example, a part of the screen cannot be arbitrarily erased.

[Problems to be Solved by the Invention]

Therefore, an object of the present invention is to solve the above-mentioned problems in the clear mode of the conventional D-RAM, to clear all the cell information of the memory, and to store the memory of any word (for example, any row in the video RAM). An object is to provide a semiconductor memory device that can clear cell information.

[Means for solving the problem]

In the present invention, the bit line BL of each sense amplifier,
It is characterized in that one transistor connected to each high-potential power supply Vcc or low-potential power supply Vss is provided in ▼ and is controlled by a signal derived from the signal of the dummy word line.

Therefore, the structure of the present invention is as follows. That is, a dynamic random number provided with a plurality of pairs of bit lines (BL, ▲ ▼) and a plurality of sense amplifiers (S / A) for detecting the potential difference between one and the other of the pair of bit lines (BL, ▲ ▼). In the access memory (D-RAM), a first transistor (Q′ab) that selectively connects one of the potentials of the pair of bit lines (BL, ▲ ▼) to a high-potential power supply (Vcc), The pair of bit lines (BL, ▲
One second transistor (Qab) for selectively connecting the other potential of (▼) to the low-potential power supply (Vss) is provided for each of the sense amplifiers (S / A), and the first transistor (Qab) is further provided. And the second transistor (Q'ab, Q
The control line of ab) is connected to the dummy word line (DW, ▲ ▼) via the switch means responding to the clear signal (φc), and when clearing the cell information, the first signal is transmitted by the clear signal (φc). And a second transistor (Q'ab, Qab) connected to the dummy word line (DW, ▲ ▼) to perform a refresh cycle, as a semiconductor memory device. Have.

[Action]

With the configuration of the present invention, when the clear signal φc is raised to high and one refresh cycle is performed, the cell information becomes
The bit line BL side is the storage “0” and the bit line ▲ ▼ side is the storage “1”. As a result, from the outside, all cell information becomes "0", and all bits can be cleared. Further, when a specific word line WL is selected and the clear signal φc is raised to high, the cell information belonging to the specific word line WL has storage "0" on the bit line BL side and storage "1" on the bit line ▲ ▼ side. From the outside, all bits of the word can be cleared from the outside.

〔Example〕

FIG. 1 shows a circuit main part of a semiconductor memory device as an embodiment of the present invention. In FIG. 1, the memory device itself is a normal D-RAM having memory cells of one transistor and one capacitor type, and word lines WL and bit lines BL, ▲
Sense amplifiers each provided with a memory cell M at the intersection of ▼ and further connected to each bit line BL and one end of ▲ ▼
The S / A is provided, and the information of each bit line BL, ▲ ▼ is output to the outside via the input / output buffer circuit IOB, and the input data from the outside is written.

The memory cell information clearing mechanism, which is a feature of the present invention, has one transistor Q′ab connected to the high-potential power source Vcc and the low-potential power source Vss for the bit lines BL, ▲ ▼ of each sense amplifier S / A. And Qab are provided and controlled by a signal derived from the dummy word line DW or the signal of ▲ ▼. In this embodiment, the gate of the transistor Qab connected to the lower power supply Vss is connected to the dummy word line DW through the clear control transistors Qc and Q'c, and the gate of the transistor Q'ab connected to the higher power supply Vcc. Is connected to the dummy word line ▲ ▼.

The rest of the configuration is the same as the normal D-RAM,
Row decoder (R-DEC), bit line information input / output bus B
US, ▲ transfer gate Q ₁ which controls the output to _{▼, Q 2, Q 3,} ..., Q '1, Q' 2, Q '3, ..., and decodes the column address signal, a column selection transfer gate A column decoder (not shown) for transmitting signals is provided.

In the operation of clearing the memory cell information, first, the clear signal φc is raised to a high level, and a normal refresh cycle is performed. When the word line WL on the bit line BL side is selected, the dummy word line ▲ ▼ rises to high, so when the clear signal φc becomes high, the transistor Q′ab
The high level of the dummy word line ▲ ▼ is transmitted to the gate of, the transistor Q′ab is turned on, the bit line ▲ ▼ is forcibly pulled high, and the sense amplifier S / A becomes low on the bit line BL side. The cell on the bit line BL side is cleared to “0”. On the other hand, if the word line WL on the bit line ▲ ▼ side is selected, the dummy word line
When DW goes high and the clear signal φc goes high, the high level of the dummy word line DW is transmitted to the gate of the transistor Qab via the transistor Qc, each transistor Qab becomes conductive, and the bit line BL goes low (Vss). Then, the sense amplifier S / A is turned so that the bit line ▲ ▼ side becomes high, and information "1" is written in the memory cell on the bit line ▲ ▼ side. As a result, the information of the memory cells becomes the storage "0" on the bit line BL side, the storage "1" on the bit line ▲ ▼ side, and becomes the information "0" of all the memory cells from the external side, and all bits are cleared. it can.

Further, in this embodiment, it is possible to clear the information of any word line. At that time, when a specific word line is selected and the clear signal φc is raised to high, the information of the memory cells belonging to that word line becomes the storage “0” on the bit line BL side and the storage “1” on the bit ▲ ▼ side.
From the outside, all bits of the word can be cleared.

For example, one word line WL is one page in the page mode of the D-RAM, and this embodiment is applied to a video RAM provided with a register for storing information of all bits of each word line corresponding to the word line. Considering this, it becomes possible to erase every arbitrary line of one image.

It should be noted that although the above embodiments show the cell arrangement having the open bit line configuration, it will be apparent that the present invention can be similarly applied to the cell arrangement having the folded bit line configuration.

Further, in the above embodiment, when the memory cell information is cleared, the memory cell information is set to "0" on the bit line BL side and "1" on the bit line ▲ ▼ side. Information “1” on bit line BL side, bit line ▲
It is also possible to set it to “0” on the ▼ side.

〔The invention's effect〕

As described above, according to the present invention, the bit line BL, ▲ ▼ of each sense amplifier is provided with one transistor connected to the high-potential power source or the low-potential power source, and the signal derived from the signal of the dummy word line is provided. And all the memory cell information can be cleared by performing only one refresh cycle, there is no need for a configuration such as selection of all word lines as in the prior art, and there is an advantage that the circuit configuration is simple. In addition, not only clearing all memory cell information but also clearing memory cell information for each word is possible.

[Brief description of drawings]

FIG. 1 is a main part configuration diagram of a semiconductor memory device as an embodiment of the present invention, and FIG. 2 is a main part configuration diagram of a semiconductor memory device as a conventional example. WL …… Word line R-DEC …… Low (row) decoder DW, ▲ ▼ …… Dummy word line BUS, ▲ ▼ …… I / O bus BL, ▲ ▼ …… Bit line M …… Memory cell S / A… Sense amplifier OUB Output buffer Vcc High power supply Vss Low power supply Qab and Q'ab ...... Clearing transistor Qc, Q'c ...... Clear control transistor Q ₁ , Q ₂ , Q ₃ , Q ′ ₁ , Q ′ ₂ , Q ′ ₃ …… Transfer gate IOB …… I / O buffer circuit φc …… Clear signal QAB, Q′AB, QAW …… Transistor

Claims (1)

(57) [Claims] 1. A dynamic random access memory provided with a plurality of pairs of bit lines and a plurality of sense amplifiers for detecting a potential difference between one and the other of the pair of bit lines. A first transistor for selectively connecting a potential to a high-potential power source and a second transistor for selectively connecting the other potential of the pair of bit lines to a low-potential power source are provided for each of the sense amplifiers, one for each sense amplifier.
And the control lines of the first and second transistors are
It is connected to a dummy word line through a switch means that responds to the clear signal, and when clearing cell information, a refresh cycle is performed in a state where the first and second transistors are connected to the dummy word line by the clear signal. A semiconductor memory device characterized by being configured to perform.